Si91845/6
Vishay Siliconix
150-mA Ultra Low-Noise LDO Regulator With Error Flag and Discharge Option
FEATURES
D Ultra Low Dropout—130 mV at 150-mA Load D Ultra Low Noise—30 mV(rms) (10-Hz to 100-kHz Bandwidth) D Out-of-Regulation Error Flag (power good) D Shutdown Control D Only 110-mA Ground Current at 150-mA Load D Fast Start-Up (50 mS) D 1.5% Guaranteed Output Voltage Accuracy D 300-mA Peak Output Current Capability D Uses Low ESR Ceramic Capacitors D Fast Line and Load Transient Response (v 30 ms) D 1-mA Maximum Shutdown Current D Output Current Limit D Si91845: Output, Auto-Discharge in Shutdown Mode D Si91846: Output, No-Discharge in Shutdown Mode D Fixed 1.8, 2.0, 2.2, 2.5, 2.6, 2.7, 2.8, 2.85, 2.9, 3.0, 3.3, 3.5, 3.6, 5.0-V Output Voltage Options D Built-in Short Circuit and Thermal Protection D Reverse Battery Protection D Thin SOT23-6 Package
APPLICATIONS
D Cellular Phones, Wireless Handsets D Noise-Sensitive Electronic Systems, Laptop and Palmtop Computers D PDAs D Digital Cameras D Pagers D MP3 Players D Wireless Modems
DESCRIPTION
The Si91845/6 is a 150-mA CMOS LDO (low dropout) voltage regulator. It is the perfect choice for low voltage, low power applications. An ultra low ground current and ultra fast turn-on make this part attractive for battery operated power systems. The Si91845/6 also offers ultra low dropout voltage to prolong battery life in portable electronics. Systems requiring a quiet voltage source will benefit from the Si91845/6’s low output noise. The Si91845/6 is designed to maintain regulation while delivering 300-mA peak current, making it ideal for systems that have a high surge current upon turn-on. For better transient response and regulation, an active pull-down circuit is built into the Si91845/6 to clamp the output voltage when it rises beyond normal regulation. The Si91845 automatically discharges the output voltage by connecting the output to ground through a 100-W n-channel MOSFET when the device is put in shutdown mode. The Si91845/6 features reverse battery protection to limit reverse current flow to approximately 1-mA in the event reversed battery is applied at the input, thus preventing damage to the IC. The Si91845/6 is available in both standard and lead (Pb)-free packages.
TYPICAL APPLICATION CIRCUIT
Si91845/6
VIN 1 mF 2 GND ERROR 5 1 VIN VOUT 6 51 kW VOUT 1 mF ERROR
SD
3
SD
BP
4 10 nF
Thin SOT-23, 6-Lead
Document Number: 71733 S-40591—Rev. B, 29-Mar-04
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Si91845/6
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings Input Voltage, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −6.0 to 6.5 V ERROR, VSD (See Detailed Description) . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VIN Output Current, IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected Output Voltage, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VIN + 0.3 V Package Power Dissipation, (Pd)b . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 mW Package Thermal Resistance, (qJA)a . . . . . . . . . . . . . . . . . . . . . . . . . 180_C/W Maximum Junction Temperature, TJ(max) . . . . . . . . . . . . . . . . . . . . . . . 150_C Storage Temperature, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 5.5 mW/_C above TA = 70_C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V to 6 V Input Voltage, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VIN CIN = COUT = 1 mF (ceramic) Maximum ESR of COUT: 0.4 W Operating Ambient Temperature, TA . . . . . . . . . . . . . . . . . . . . −40_C to 85_C
SPECIFICATIONS
Test Conditions Unless Specified Parameter
Input Voltage Range Output Voltage Accuracy Line Regulation (VOUT v 3 V) Line Regulation (3.0 V < VOUT v3.6 V) Line Regulation (5-V Version) DVIN DVOUT 100 From VIN = VOUT(nom) + 1 V to VOUT(nom) + 2 V VOUT(nom) From VIN = 5.5 V to 6 V IOUT = 1 mA
d, Dropout V lt D t Voltaged g (VOUT(nom) w 2.6 V) .6
Limits
−40 to 85_C
Symbol
VIN
TA = 25_C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, CIN = 1 mF, COUT = 1.0 mF, VSD = 1.5 V
Tempa
Full
Minb
2 −1.5 −2.5 −0.06 0 0
Typc
Maxb
6
Unit
V %
1 mA v IOUT v 150 mA
Room Full Full Full Full Room Room Full Room Full Room Full Room Full Room Full Room Full Room Full Room Full Full Room Room Room Room
1 1
1.5 2.5 0.18 0.3 0.4
%/V
1 45 50 130 65 190 100 110 110 120 300 30 60 40 30 Document Number: 71733 S-40591—Rev. B, 29-Mar-04 dB 80 90 180 220 100 120 250 300 150 180 200 230 170 200 200 230 mA mV(rms) mA mV
IOUT = 50 mA IOUT = 150 mA IOUT = 50 mA IOUT = 150 mA IOUT = 0 mA IOUT = 150 mA IGND IOUT = 0 mA IOUT = 150 mA IO(peak) eN VOUT w 0.95 x VOUT(nom). tPW = 2 ms VNOM = 2.6 V, BW = 10 Hz to 100 kHz, 0 mA t IOUT t 150 mA f = 1 kHz IOUT = 150 mA f = 10 kHz f = 100 kHz
VIN − VOUT Dropout Voltage Dropout Voltaged, g (VOUT(nom) t 2.6 V, VIN w 2 V) ( )
Ground Pin Currente, g (VOUT(nom) v 3 V) ( )
Ground Pin Currente, g (VOUT(nom) u 3 V) ( ) Peak Output current Output Noise Voltage
Ripple Rejection pp j
DVOUT/DVIN
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Si91845/6
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified Parameter
Dynamic Line Regulation Dynamic Load Regulation Thermal Shutdown Junction Temperature Thermal Hysteresis Reverse current Short Circuit Current
Limits
−40 to 85_C
Symbol
DVO(line) DVO(load) TJ(S/D) THYST IR ISC
TA = 25_C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, CIN = 1 mF, COUT = 1.0 mF, VSD = 1.5 V
Tempa
Room Room Room Room
Minb
Typc
20 25 150 20 1 700
Maxb
Unit
VIN : VOUT(nom) + 1 V to VOUT(nom) + 2 V tr/tf = 2 ms, IOUT = 150 mA IOUT : 1 mA to 150 mA, tr/tf = 2 ms
mV
_C mA mA
VIN = −6.0 V VOUT = 0 V
Room Room
Shutdown
Shutdown Supply Current SD Pin Input Voltage Auto Discharge Resistance SD Pin Input Currentf SD Hysteresis VOUT Turn-On Time ICC(off) VSD R_DIS IIN(SD) VHYST(SD) tON VSD (See Figure 1), ILOAD = 100 mA VSD = 0 V High = Regulator ON (Rising) Low = Regulator OFF (Falling) Si91845 Only VSD = 1.5 V, VIN = 6 V Room Full Full Room Room Full Room 100 0.7 150 50 1.5 0.1 1 VIN 0.4 mA V W mA mV mS
ERROR Output
ERROR High Leakage ERROR Low Voltage ERROR Voltage Threshold ERROR Voltage Threshold Hysteresis ERROR Voltage Threshold ERROR Voltage Threshold Hysteresis IOFF VOL VERROR VHYST(ERROR) VERROR VHYST(ERROR) ERROR v VIN. VOUT in Regulation ISINK = 0.5 mA VOUT Below VOUT(nom)g VOUT Falling, IOUT = 1 mA, VOUT(nom) u 2 V VOUT u 2 V VOUT Below VOUT(nom) VOUT Falling, IOUT = 1 mA, VOUT(nom) t 2 V VOUT t 2 V
g
Full Full Full Room Room Room −2 −4 1.5
1 0.4 −6
mA V
% −10 4
Notes a. Room = 25_C, Full = −40 to 85_C. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-V differential, provided that VIN does not not drop below 2.0 V. e. Ground current is specified for normal operation as well as “drop-out” operation. f. The device’s shutdown pin includes a typical 2-MW internal pull-down resistor connected to ground. g. VOUT(nom) is VOUT when measured with a 1-V differiential to VIN.
TIMING WAVEFORMS
VIN VSD tr v 1 mS
0V
tON VNOM 0.95 VNOM
VOUT
FIGURE 1. Timing Diagram for Power-Up
Document Number: 71733 S-40591—Rev. B, 29-Mar-04
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Si91845/6
Vishay Siliconix
PIN CONFIGURATION PIN DESCRIPTION
Thin SOT-23, 6-Lead
VIN 1 6 VOUT
Pin No.
1 2 3 4
Name
VIN GND SD BP ERROR VOUT
Function
Input supply pin. Bypass this pin with a 1-mF ceramic or tantalum capacitor to ground Ground pin. For better thermal capability, directly connected to large ground plane By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to VIN if unused Noise bypass pin. For low noise applications, a 0.01 mF ceramic capacitor should be connected from this pin to ground. The open drain output is an error flag output which goes low when VOUT drops 4% below its nominal voltage. Output voltage. Connect COUT between this pin and ground.
GND SD
2
5 4
ERROR BP
3
5 6
ORDERING INFORMATION
Part Number
Si91845DT-18-T1 Si91845DT-20-T1 Si91845DT-22-T1 Si91845DT-25-T1 Si91845DT-26-T1 Si91845DT-27-T1 Si91845DT-28-T1 Si91845DT-285-T1 Si91845DT-29-T1 Si91845DT-30-T1 Si91845DT-33-T1 Si91845DT-35-T1 Si91845DT-36-T1 Si91845DT-50-T1 Note: LL = Lot Code
Si91845
Temperature Range Package
Lead (Pb)-Free Part Number
Si91845DT-18-T1—E3 Si91845DT-20-T1—E3 Si91845DT-22-T1—E3 Si91845DT-25-T1—E3 Si91845DT-26-T1—E3 Si91845DT-27-T1—E3 Si91845DT-28-T1—E3 Si91845DT-285—E3 Si91845DT-29-T1—E3 Si91845DT-30-T1—E3 Si91845DT-33-T1—E3 Si91845DT-35-T1—E3 Si91845DT-36-T1—E3 Si91845DT-50-T1—E3
Marking
G0LL H1LL H2LL H3LL H4LL H5LL H6LL H7LL H8LL H9LL H0LL I1LL I2LL I3LL
Voltage
1.8 2.0 2.2 2.5 2.6 2.7 2.8 2.85 2.9 3.0 3.3 3.5 3.6 5.0
−40 to 85_C 40 to 85
Thin SOT23-6 Thin SOT23-6
ORDERING INFORMATION
Part Number
Si91846DT-18-T1 Si91846DT-20-T1 Si91846DT-22-T1 Si91846DT-25-T1 Si91846DT-26-T1 Si91846DT-27-T1 Si91846DT-28-T1 Si91846DT-285-T1 Si91846DT-29-T1 Si91846DT-30-T1 Si91846DT-33-T1 Si91846DT-35-T1 Si91846DT-36-T1 Si91846DT-50-T1 Note: LL = Lot Code www.vishay.com
Si91846
Temperature Range Package
Lead (Pb)-Free Part Number
Si91846DT-18-T1—E3 Si91846DT-20-T1—E3 Si91846DT-22-T1—E3 Si91846DT-25-T1—E3 Si91846DT-26-T1—E3 Si91846DT-27-T1—E3 Si91846DT-28-T1—E3 Si91846DT-285-—E3 Si91846DT-29-T1—E3 Si91846DT-30-T1—E3 Si91846DT-33-T1—E3 Si91846DT-35-T1—E3 Si91846DT-36-T1—E3 Si91846DT-50-T1—E3
Marking
I4LL I5LL I6LL I7LL I8LL I9LL I0LL J1LL J2LL J3LL J4LL J5LL J6LL J7LL
Voltage
1.8 2.0 2.2 2.5 2.6 2.7 2.8 2.85 2.9 3.0 3.3 3.5 3.6 5.0
−40 to 85_C 40 to 85
Thin SOT23 Thin SOT23-6
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Document Number: 71733 S-40591—Rev. B, 29-Mar-04
Si91845/6
Vishay Siliconix
TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED)
0.30 0.15 0.00 −0.15 −0.30 −0.45 −0.60 −0.75 0 25 50 75 100 125 150 Load Current (mA) V OUT (%)
Normalized Output Voltage vs. Load Current
VIN = VOUT(nom) + 1 V
0.4 0.2
Normalized VOUT vs. Temperature
VIN = VOUT(nom) + 1 V IOUT = 0 mA
Output Voltage (%)
−0.0 −0.2 −0.4 −0.6 −0.8 −1.0 −40
IOUT = 75 mA
IOUT = 150 mA
−15
10
35
60
85
Ambient Temperature (_C)
150
GND Current vs. Load Current
VOUT = 3.0 V VIN = 4.0 V
300 250 200 I GND ( m A) 150 100
No Load GND Pin Current vs. Input Voltage
85_C
125 25_C I GND ( m A) 100 −40_C 75 50 50 0 25 50 75 100 125 150 Load Current (mA) 0 2 3 4 5 6 7 Input Voltage (V)
85_C 25_C −40_C
0
Power Supply Rejection
CIN = 1 mF COUT = 1 mF ILOAD = 150 mA VOUT = 3.0 V I SC (mA)
750 725 700
Output Short Circuit Current vs. Temperature
VOUT = 2.6 V
−20
Gain (dB)
−40
675 650
−60 625 −80 10 600 −40
100
1000
10000
100000
1000000
−15
10
35
60
85
Frequency (Hz) Document Number: 71733 S-40591—Rev. B, 29-Mar-04
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Si91845/6
Vishay Siliconix
TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED)
350 300 250 V DROP (mV) 200 150 100 50 0 0 60 120 180 240 300 ILOAD (mA) V OUT (V)
Dropout Voltage vs. Load Current
VOUT = 3.0 V
3.0 2.5 2.0 1.5 1.0 0.5 0.0 0
VIN − VOUT Transfer Characteristic
VOUT = 3.0 V
1
2
3 VIN (V)
4
5
6
350 300 250 V DROP (mV) 200 150 100 50 0 −50
Dropout Voltage vs. Temperature
VOUT = 3.0 V IOUT = 300 mA Dropout Voltage (mV)
400 350 300 250 200 150 100 50 IOUT = 10 mA IOUT = 0 mA 0 1.0
Dropout Voltage vs. VOUT
IOUT = 300 mA
IOUT = 150 mA
IOUT = 75 mA
IOUT = 75 mA
IOUT = 150 mA
IOUT = 10 mA 1.5 2.0 2.5 3.0 VOUT 3.5 4.0 4.5 5.0
−25
0
25
50
75
100
125
150
Junction Temperature (_C)
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Document Number: 71733 S-40591—Rev. B, 29-Mar-04
Si91845/6
Vishay Siliconix
TYPICAL WAVEFORMS
Load Transient Response-1
Load Transient Response-2
VOUT 10 mV/div VOUT 10 mV/div
ILOAD 100 mA/div
ILOAD 100 mA/div
20 ms/div VOUT = 3.0 V COUT = 1 mF ILOAD = 1 to 150 mA trise = 2 msec
20 ms/div VOUT = 3.0 V COUT = 1 mF ILOAD = 150 to 1 mA tfall = 2 msec
LineTransient Response-1
LineTransient Respons-2
VOUT 10 mV/div VOUT 10 mV/div
VIN 2 V/div
VIN 2 V/div
20 ms/div VINSTEP = 4 to 5 V VOUT = 3 V COUT = 1 mF CIN = 1 mF ILOAD = 150 mA trise = 5 msec
20 ms/div VINSTEP = 5 to 4 V VOUT = 3 V COUT = 1 mF CIN = 1 mF ILOAD = 150 mA tfall = 5 msec
Document Number: 71733 S-40591—Rev. B, 29-Mar-04
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Si91845/6
Vishay Siliconix
TYPICAL WAVEFORMS
Output Noise
10
Noise Spectrum
VOUT 200 mV/div
Output Spectral Noise Density
mV
Hz
0.01 4 ms/div VIN = 4 V VOUT = 3 V IOUT = 150 mA CNOISE = 0.01 mF BW = 10 Hz to 100 kHz 10 Hz VIN = 4 V VOUT = 3 V ILOAD = 150 mA CNOISE = 0.01 mF 1 MHz
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Document Number: 71733 S-40591—Rev. B, 29-Mar-04
Si91845/6
Vishay Siliconix
BLOCK DIAGRAM
Si91845/6
VIN Reverse Polarity Protection BP Reference − +
VOUT Thermal Sensor Si91845 Only
Current Limit ERROR SD Shutdown Control
GND
DETAILED DESCRIPTION
The Si91845/6 is a low-noise, low drop-out and low quiescent current linear voltage regulator, packaged in a small footprint Thin SOT23-6 package. The Si91845/6 can supply loads up to 300 mA. As shown in the block diagram, the circuit consists of a bandgap reference, error amplifier, p-channel pass transistor and feedback resistor string. An external bypass capacitor connected to the BP pin reduces noise at the output. Additional blocks, not shown in the block diagram, include a precise current limiter, reverse battery and current protection, and thermal sensor. Thermal Overload Protection The thermal overload protection limits the total power dissipation and protects the device from being damaged. When the junction temperature exceeds 150_, the device turns the p-channel pass transistor off. Reverse Battery Protection The Si91845/6 has a battery reverse protection circuitry that disconnects the internal circuitry when VIN drops below the GND voltage. There is no current drawn in such an event. When the SD pin is hardwired to VIN, the user must connect the SD pin to VIN via a 100-kW resistor if reverse battery protection is desired. Hardwiring the SD pin directly to the VIN pin is allowed when reverse battery protection is not desired. Noise Reduction An external 10-nF bypass capacitor at BP is used to create a low pass filter for noise reduction. The start-up time is fast, since a
Document Number: 71733 S-40591—Rev. B, 29-Mar-04
power-on circuit pre-charges the bypass capacitor. After the power-up sequence the pre-charge circuit is switched to standby mode in order to save current. It is therefore not recommended to use larger bypass capacitor values than 50 nF. When the circuit is used without a capacitor, stable operation is guaranteed. ERROR ERROR is an open drain output that goes low when VOUT is less than 4% of its normal value. To obtain a logic level output, connect a pull-up resister from ERROR to VOUT or any other voltage equal to or less than VIN. ERROR pin is high impedance (off) when SD pin is low. Auto-Discharge/No-Discharge VOUT has an internal 100-W (typ.) discharge path to ground when SD pin is low. This applies only to the Si91845. The Si91846 does not have a discharge path when the SD pin is low. Stability The circuit is stable with only a small output capacitor equal to 6 nF/mA (= 1 mF @ 150 mA). Since the bandwidth of the error amplifier is around 1−3 MHz and the dominant pole is at the output node, the capacitor should be capacitive in this range, i.e., for 150-mA load current, an ESR
