SI9430DY

SPICE Device Model Si9430DY Vishay Siliconix P-Channel 30-V (D-S) MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70512 01-Jun-04 www.vishay.com 1 SPICE Device Model Si9430DY Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Currenta VGS(th) ID(on) VDS = VGS, ID = −250 µA VDS = −5 V, VGS = −10 V VDS = −5 V, VGS = −4.5 V VGS = −10 V, ID = −5.3 A Drain-Source On-State Resistancea rDS(on) VGS = −6 V, ID = −3.6 A VGS = −4.5 V, ID = − 2.0 A Forward Transconductancea Diode Forward Voltage a Symbol Test Conditions Typical 2.2 117 14 0.033 0.042 0.055 9.3 −0.76 Unit V A Ω gfs VSD VDS = −15 V, ID = −5.3 A IS = −2.4 A, VGS = 0 V S V Dynamic b Total Gate Chargeb Gate-Source Chargeb Gate-Drain Charge b Qg Qgs Qgd td(on) tr b 26.4 VDS = −10 V, VGS = −10 V, ID = −5.3 A 4.5 5.6 15 VDD = −10 V, RL = 10 Ω ID ≅ −1 A, VGEN = −10 V, RG = 6 Ω 21 35 45 IF = −2.4A, di/dt = 100 A/µs 66 ns nC Turn-On Delay Timeb Rise Timeb Turn-Off Delay Time Fall Timeb Source-Drain Reverse Recovery Time Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. td(off) tf trr www.vishay.com 2 Document Number: 70512 01-Jun-04 SPICE Device Model Si9430DY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 70512 01-Jun-04 www.vishay.com 3