SI9750CY-T1

Si9750 Vishay Siliconix In-Rush Current Limit MOSFET Driver FEATURES D 2.9- to 13-V Input Operating Range D Microprocessor RESET D Integrated High-Side Driver for N-Channel MOSFET D Programmable di/dt Current DESCRIPTION The Si9750 current limit MOSFET interface IC is designed to operate between a power source and a load using a low on-resistance power MOSFET with a sense terminal or in conjunction with a low ohmic sense resistor. The Si9750 current limiter prevents source and load transients during hot swap and power-on with programmable dv/dt and di/dt. Both turn-on and steady-state current limits can be individually programmed, providing protection against short circuits. Power on RESET and logic controls allow complete microprocessor interfacing. The RESET function of the Si9750 is industry-standard with full programmability. The Si9750 is available in a 16-pin SOIC package and is rated over the commercial temperature range (0 to 70_C). The Si9750 is available in both standard and lead (Pb)-free packages. FUNCTIONAL BLOCK DIAGRAM VDD VDD COIL Bias Ref Boost POR HI/LO ENABLE STATUS IBIAS CRETRY Overcurrent + − LIMSET LOAD POR CRST POR Reset Delay Bandgap Ref Reset − + Ref RESET VRST Load SENSE RLIMSET RSENSE (mW) VLOAD Control Gate Drive GATE BOOST CBOOST Low RDS N-Channel FET LBOOST RBIAS CGATE Retry Delay GND Document Number: 70028 S-40754—Rev. D, 19-Apr-04 www.vishay.com 1 Si9750 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Voltages Referenced to Ground VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Boost Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 V Inputs/Outputs (except Gate, Boost and VRST) . . . . . . . . . . . . . . . . . . . . . −0.3 to VDD + 0.3 V VRST Input Current (0 < VRST < 15 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Inputs/Outputs Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA RESET Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 mA STATUS Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 125_C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Power Dissipation (package)a 16-Pin SOICb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Thermal Impedance (QJA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140_C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.2 mW/_C above 25_C. * . Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating may cause permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time SPECIFICATIONS Test Conditions Unless Specified Parameter Supply Quiescent Current IQ ENABLE =Logic Low 4 8 mA Limits 0 to 70_C Symbol 2.9 V v VDD v 13.2 V HI/LO = GND RBIAS = 12.5 kW GND, 12 5 LBOOST = 100 mH, CBOOST = 100 nF Mina Typb Maxa Unit Logic Enable Turn-On Voltage Enable Turn-Off Voltage Enable Source Current Turn-On Time Turn-Off Time Turn-On Boost tOFF Initial Short Circuit tOFF Short Circuit Status Output Voltage Status Output Delay Time Status Threshold HI/LO Turn-On Voltage HI/LO Turn-Off Voltage VEN(on) VEN(off) IENSRC tON tOFF tON(BST) tOFF(ISC) tOFF(SC) VSTAT tSTDLY VSTATTHR VHILO(on) VHILO(off) VENABLE = 0V See Figure 3 See Figure 4 CGATE = 33 nF, See Figure 6 CGATE = 33 nF, See Figure 7 ISINK = 200 mA See Figure 8 0.85 x VDD 0.7 x VDD 0.3 x VDD 0.7 x VDD 40 120 5 5 600 10 2 0.4 25 0.95 x VDD V V ms ms 0.3 x VDD V mA Gate Drive Enhancement Voltage (VGATE − VSENSE) Source Current Sink Current VGS ISOURCE ISINK VCBOOST = 9 V 8.5 1.06 1.6 10.5 1.30 2.6 15 1.54 3.7 V mA Current Sense Circuit Current Sense Amplifier Common Mode Range Current Sense Amplifier Voltage Offset Current Sense Amplifier Bias Current RLIMSET Reference Current Current Sense Amplifier Hysteresis Current Sense Amplifier Series Offset VCMR VOS ISOS IRLIMSET VHYST VSOS HI/LO = VDD, VCMR > 0.5 V Normal Operation 18 0 −3 −0.2 19.5 12 20 21 VDD + 0.3 3 V mV mA mV Power On Reset RESET Output Voltage RESET Output Hysteresisc RESET Comparator Input Threshold www.vishay.com VOP(rst) VHYST VRST IOUT = 1 mA, VDD > 2 V See Note c 2 1.223 1.250 1.277 0.4 V mV V 2 Document Number: 70028 S-40754—Rev. D, 19-Apr-04 Si9750 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Specified Parameter Power On Reset RESET Comparator Offset Voltaged RESET Comparator Input Bias Current RESET Timer Delay RETRY VRBIAS IBIAS tRSTD tRETRY CRST = 15 nF, See Figure 8 CRETRY = 100 nF 110 70 0.5 −0.2 150 130 190 200 mV mA ms ms Limits 0 to 70_C Symbol 2.9 V v VDD v 13.2 V HI/LO = GND, RBIAS = 12.5 kW LBOOST = 100 mH, CBOOST = 100 nF Mina Typb Maxa Unit Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production test. c. In a practical situation, VHYST is multiplied by ratio of a resistor divider chain. For VDD = 13.2 V, VHYST = 20 mV. d. The RESET comparator input threshold specification (VRST) includes theRESET comparator offset voltage. PIN CONFIGURATION AND ORDERING INFORMATION SOIC-16 BOOST VDD GATE LOAD SENSE LIMSET HI/LO ENABLE 1 2 3 4 5 6 7 8 Top View 16 15 14 13 12 11 10 9 COIL GND CRST CRETRY RESET STATUS VRST RBIAS ORDERING INFORMATION Part Number Si9750CY Si9750CY-T1 Si9750CY-T1—E3 0 to 70_C SOIC-16 Temperature Range Package PIN DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function BOOST VDD GATE LOAD SENSE LIMSET HI/LO ENABLE RBIAS VRST STATUS RESET CRETRY CRST GND COIL Positive supply pin. Connection to external power MOSFET gate. Connection to positive supply side of LOAD. Description Output of on-chip Boost converter. A 100-nF capacitor should be connected between BOOST and GND Connects external sense resistor of a sensefet sense pin to SENSE input of overcurrent trip comparator. A standard MOSFET may also be used in conjunction with a low ohmic value shunt resistor. Connects overcurrent limit set resistor RLIMSET to the reference input of overcurrent trip comparator. CMOS logic input to control the overcurrent trip comparator sensitivity at power-on. HI/LO should be connected to GND for low Capacitive loads and to VDD for high capacitive loads. CMOS logic input to turn IC on or off. GATE voltage remains low when ENABLE is high. A resistor connected from this pin to GND programs the reference bias current for the overcurrent trip comparator resistor RLIMSET and the GATE(on) charge current. See Functional Description for equations. Input to voltage monitor comparator. Open drain NMOS output. This pin is driven low when the current limiter is enabled and the LOAD voltage is greater than 90% of VDD. Open drain NMOS output. This pin is driven low during power on reset or when VRST is lower than the internal 1.25-V reference. A capacitor connected from this pin to GND programs the retry timer. A capacitor connected from this pin to GND programs the reset timer. Negative supply pin. Connection to Boost converter inductor. www.vishay.com Document Number: 70028 S-40754—Rev. D, 19-Apr-04 3 Si9750 Vishay Siliconix FUNCTIONAL DESCRIPTION The Si9750 together with an n-channel MOSFET provides the following functions: D limits di/dt current for hot insertion applications D provides complete short circuit protection D high-side drive allows n-channel MOSFET to be used, for lower power dissipation D industry-standard microprocessor reset function D logic control input and outputs ILOAD x RSENSE >1.2 x IBIAS x RLIMSET + IBIAS(1 kW + RHI) (HI/LO = High) (3) ILOAD x RSENSE > 1.2 x IBIAS x RLIMSET (with pin HI/LO=Low) (2) If the HI/LO pin is tied low the current limit is 20% higher during turn-on than the steady state current limit point. If a higher current limit is needed at start-up, the HI/LO pin can be tied high. The equation becomes: Setting the Current Limit (SENSE, HI/LO pins, RLIMSET, RSENSE) The current limit point is determined by the voltage across RSENSE, the value of RLIMSET, and the bias current. The current limit circuit is shown in Figure 1 The steady state current is set by the equation: Notice that any current limit can be set at turn-on using an optional resistor, RHI. Relaxation Mode Current Limit (CRETRY pin) In an overload condition, the Si9750 will go into a relaxation mode current limit operation that not only protects the source and load, but also reduces the power dissipated in the MOSFET. When an overload is detected, the circuit quickly turns off, then goes into a retry mode whereby the current is ramped up slowly. If the fault still exists, the current will ramp down again. This sequence will repeat indefinitely at a period defined by 106 x CRETRY until the fault is removed. Typically, capacitors in the range of 1 nF to 1 mF can be used on CRETRY, but the period should be >50 ms. ILOAD x RSENSE > IBIAS x RLIMSET (1) Due to the highly capacitive nature of some loads, the Si9750 has an option to increase the current limit point to a much higher level at turn-on. In this case, turn-on is defined as VGATE < VDD + 7.8 V. This function is implemented with the HI/LO pin. Si9750 Overcurrent IBIAS HI/LO − + 1 kW, "20% SENSE GATE RHI (Optional) RSENSE VDD 330 W 33 nF 330 W LIMSET RLIMSET HI/LO ILOAD VLOAD FIGURE 1. www.vishay.com 4 Document Number: 70028 S-40754—Rev. D, 19-Apr-04 Si9750 Vishay Siliconix FUNCTIONAL DESCRIPTION (CONT’D) di/dt Limiting On Hot and Cold Insertion (GATE pin) The GATE pin provides a constant current source that is used to control the rate of rise of the gate of the MOSFET, and hence to control the di/dt of the load and source current. The equation that governs the gate current is: ISOURCE + 1.25 V x (for RBIAS = 12.5 kW) 12 + 1.2 mA R BIAS boost inductor should typically be 100 mH, 180 mA dc, and the boost capacitor should be 100 nF. Logic Control (STATUS, ENABLE, RESET, VRST and CRST pins) STATUS. The status monitor detects when the load voltage is 90% of input voltage, VLOAD > 0.9 x VDD. This pin is an open-drain NMOS output, capable of sinking 200 mA at VOL = 0.4 V. If this pin is used in conjunction with the ENABLE of another unit, power supply sequencing (or daisy-chaining) is easily implemented. ENABLE. This CMOS logic compatible input serves as the on/off control pin. This pin has 40-mA minimum pull-up to VDD. (4) Typically, a 33-nF capacitor should be connected from the GATE pin to ground. If a large ISOURCE is needed for high di/dt, a 330-W resistor in series with CGATE may be necessary to prevent oscillation. In the case that VDD > 6 V, a resistor of approximately 330 W is also recommended in series with the gate. (Figure 1) Reference Bias Current (RBIAS pin) This pin sets the internal current used by RLIMSET to determine all the current limit points. Typically RBIAS = 12.5 kW which sets a 20-mA bias current. The equation which relates RBIAS to IBIAS is: RESET (VRST, CRST, RESET pins). This is a standard implementation of the microprocessor reset function. A comparator looks at the voltage on VRST pin and compares it with 1.25 V. This function is programmable by using an external voltage divider. When VRST is higher than 1.25 V, the reset signal is delayed by the CRST pin, defined by Equation (6) and then goes high. (Figure 2) IBIAS + 1.25 V + 20 mA 5 x RBIAS Reset delay tRSTD [ 104 x CRST (5) (6) (for RBIAS = 12.5 kW) Power on Reset (POR) (VDD pin) This function monitors the voltage on the VDD pin and signals the system if all input voltage requirements have been met. At turn-on when VDD > 2.7 V " 200 mV, a POR signal is generated for a duration of 100 ms. After this point the system is released into operation. If VDD falls below 2.7 V " 200 mV, a second POR signal will be generated. If two POR signals are detected, this indicates that the source for VDD is not capable of supplying the load current. The IC then turns off the MOSFET and initiates its retry period, hence fully protecting the MOSFET from an over-power condition. Current HI/LO Pin RLIMSET CRETRY Short Circuit Applied to Output Turn-On VGATE > VDD + 7.8 V Current Limit Point ILOAD Boost Converter (COIL, BOOST pins) The boost converter generates the gate drive for the external n-channel MOSFET. This is limited to typically VDD + 11 V. The Document Number: 70028 S-40754—Rev. D, 19-Apr-04 FIGURE 2. Typical Operation Under Start-up Condition With An Overcurrent Fault Applied to the Output www.vishay.com 5 Si9750 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS OTHERWISE NOTED) 3.5 I SOURCE Gate-Source Current (mA) − 3.0 2.5 2.0 1.5 1.0 0.5 4 8 12 RBIAS (kW) 16 20 Gate-Source Drive Current vs. RBIAS 3.0 Gate-Sink vs. VDD I SINK − Gate-Sink Current (mA) 2.8 2.6 2.4 2.2 2.0 2.80 4.88 6.96 9.04 11.12 13.20 VDD (V) 50 I R(LIMSET) R LIMSETCurrent ( m A) − RLIMSET Current vs. RBIAS 400 t RSTD − RESET Timer Delay ( m S) RESET Timer Delay vs. CRESET 40 300 30 200 20 10 100 0 0 4 8 12 16 20 RBIAS (kW) 0 0 10 20 30 40 50 CRST (nF) 600 500 t RETRY RETRY Delay (mS) − 400 300 200 100 0 0 50 RETRY Delay vs. CRETRY 100 150 200 250 300 350 400 CRETRY (nF) www.vishay.com Document Number: 70028 S-40754—Rev. D, 19-Apr-04 6 Si9750 Vishay Siliconix SWITCHING TIME TEST CIRCUITS VDD 0 ENABLE 0.3 VDD tON 50 % 0 50 % ISINK 0.7 VDD ISOURCE tOFF FIGURE 3. Normal-Mode Operation ENABLE 1 0 1 VDD 0 VDD 0 1 VBOOST−VDD 1 ISOURCE 0 tON(bst) 50 % 0 1 1 tBOOST 90 % FIGURE 4. Timing Definition with ENABLE Already On FIGURE 5. Start of Boost Converter tRETRY ILOAD ILOAD VSENSE Threshold tOFF(isc) VG ISOURCE 1V 0 ISINK 50% VSENSE Threshold tOFF(sc) FIGURE 6. First Short Circuit 1 VG 0 1 0 1 STATUS 0 1 RESET(2) 0 FIGURE 7. Relaxation-Mode Current Limit VLOAD Status Threshold tSTDLY tSTDLY 0.3 x VDD tRSTD (2) With reset input divider correctly set, monitoring VLOAD FIGURE 8. STATUS and RESET Document Number: 70028 S-40754—Rev. D, 19-Apr-04 www.vishay.com 7 Legal Disclaimer Notice Vishay Notice Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale. Document Number: 91000 Revision: 08-Apr-05 www.vishay.com 1