Si9979
Vishay Siliconix
3-Phase Brushless DC Motor Controller
FEATURES
D Hall-Effect Commutation D 60_ or 120_ Sensor Spacing D Integral High-Side Drive for all N-Channel MOSFET Bridges D PWM Input D D D D D Quadrature Selection Tachometer Output Reversible Braking Output Enable Control D D D D Cross Conduction Protection Current Limiting Undervoltage Lockout Internal Pull-Up Resistors
DESCRIPTION
The Si9979 is a monolithic brushless dc motor controller with integral high-side drive circuitry. The Si9979 is configured to allow either 60_or 120_ commutation sensor spacing. The internal low-voltage regulator allows operation over a wide input voltage range, 20- to 40-V dc. The Si9979 provides commutation from Hall-effect sensors. The integral high-side drive, which utilizes combination bootstrap/charge pump supplies, allows implementation of an all n-channel MOSFET 3-phase bridge. PWM, direction, quadrature select, and braking inputs are included for control along with a tachometer output. Protection features include cross conduction protection, current limiting, and undervoltage lockout. The FAULT output indicates when undervoltage, over current, disable, or invalid sensor shutdown has occurred. The Si9979 is available in both standard and lead (Pb)-free 48-pin SQFP packages and is specified to operate over the commercial temperature range of 0 to 70_C (C suffix), and the industrial temperature range of −40 to 85_C (D suffix).
FUNCTIONAL BLOCK DIAGRAM
42 Low-Voltage Regulator VDD 43 VDD VREF Low-Side U.V. Lockout INA INB INC 60/120 EN F/R QS PWM BRK TACH FAULT 1 2 3 4 5 6 7 8 9 10 11 VDD VDD VDD VDD VREF VREF VREF VREF VREF 29 25
13-16, 21-24 37-41, 44-48
V+
Bootstrap Reg. CAPA CAPB CAPC High-Side U.V. Lockout Charge Pump
36 34 35
CAPA GTA SA CAPB GTB SB CAPC GTC SC GBA GBB GBC GND IS− IS+
Bootstrap Reg. Charge Pump
32 30 31
Bootstrap Reg. Charge Pump Input Logic VDD
28 26 27 33
RT RT/CT
18 17 One Shot
− +
20 19
Document Number: 70012 S-41209—Rev. E, 21-Jun-04
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Si9979
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltage on Pin 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V Voltage on Pins 1−4, 10, 11 . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 V Voltage on Pins 5−9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 5.5 V Voltage on Pins 26, 28, 30, 32, 34, 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Voltage on Pins 27, 31, 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2 to 50 V Operating Temperature C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70_C D Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 to 85_C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 150_C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Power Dissipation (PD) C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.70 W D Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55 W
RECOMMENDED OPERATING RANGE
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 to 40 VDC RT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 kW Min
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Otherwise Parameter Power
Supply Voltage Range Logic Voltage Supply Current Logic Current Internal Referenced V+ VDD I+ IDD VREF −20 4.2 −20 mA v IDD v 0 mA 20 14.5 16 4.5 40 17.5 V mA V
Limits Mina Typb Maxa Unit
Symbol
V+ = 20 to 40 V, IDD = 0 mA
Commutation Inputs (INA, INB, INC, 60/120)
High-State Low-State High-State Input Current Low-State Input Current VIH VIL IIH IIL VIH = VDD VIL = 0 V −50 4.0 1.0 10 V mA
Logic Inputs (F/R, EN, QS, PWM, BRK)
High-State Low-State High-State Input Current Low-State Input Current VIH VIL IIH IIL VIH = 5.5 V VIL = 0 V −125 2.0 0.8 10 V mA
Outputs
Low-Side Gate Drive, High State Low-Side Gate Drive, Low State High-Side High Side Gate Drive High State Drive, High-Side Gate Drive, Low State Capacitor Voltaged Low-Side Switching, Rise Time Low-Side Switching, Fall Time High-Side Switching, Rise Time High-Side Switching, Fall Time Break-Before-Make Break Before Make Time TACH Output/FAULT Output TACH Output Pulsewidth www.vishay.com VGBH VGBL VGTH VGTL VCAP trL tfL trH tfH tBLH tBHL VOL tT IOL = 1.0 mA 300 Risetime = 1 to 10 V Falltime = 10 to 1 V CL = 600 pF V+ = 40 V 55 70 25 100 40 100 300 0.15 600 0.4 V ns Document Number: 70012 S-41209—Rev. E, 21-Jun-04 ns TA = 0 to 70_C TA = −40 to 85_C C Suffix D Suffix 16 16 14 16 17.5 0.1 18 20 0.1 V
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Si9979
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Protection
Low-Side Undervoltage Lockout Low-Side Hysteresis High-Side Undervoltage Lockout UVLL VH UVLH SA, B, C = 0 V 12.2 0.8 VDD − 3.3 V
Limits Mina Typb Maxa Unit
Symbol
V+ = 20 to 40 V, IDD = 0 mA
Current Limit
Comparator Input Bias Current Comparator Threshold Voltage Common Mode Voltage One Shot Pulse Width IIB VTH VCM tp RT = 10 k, CT = 0.001 mF RT = 10 k, CT = 0.01 mF TA = 0 to 70_C TA = −40 to 85_C C Suffix D Suffix −5 90 85 0 8 80 10 100 100 100 110 125 1 12 120 mA mV V ms
Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. The reference voltage is not available for external use. d. VCAP = (V+) + (VDD).
COMMUTATION TRUTH TABLE
Inputs Sensors (60_Spacing) INA
0 1 1 1 0 0 0 1 1 1 0 0 X X L L L 1 1 0 0 Notes:
Outputs Top Drive EN
1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1
Conditions
Sensors (120_Spacing) INA
1 1 1 0 0 0 1 1 1 0 0 0 X X L L L 1 1 0 0
Bottom Drive GB
A
0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 1 0 1
INB
0 0 1 1 1 0 0 0 1 1 1 0 X X L L L 0 0 1 1
INC
0 0 0 1 1 1 0 0 0 1 1 1 X X L L L 1 1 0 0
INB
0 0 1 1 1 0 0 0 1 1 1 0 X X L L L 1 1 0 0
INC
1 0 0 0 1 1 1 0 0 0 1 1 X X L L L 1 1 0 0
F/R
1 1 1 1 1 1 0 0 0 0 0 0 X X X X X X X X X
BR K
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1
IS+
0 0 0 0 0 0 0 0 0 0 0 0 X X 0 1 1 X X X X
GT- GT- GTA
1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
GB
B
1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1
GB
C
0 1 1 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 0 1
B
0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0
C
0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
FAULT
1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 Disable Power Down Brake Over I in BRK Over I
L. Any valid sensor combination X. Don’t care www.vishay.com
Document Number: 70012 S-41209—Rev. E, 21-Jun-04
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Si9979
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION SQFP-48
GND GND GND GND GND GND GND GND GND GND V DD V+
48 47 46 45 44 43 42 41 40 39 38 37
ORDERING INFORMATION
36 35 34 33 32 31 30 29 28 27 26 25 CAPA SA GTA GBA CAPB SB GTB GBB CAPC SC GTC GBC
INA INB INC 60/120 EN F/R QS PWM BRK TACH FAULT GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GND GND IS + IS − GND GND GND GND GND R T/C T GND RT
Standard Part Number
Si9979CS Si9979DS
Lead (Pb)-Free Part Number
Si9979CS—E3 Si9979DS—E3
Temperature Range Package
0 to 70_C −40 to 85_C SQFP-48 -48
NOTE: Si9979CS and Si9979DS are supplied in trays.
Top View
PIN DESCRIPTION
Pins 1−3: INA, INB, INC INA, INB, and INC are the commutation sensor inputs, and are intended to be driven by open collector Hall effect switches. These inputs have internal pull up resistors tied to VDD, which eliminates the need for external pull up resistors. Pin 4: 60/120 The 60/120 input allows the use of the Si9979 with either a 60_ or 120_ commutation sensor spacing. An internal pull up resistor, which is tied to VDD, sets the default condition to 60_ spacing. 120_ spacing is selected by pulling this input to ground. Pin 5: EN (Enable) A logic “1” on this input allows commutation of the motor. This is the default condition as this pin is pulled up internally. When this pin is pulled to ground, all gate drive outputs are turned off. Pin 6: F/R (Forward/Reverse) A logic “1” on this input selects commutation for motor rotation in the “forward” direction. This is the default condition as this
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pin is pulled up internally. When this pin is pulled to ground, the commutation sensor logic levels are inverted internally, causing reverse rotation. Pin 7: QS (Quadrature Select) This input determines whether the bottom MOSFETs or both bottom and top MOSFETs switch in response to the PWM signal. A logic “1” on this input enables only the bottom MOSFETs. This is the default condition as this pin is pulled up internally. When this pin is pulled to ground, both the bottom and top MOSFETs are enabled. Pin 8: PWM An open collector (drain) or TTL compatible signal is applied to this input to control the motor speed. The QS input determines which MOSFETs are switched in response to the PWM signal. If no PWM signal is being used, this input is left open. It is pulled up internally, which allows the MOSFETs to follow the commutation sequence.
Document Number: 70012 S-41209—Rev. E, 21-Jun-04
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Si9979
Vishay Siliconix
PIN DESCRIPTION (CONT’D)
Pin 9: BRK With this input at logic “1”, the top MOSFETs are turned off and the bottom MOSFETs are turned on, shorting the motor windings together. This provides a braking torque which is dependent on the motor speed. This is the default condition as this pin is pulled up internally. When this pin is pulled to ground, the MOSFETs are allowed to follow the commutation sequence. Pin 10: TACH This output provides a minimum 300-nanosecond output pulse for every commutation sensor transition, yielding a 6 pulse per electrical revolution tachometer signal. This output is open drain. Pin 11: FAULT The FAULT output switches low to indicate that at least one of the following conditions exists, controller disable (EN), undervoltage lockout, invalid commutation sensor code shutdown, or overcurrent shutdown. This output is open drain. Pin 17: RT/CT The junction of the current limit one shot timing resistor and capacitor is connected to this pin. This one-shot is triggered by the current limit comparator when an overcurrent condition exists. This action turns off all the gate drives for the period defined by RT and CT , thus stopping the flow of current. Pin 18: RT One side of the current limit one shot timing resistor is connected to this pin. Pin 19: IS+ This is the sensing input of the current limit comparator and should be connected to the positive side of the current sense resistor. When the voltage across the current sense resistor exceeds 100 mV, the comparator switches and triggers the current limit one-shot. The one-shot turns off all the gate drives for the period defined by RT and CT, thus stopping the flow of current. If the overcurrent condition remains after the shutdown period, the gate drives will be held off until the overcurrent condition no longer exists. Pin 20: IS− This pin is the ground reference for the current limit comparator. It should be connected directly to the ground side of the current sense resistor to enhance noise immunity. Pins 12−16: 21−24, 37−41, 44−48, GND These pins are the return path for both the logic and gate drive circuits. Also, they serve to conduct heat out of the package, into the circuit board. Pin 25: GBC This is the gate drive output for the bottom MOSFET in Phase C. Pin 26: GTC This is the gate drive output for the top MOSFET in Phase C. Pin 27: SC This pin is negative supply of the high-side drive circuitry. As such, it is the connection for the negative side of the bootstrap capacitor, the top MOSFET Source, the bottom MOSFET Drain, and the Phase C output. Pin 28: CAPC This pin is the positive supply of the high-side circuitry. The bootstrap capacitor for Phase C is connected between this pin and SC. Pin 29: GBB This is the gate drive output for the bottom MOSFET in Phase B. Pin 30: GTB This is the gate drive output for the top MOSFET in Phase B. Pin 31: SB This pin is negative supply of the high-side drive circuitry. As such, it is the connection for the negative side of the bootstrap capacitor, the top MOSFET Source, the bottom MOSFET Drain, and the Phase B output. Pin 32: CAPB This pin is the positive supply of the high-side circuitry. The bootstrap capacitor for Phase B is connected between this pin and SB. Pin 33: GBA This is the gate drive output for the bottom MOSFET in Phase A.
Document Number: 70012 S-41209—Rev. E, 21-Jun-04
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Si9979
Vishay Siliconix
PIN DESCRIPTION (CONT’D)
Pin 34: GTA This is the gate drive output for the top MOSFET in Phase A. Pin 35: SA This pin is negative supply of the high-side drive circuitry. As such, it is the connection for the negative side of the bootstrap capacitor, the top MOSFET Source, the bottom MOSFET Drain, and the Phase A output. Pin 36: CAPA This pin is the positive supply of the high-side circuitry. The bootstrap capacitor for Phase A is connected between this pin and SA. Pin 42: V+ The supply voltage for the Si9979 is connected between this pin and ground. The internal logic and high-side supply voltages are derived from V+. Pin 43: VDD VDD is the internal logic and gate drive voltage. It is necessary to connect a capacitor between this pin and ground to insure that the current surges seen at the turn on of the bottom MOSFETs does not trip the undervoltage lockout circuitry.
APPLICATION CIRCUITS
LITTLE FOOT V+
Si9979
1 mF 42 43 To Commutation Sensors 1 2 3 5 6 9 4 TACH PWM IN FAULT 10 7 8 11 18 17 RT CT 12−16, 21−24 37−41, 44−48 GND V+ VDD INA INB INC EN F/R BRK 60/120 TACH QS PWM FAULT RT RT/CT GND GTA SA CAPA GTB SB CAPB GTC SC CAPC GBA GBB GBC IS+ IS− GND 34 35 36 30 31 32 26 27 28 35 29 25 19 20 C RS R CBC CBB CBA
Q1
Q2
Q3
A B C Q4 Q5 Q6 To Motor Windings
FIGURE 1. Three-Phase Brushless DC Motor Controller
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Document Number: 70012 S-41209—Rev. E, 21-Jun-04
Si9979
Vishay Siliconix
APPLICATION CIRCUITS
V+ LITTLE FOOT
Si9979
1 mF 42 V+ 43 V 1 2 3 5 6 9 4 GTA SA CAPA GTB SB CAPB EN F/R BRK GTC SC CAPC GBA GBB GBC IS+ IS− GND 34 35 36 30 31 32 26 27 28 35 29 25 19 20 C RS R CBB CBA
Q1
Q2
DD
To Commutation Sensor
INA INB INC
A B
To Motor Windings
Notes: 1) If driving single phase BLDC, tie INA, INB, and INC together and drive with single hall. 2) If it is being used as an Hbridge controller, tie INA, INB, and INC to GND. Use F/R input to change active diagonal pair of MOSFETs. 3) There is no TACH output when connected in this configuration.
TACH PWM IN FAULT RT CT
60/120 10 TACH 7 QS 8 PWM 11 FAULT 18 RT 17 RT/CT GND
Q4
Q5
12−16, 21−24 37−41, 44−48 GND
FIGURE 2. Single H-Bridge Controller
LITTLE FOOT V+ MC14022 0 1 2 CLK CP0 3 4 5 6 7 CP1 MR TACH PWM IN FAULT RT CT 1 mF 42 43 1 2 3 5 6 9 4 10 7 8 11 18 17 V+ VDD INA INB INC EN F/R BRK 60/120 TACH Q S PWM FAULT RT RT/CT GND
Si9979
GTA SA CAPA GTB SB CAPB GTC
C
Q1 34 35 36 30 31 32 26 CBB CBA
Q2
Q3
A B To Motor C Windings Q4 Q5 Q6
SC 27 28 CAP GBA GBB
S
35
CBC
29 R
GBC 25 I + 19
IS− 20 GND
C RS
12−16, 21−24 37−41, 44−48 GND
FIGURE 3. Three-Phase AC Motor Controller
Document Number: 70012 S-41209—Rev. E, 21-Jun-04 www.vishay.com
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Si9979
Vishay Siliconix
APPLICATION CIRCUITS
V+
VDD’
V+
C1 1 mF VDD’ = VDD − VBE
VDD
Si9979
FIGURE 4. External VDD Regulator
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Document Number: 70012 S-41209—Rev. E, 21-Jun-04
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Vishay
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.
Document Number: 91000 Revision: 08-Apr-05
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