SIC413

SiC413 Vishay Siliconix microBUCKTM SiC413 4-A, 26-V Integrated Synchronous Buck Regulator DESCRIPTION The SiC413 is an integrated, dc-to-dc power conversion solution with built-in PWM-optimized high- and low-side N-channel MOSFETs and advanced PWM controller. The SiC413 provides a quick and easy to use POL voltage regulation solution for a wide range of applications. Vishay Siliconix’s Proprietary packaging technology is used to optimize the power stage and minimize power losses associated with parasitic impedances and switching delays. The co-packaged Gen III TrenchFET power MOSFET devices deliver higher efficiency than lateral DMOS monolithic solutions. FEATURES • Integrated PWM controller and Gen III trench MOSFETs • Quick and easy single chip converter • Integrated current sense • Cycle by cycle over-current protection • Built-In bootstrap diode • Output over-voltage protection • Under voltage lockout • Thermal shutdown • Soft start • Break-before-make operation • Halogen-free according to IEC 61249-2-21 definition • Compliant to RoHS directive 2002/95/EC PRODUCT SUMMARY Input Voltage Range Output Voltage Range Operating Frequency Continuous Output Current Peak Efficiency Highside/Lowside RDS_ON Package 4.75 V to 26 V 0.6 V to 13.2 V 500 kHz 4A 93 % 35 mΩ/19 mΩ SO-8 APPLICATIONS • • • • • • LCD TV, set top box and DVD player Desktop PC and server Add-in graphics board Memory, FPGA or µP device power supplies Point of load dc-to-dc conversion Telecom and networking equipment TYPICAL APPLICATION VIN VREG 7 VIN 6 Enable EN 2 3 BOOT COMP 1 Controller 4 VSW VO FB 8 SiC413 5 GND Figure 1 - Typical Application Circuit Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 www.vishay.com 1 SiC413 Vishay Siliconix PIN CONFIGURATION COMP EN BOOT VSW 1 2 3 4 8 7 6 5 FB VREG VIN GND Figure 2. SO-8 Pin Out - Top View PIN DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 Symbol COMP EN BOOT VSW GND VIN VREG FB Description Error amplifier output. Connects to the compensation network. Chip enable pin. Active HIGH. Connects to a power source through a 10K to100K resistor to enable. Connect to 0.1 µF capacitor from VSW to BOOT to power the high side gate driver. Inductor Connection. Connect an output filter inductor to this pin. VSW is high impedance when the IC is in shutdown mode. GROUND pin. Supply voltage. Internal regulator output. An external 4.7 µF decoupling capacitor is required at this pin. Output voltage feedback input. ORDERING INFORMATION Part Number SiC413CB-T1-E3 SiC413DB Package SO-8 (6.2 x 5 x 1.75 mm) Reference board FUNCTIONAL BLOCK DIAGRAM VREG VI N UVLO 5.5 VREG EN Shutdown control OTP OVP PW M GM Over current Control logic and active dead time VS W VREG BOOT FOSC GND FB COMP Figure 3. Functional Block Diagram www.vishay.com 2 Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 SiC413 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noteda Parameter Input Breakdown Voltage Common Switch Node Breakdown Voltage Logic Inputs Bootstrap Voltage Maximum Power Dissipation Operating Temperature Storage Junction Temperature Soldering Peak Temperature Notes: a. TA = 25 °C and all voltages referenced to GND unless otherwise noted. Symbol VIN VSW DC VSW Peakc VCOMP, VFB, VEN VBOOT PD Tj Tstg - 25 - 40 Min. - 0.3 -1 -1 - 0.3 - 0.3 Max. 28 28 30 6 33 1.5 125 150 260 °C W V Unit Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONSb Parameter Input Voltage Logic Inputs Common Switch Node Symbol VIN VCOMP, VFB, VEN VSW DC VSW peakc Min. 4.75 4.5 - 0.3 - 0.3 Typ. 12 5 12 24 Max. 26 5.5 26 28 V Unit Notes: b. Recommended operating conditions are specified over the entire temperature range, and all voltages referenced to GND unless otherwise noted. c. Peak value is specified for pulses ≤ 100 ns. THERMAL RESISTANCE RATINGS Parameter Junction-to-Case Resistance In Operation, Max. Junction Junction-to-Ambient Resistance PCB = Copper 25 mm x 25 mm Case Top to Board Edge PCB = EVBSiC413 Rev. 3.0; No Forced Airflow Symbol RthJC RthJA RthCA Contact Vishay for thermal design assistance °C/W Typ. Unit Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 www.vishay.com 3 SiC413 Vishay Siliconix SPECIFICATIONS Conditions Unless Specified Otherwise VIN = 12 V, VEN = 5 V, VOUT = 3.3 V, TA = 25 °C Air flow = 0 5 0 ≤ IO ≤ 4 A IOUT = 0 VFB RDS(ON)HS RDS(ON)LS FOSC DC TA = 25 °C TA = - 25 °C to 85 °C VBOOT - VSW = 5.5 V VREG = 5.5 V 435 62 0.591 0.582 0.6 0.6 35 19 500 70 110 2.5 1.5 IFB 2 30 VEN H VEN L VEN rising VEN falling VFB rising and when VFB/VREF is greater than VFB falling and when VFB/VREF is less than VIN rising VIN falling 3.55 1.8 0.6 565 Parameter Converter Operation Output Currenta Internal Regulated Voltage Load Regulationa Line Regulationa Feedback Voltage MOSFET On Resistance Internal Oscillator Frequency Max. PWM Duty Cycle Error Amplifier Open Loop Voltage Gain Unity Gain Bandwidth Transconductance Input Bias Current Max. Sink/Source Current Enable Enable Logic Level High Enable Logic Level Low Protection Overvoltage Trip Point Overvoltage Trip Hysteresis VIN Undervoltage Lockout VIN Undervoltage Lockout Hysteresis Thermal Shutdown Thermal Shutdown Hysteresis Peak Current Limit Soft Start Soft Start Period Supply Current Input Current Shutdown Current Dynamicb Rise Time Fall Time Symbol IOUT VREG Min. Typ.a 4 5.7 Max. Unit A 6.1 0.6 0.1 0.609 0.618 V % %/V V mΩ kHz % dB MHz mS nA µA V OVP OVPHYS VIN UVLO-h VIN UVLO HS TJ SD TJ SD HS ILIM TSS IQ ISD Tr_SW Tf_SW 115 120 110 3.8 200 165 20 7 5 125 % 4.05 V mV °C A ms mA µA VEN = high and no load VEN = 0 V 10 % to 90 % of SW 90 % to 10 % of SW 10 8 16 15 ns Notes: a. Guaranteed by design and not 100 % production tested. b. Pulse test; pulse width ≤ 300 ms, duty cycle ≤ 2 %. www.vishay.com 4 Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 SiC413 Vishay Siliconix ELECTRICAL CHARACTERISTICS 16 14 12 10 ISD (µA) 77 VIN = 12 V 76 Maximum Duty Cycle (%) VIN = 12 V 75 74 73 72 71 70 - 25 - 10 8 6 4 2 0 - 25 - 10 5 20 35 50 65 80 95 110 125 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Shut Down Current vs. Temperature 6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.4 - 25 - 10 VIN = 4.75 V VIN = 12V/24 V Switching Frequency (kHz) Maximum Duty Cycle vs. Temperature 530 VIN = 12 V 520 510 VREG (V) 500 490 480 5 20 35 50 65 80 95 110 125 470 - 25 - 10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Internal Regulator Voltage vs. Temperature Frequency vs. Temperature 1.010 VIN = 12 V 1.005 VFB (Normalized) ILIM (Normalized) 1.3 1.2 1.1 1 0.9 0.8 0.7 1.000 0.995 0.990 - 25 - 10 5 20 35 50 65 80 95 110 125 0.6 - 25 - 10 5 20 Temperature (°C) 35 50 65 80 Temperature (°C) 95 110 125 Feedback Voltage vs. Temperature (Normalized) Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 Peak Current Limit vs. Temperature (Normalized) www.vishay.com 5 SiC413 Vishay Siliconix ELECTRICAL CHARACTERISTICS 95 VO = 5.0 V 90 VO = 3.3 V 85 Efficiency (%) Efficiency (%) 95 90 85 80 75 70 65 60 0.0 80 75 70 65 60 0.0 VO = 1.8 V 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Load Current (A) Load Current (A) Efficiency at VIN = 12 V Efficiency at VIN = 5 V and VO = 1.8 V 3.365 Set VO + 0.3 % 3.360 Output Voltage (V) Output Voltage (V) 5.070 Set VO + 0.3 % 5.065 5.060 3.355 5.055 5.050 Actual VO 5.045 5.040 3.350 Actual VO 3.345 3.340 Set VO - 0.3 % 3.335 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 5.035 Set VO - 0.3 % 5.030 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Load Current (A) Load Current (A) Load Regulation at VIN = 12 V, VO = 3.3 V Load Regulation at VIN = 12 V, VO = 5.0 V www.vishay.com 6 Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 SiC413 Vishay Siliconix ELECTRICAL CHARACTERISTICS VO: 1 V/div t: 200 µs/div EN: 2 V/div COMP: 500 mV/div COMP: 200 mV/div VO: 1 V /div IL: 1 A/div IL: 1 A/div t: 1 ms/div EN: 2 V/div System starts up with EN pin becoming HIGH while VIN is ready. VIN = 12 V, VO = 3.3 V and IO is preset to about 3 A. Resistive load. VO: 1 V/div VO: 20 mV/div IL: 1 A/div System shuts down with EN pin becoming LOW. VIN = 12 V, VO = 3.3 V and IO comes down from about 3 A. VO: 100 mV/div VSW: 5 V/div t: 500 ns/div IL: 2 A/div t: 50 µs/div VO ripple and VSW switching waveform. VIN = 12 V, VO = 3.3 V and L = 10 µH (IHLP2525EZ type). CO consists of MLCC of 4.7 µF and tantalum of 100 µF/20 V x 2 Transient response. VIN = 12 V, VO = 3.3 V and L = 10 µH (IHLP2525EZ type). CO consists of MLCC of 4.7 µF and tantalum of 100 µF/20 V x 2. Output current steps up and down between 0.4 A and 4 A with less than 1 µs rising and falling time. t: 20 ms/div VSW: 10 V/div VO: 1 V/div COMP: 500 mV/div IL: 5 A/div Overcurrent protection at IO = 8 ~ 10 A. VIN = 12 V, VO = 3.3 V and L = 10 µH (IHLP2525EZ type). CO consists of MLCC of 4.7 µF and tantalum of 100 µF/20 V x 2 Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 www.vishay.com 7 SiC413 Vishay Siliconix DETAILED OPERATIONAL DESCRIPTION Input Voltage (VIN) The input voltage pin on the SiC413CB provides the bias supply for the PWM controller IC and the MOSFET driver circuitry. This pin also is internally connected to the drain of the high side MOSFET. Feedback (FB) and Output Voltage (VO) The FB pin is the negative input of the internal error amplifier. This pin connects to the center of the output voltage divider, through a 10K ~ 100K resistor (for noise isolation). When in regulation the FB voltage is 0.6 V. The output voltage VO is set based on the following formula. VO = VREF (1 + R1/R2) where R1 and R2 are shown in Figure 4. Enable (EN) CMOS logic signal. In the low state, the EN pin shuts down the driver IC and disables both high-side and low-side MOSFETs. An internal pull up resistor will enable the device if this pin is left open. An external pull up of 10 kΩ to 100 kΩ is recommended for better noise immunity. Soft-Start (SS) This device allows typical 5 ms soft start time to prevent inrush current during system startup. The soft start cycle starts when EN is asserted (low to high). Under Voltage Lockout (UVLO) The SiC413CB incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (VIN) is below x.xx V typical. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage. Once the UVLO rising threshold is reached, the device start-up begins. The device keeps operating unless VIN drops below UVLO falling threshold. The nominal 200 mV UVLO hysteresis and 2.5 µs rising and falling edge de-glitch circuit reduce the likelihood of the device shutdown due to noise on VIN. Switch Node (VSW) The switch node is the interconnection between the and high- and low-side MOSFETs. Connect the output inductor to this pin. Also, this node is the return path for the bootstrap capacitor. Bootstrap Circuit (BOOT) A diode and a capacitor form a bootstrap circuit that powers high-side MOSFET driver. SiC413 has this diode built in and therefore only an external capacitor is required to form this circuit. This capacitor is connected between BOOT pin and VSW pin. Over Temperature Protection (OTP) OTP provides thermal protection to the controller and power MOSFETs when an overload condition occurs. When the junction temperature of the SiC413CB exceeds nominal 165 °C (OTP trip point), the power MOSFETs will be turned off www.vishay.com 8 and the controller will be disabled. The device will automatically restart when the junction temperature drops to nominal 20 °C below its trip point. After the thermal protection is deasserted, a regular soft start cycle will be initiated. Over Voltage Protection (OVP) When the feedback voltage on FB pin exceeds 120 % of VREF, the over voltage condition is asserted. When over voltage occurs, the controller will turn on low-side MOSFET and turn off high-side MOSFET to discharge the excessive output voltage. The over voltage condition is removed when the voltage on FB pin drops to below 110 % of VREF. Over Current Protection (OCP) The SiC413CB integrates all components required for over current protection. This achieved by sensing the current flowing through the Low-side MOSFET. When low-side MOSFET is turned on, the current flowing through it will generate a voltage drop determined by its RDS(ON). After a blanking time delay (to ignore switching noise), this voltage is compared to a reference that corresponds to a preset overcurrent threshold (typical 7 A peak). If the voltage drop on low-side MOSFET is higher than the preset reference, an overcurrent protection event occurs. This triggers the PWM controller to keep the low side MOSFET on until the inductor current discharges to a level below the over current protection threshold. This lowers the duty cycle and causes the output voltage to droop. The SiC413CB overcurrent fault mode is designed to protect against false triggering.An overcurrent event is defined as starting when the overcurrent threshold is tripped and ending when the inductor current in the low side MOSFET is below the overcurrent trheshold. Seven sequential overcurrent events are required to place the SiC413CB into the over current fault mode. Overcurrent events are counted by an up down counter. If the overcurrent state is detected, the counter counts 1 up otherwise it counts 1 down. If the count reaches 7, the device will enter fault mode and both high- and low-side MOSFETs will turn off for 15 PWM clock cycles. After this period, the device will initiate a regular soft start. This sequence repeats until the overcurrent is completely removed. This is often referred to as hiccup mode. If the counter does not reach the count of 7. The SiC413CB does not enter into the overcurrent fault mode and operation is not disrupted. Shoot-Through Protection (Break-Before-Make: BBM) The SiC413CB has an internal break-before-make function to ensure that both high- and low-side MOSFETs are not turned on at the same time. An internal circuit detects the falling edge of both high- and low-side gate drive. The low-side MOSFET is turned on only after the high-side gate voltage is less than VBBM, similarly the high-side MOSFET gate is turned on after a fixed deadtime after the low side gate is less than VBBM. This BreakBefore-Make time parameter is not user adjustable. Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 SiC413 Vishay Siliconix APPLICATION NOTES Inductor Selection The inductor is one of the energy storage components in a converter. Choosing an inductor means specifying its size, structure, material, inductance, saturation level, DC-resistance (DCR), and core loss. Fortunately, there are many inductor vendors that offer wide selections with ample specifications and test data, such as Vishay Dale. The following are some key parameters that users should focus on. In PWM mode, inductance has a direct impact on the ripple current. Assuming 100 % efficiency, the steady state peak-to-peak inductor (L) ripple current (IPP) can be calculated as It is common practice to rate for the worst-case RMS ripple that occurs when the duty cycle is at 50 %: I RMS = IO.MAX. 2 Output Capacitor Selection The output capacitor affects output voltage ripple due to 2 reasons: the capacitance and the effective series resistance (ESR). The selection of the output capacitor is primarily determined by the capacitor ESR required minimizing voltage ripple and current ripple. The relationship between output ripple ΔVO, capacitance CO and its ESR is: I PP = VO . (VIN - VO ) VIN . L . f ΔVO = I PP . ESR + ( 1 8 . f . CO ) where f = switching frequency. Higher inductance means lower ripple current, lower rms current, lower voltage ripple on both input and output, and higher efficiency, unless the resistive loss of the inductor dominates the overall conduction loss. However, higher inductance also means a bigger inductor size and a slower response to transients. For fixed line and load conditions, higher inductance results in a lower peak current for each pulse, a lower load capability, and a higher switching frequency. The saturation level is another important parameter in choosing inductors. Note that the saturation levels specified in data sheets are maximum currents. For a dc-to-dc converter operating in PWM mode, it is the maximum peak inductor (IPK) current that is relevant, and can be calculated using these equations: Multiple capacitors placed in parallel may be needed to meet the ESR requirements. However if the ESR is too low it may cause stability problems. Control Loop Design The SiC413CB is an integrated voltage mode buck converter. The loop stability depends on input and output voltage, output LC filter, the equivalent lumped capacitance, resistance and inductance attached to the output voltage rail beyond the LC filter. The output LC filter creates a two pole roll-off of the loop gain that makes the closed loop system inherently unstable. Therefore, a compensation network of poles and zeros must be implemented to achieve unconditional stability. Figure 4 shows a simplified diagram of the SiC413CB buck converter control loop and the external elements that affect loop gain, phase shift and stability. In this diagram L1, C4 and C5 and R6 form a first order model of low pass filter. Resistor R6 represents the effective series resistance (ESR) of C5, which is often the case of a polymer (tantalum) capacitor. Ceramic (MLCC) capacitors are also used as denoted by C4, which has near zero ESR. To balance the performance and cost, the recommended output capacitor configuration is a combination of low cost, high capacitance polymer capacitors (C5) with ESR (R6) to add a zero to help boost phase margin and MLCC capacitors (C4) that have low ESR for achieving low voltage ripple. In practice, the lumped equivalent capacitance at the output of the filter may be a combination of many different kinds of capacitors. The characteristics of these capacitors must be considered when deriving the open loop transfer function and designing the loop compensation. It is important to have a good approximation of the lumped impedance (capacitors, resistors, ferrite beads, π filters, etc.) tied to the rail before calculating compensation network component values. Resistor R1 and R2 form the feedback voltage divider that samples the DC output and applies a feedback signal to the FB pin. Components C1, C2, C3, R4, R5 and the transconductance error amplifier form the loop compensation network. With voltage mode control loop the www.vishay.com 9 I PK = IO + I PP 2 where IO = output current. This peak current varies with inductance tolerance and other errors, and the rated saturation level varies over temperature. So a sufficient design margin is required when choosing current ratings. A high-frequency core material, such as ferrite, should be chosen, the core loss could lead to serious efficiency penalties. The DCR should be kept as low as possible to reduce conduction losses. Input Capacitor Selection To minimize input voltage ripple caused by the step-down conversion, and interference of large voltage spikes from other circuits, a low-ESR input capacitor is required to filter the input voltage. The input capacitor should be rated for the maximum RMS input current of: IRMS = I O. MAX VO VIN () 1VO VIN Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 SiC413 Vishay Siliconix output voltage is fed back at the FB pin. This feedback signal is summed with a precision voltage reference through a high bandwidth transconductance amplifier, often referred to as the error amplifier. This summation creates an error signal that is proportional to the difference between the actual output voltage and the desired output voltage, which is achieved when the voltage at the center tap of the feedback resistor divider is equal to the voltage reference. The error signal is present at the COMP pin, which is the output of the error amplifier. The error amplifier in the SiC413CB has a high loop gain and a 2.5 MHz Gain Bandwidth Product. It is designed this way to provide fast transient response in applications such as DRAM memory arrays in Graphics Cards. This lets the control loop quickly respond to any deviation of the output voltage. It also makes the SiC413CB more sensitive to noise on the FB pin. It is recommended to add resistor R3 at 20 kΩ to help isolate the error amplifier from noise on the FB pin and give the designer the full benefit of the fast response time the SiC413CB can deliver. Under normal operation the output of the error signal varies between 1.0 V and 2.0 V. This corresponds to the peak to peak amplitude of the saw-tooth wave form generated by the oscillator at the input to the PWM comparator. The PWM comparator drives the logic that controls the MOSFET gate drivers. These drivers control the turn on and turn off of the high- and low-side MOSFETs. As the error signal varies the PWM duty cycle is adjusted up and down to counteract the error. This interaction is normal load modulation and can be seen in a slight jitter on the trailing edge of the PWM signal. The resulting PWM signal at the VSW switching node is integrated by the LC filter to deliver the desired DC output voltage. Very low steady state duty cycles occur when the desired output is much smaller than the input (i.e. 24 V input to 1.2 V output). In this case, the error signal will be closer to 1 V. Very high duty cycles occur when the desired output is closer to the input (i.e. 5 V input to 3.3 V output). In this case, the error signal is closer to 2 V. As can be seen, in these cases the error signal may have limited headroom for control under severe load transient conditions. This can result an asymmetrical transient response characteristic and slightly longer regulation recovery times for either the load acquisition or load shedding. Open Loop Transfer Function The following discussion derives the equations for the open loop transfer function. The technique for selecting the poles and zeros for optimized loop stability is then presented. For this analysis we are considering the LC filter approximation given in Figure 4 and are not considering the impedance of the load. However, most output impedances can be modeled using the lumped circuit approximation shown in Figure 4. One exception is the use of a π filter with a roll off frequency that is inside the loop bandwidth. In this case, derivation of the transfer function that includes the phase and gain effects of this filter is important. In some cases, π filters can reduce gain margin and cause marginal stability if not considered thoroughly. The loop gain transfer function is broken into four blocks, each representing a different part of the buck converter. The four blocks and their frequency domain equations are as follows: Block 1 - GLC: Output LC filter consisting of L1, C4, C5 and R6 GLC = SR6 • C5 + 1 S R6 • C4 • C5 • L1 + S L1 • (C4 + C5) + SR6 • C5 + 1 3 2 Block 2 - GSP: Output voltage sampling network composed of C1, R1 and R2 S+ G SP = S+ 1 R1 • C1 1 R1 • R2 • C1 R1 + R2 Block 3 - GPWM: PWM modulation gain that equals to VIN/ΔVOSC, where ΔVOSC = saw tooth peak to peak voltage G PWM = VIN ΔVOSC Block 4 - GCOMP: Amplifier compensator with components of C2, C3, R4, R5 and the amplifier gain gM, which is a function of frequency. S+ S2 + S ( 1 R5 • C2 GCOMP = g M • 1 • C3 1 1 1 1 + + )+ R5 • C2 R4 • C3 R5 • C3 R4 • R5 • C2 • C3 Resistor R4 value should be very large compared to R5. The purpose of R4 is to eliminate non-monotonic output behavior during rapidly pulsed off-then-on line transients. R4 provides a fast discharge path for C3 and resets the error signal at COMP to zero before the line input pulses back on. Ideally, R4 can be ignored for the purposes of the loop transfer function. Ignoring R4 gives the following simplified transfer function for Block 4. 1 R5 • C2 = • SC3 1 S+ C2 • C3 R5 • C2 + C3 gM S+ G COMP The overall open loop transfer function for this system, GOL, is then the product of the four transfer functions derived for each block. G OL = G LC • G SP • G PWM • G COMP Converting to the logarithm form we have G OL (dB) = G LC (dB) + GSP (dB) + G PWM (dB) + G COMP (dB) www.vishay.com 10 Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 SiC413 Vishay Siliconix Compensation Considerations The criterion for unconditional stability of a closed loop system is that the open loop transfer function has the following attributes. 1. The magnitude of the open loop transfer function must cross through 0 dB with a slope of - 20 dB per decade 2. The phase shift of the open loop transfer function must be at least 45 at the frequency, at which the magnitude of the loop gain crosses through 0 dB 3. The phase shift should not be rapidly decreasing at loop gain slightly less than 0 dB To determine if these criterion are met the Bode plot of the transfer function is drawn. Before drawing the bode plot, the poles and zeros need to be located. The following discussion serves as a guide to selection of the component values for the compensation network. The compensation process begins by selecting loop bandwidth. We recommend that the 0 dB crossover frequency is set somewhere between 10 % and 20 % of switching frequency. The SiC413CB has a fixed switching frequency of 500 kHz. This means that the bandwidth of the loop can be set somewhere between 50 kHz and 100 kHz. This wide loop bandwidth, made possible by the ultra fast error amplifier in the SiC413CB, can provide excellent transient response and load regulation. It can be seen that within the LC filter block, there are generally three poles (denoted P1, P2 and P3) and one zero (denoted Z1). The double pole (P1 and P2) created by the LC filter is the dominant response characteristic of the system. The locations of these poles and zero depend strongly on the types of capacitors used in the output filter. Three cases will be analyzed as follows. Case 1: Output capacitors are a combination of those with ESR (C5. e.g. polymer or tantalum type) and those with no ESR or little ESR (C4. e.g. ceramic type) The poles and zero for this case are as follows fP1,P2 ≈ 1 2π L1 • (C4 + C5) This output filter configuration can be challenging because there is no zero to help boost the phase shift that is introduced by the LC double pole. Case 3: All capacitors have ESR, no ceramics. Ignoring C4 we have the following for the poles and zero f P1,P2,ESR = 1 2π L1 • C5 f P3,ESR f Z1,ESR = does not exist 1 2π • C5 • R6 This case is the best situation for loop compensation since no extra pole to add phase shift. The zero created with the ESR also helps reverse phase shift added by the LC filter. In the output voltage feedback network block there is one pole (denoted P4) and one zero (denoted Z2). The locations of the pole and zero are f P4 = 1 R1 • R2 • C1 2π • R1 + R2 f Z2 = = 1 2π • C1 • (R1//R2) 1 2π • C1 • R1 In this block C1 and R1 create the zero and C1 together with the parallel combination of R1 and R2 generates the pole. Adding a capacitor in parallel with R2 is not effective here. It does not change the zero location and move the pole closer to this zero and cancels out its effect on phase margin. From Figure 4 we can derive the DC expression for the output voltage. VO = (1 + R1 ) • VREF R2 From this equation and the equations of the pole and zero locations, it can be seen that pole and zero locations of this block have the following relationship f P4 VO = f Z2 VREF f P3 ≈ f Z1 ≈ 1 2π • C4 • R6 1 2π • C5 • R6 To meet the above stability criterion, the frequency of the zero fZ1 should be placed at a frequency lower than or equal to that at the double pole of fP1,P2. Pole fP3 should be located at a much higher frequency than fP1,P2. This requirement sets the boundaries on the values of C4, C5 and R6. Capacitor C4 has to be much smaller than C5. Case 2: Output capacitor is all ceramic MLCC Ignoring C5 and R6, the poles are as follows f P1,P2, MLCC = 2π f P3, MLCC 1 L1 • C4 and f Z1, MLCC will not exist This relationship means that when the output voltage VO is approaching the chip reference voltage, VREF, the zero in the sampling network has diminishing effect on boosting the loop phase margin. In other words, the value if adding C1 is more apparent when the output voltage is high relative to VREF and becomes smaller at lower output voltages. Therefore, the use of this capacitor is optional for low voltage conversions (e.g. 1.2 V output or lower). To make the zero fZ2 work for compensation of the control loop it should to be placed at a frequency that is less than or equal to the frequency of the LC double pole location. Block 3 is a DC transfer block and therefore has no pole and zero. It only affects the DC gain of open loop transfer function. This can affect phase margin as increasing the DC loop gain can increase the loop bandwidth and reduce phase margin and visa versa. www.vishay.com 11 Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 SiC413 Vishay Siliconix The amplifier compensation block is where the designer works hard to compensate the loop to achieve an unconditionally stable closed loop system. This block generally has two poles (denoted P5 and P6) and one zero (denoted Z3) as shown in the equation. The locations of these poles and zero are f P5 = 0 f P6 = 1 2π • R5 • f Z3 = C2 • C3 C2 + C3 To make the zero fZ3 and pole fP6 work for increasing phase margin the zero should be placed at a frequency lower than and the pole much higher than the LC double pole frequency. In general, as soon as the output LC filter is determined, the dominant double pole is fixed. Then the compensation design will be a "try and use" process based on above theory. Usually a network analyzer is used to confirm the loop stability. To make a control system stable the solution is infinite, meaning there are lots of combinations of C1, C2, C3, R1, R4 and R5 that can make the system stable. But a designer's job is to find the optimized one that both makes the system stable and has the best transient response. 1 2π • R5 • C2 VO VIN High-side MOSFET Driver Q1 C1 R1 R3 + R2 Transconductance Amplifier + C2 R4 VREF = 0.6 V R5 C3 Sawtooth Comparator L1 VO Low-side MOSFET Driver Q2 C4 C5 2.0 V 1.0 V R6 Figure 4. Control and Compensation Network www.vishay.com 12 Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 SiC413 Vishay Siliconix PCB Layout As in the design of any switching dc-to-dc converter, a good PCB layout ensures successful transition from design to production. One of a few drawbacks of switching converters is the noise generated by the high frequency switching and coupled by parasitic inductance and capacitance. However, noise levels can be reduced or minimized if a PCB is well laid out. The following is a guidance on SiC413 layout. Input Capacitors: C1 through to C6 are the input capacitors. They are placed side by side together to form a block and this block sits right beside SiC413's VIN and GND pins. This placement minimizes the distance between VIN pin, capacitors and chip’s ground, which minimizes the possibility of noise injected in VIN pin. Also the MLCC with smallest value (0.01 µF) is placed closest to VIN pin, and then MLCC with larger values (0.1 µF, 10 µF) and the last, the electrolytic. This is because their ESRs are getting larger and larger from small value MLCC to large value MLCC and then electrolytic capacitor. Output Capacitors: C17 through to C20 are the output capacitors. They are placed the same way as input capacitors. Decoupling Capacitors of VREG: C7 and C8, are placed right beside GND pin on their negative sides. Their positive sides are connected to the chip's VREG pin through two vias from the bottom of the PCB. The trace distance should be kept less than 10 mm. Boot Capacitor: C14 is the boot capacitor. R5 is added to allow flexibility for adjusting the high-side MOSFET driving current to reduce possible noise. Compensation Network: C9, C10, R6 and R10 form this network. These components should be placed in a tight group. This group then should be in close proximity to the COMP pin. Trace lengths between the components should be minimized. Output Sampling Network: R7, C15, R9 and R11 constitute the output voltage sampling network. These components should be placed in a tight grouping and in close proximity to the FB pin. Since SiC413 has only one GND pin, this makes the chip more sensitive to noise coming from GND. Therefore R11 is added to perform as a filter to remove any possible noise from ground. Grounding: Separate analog and power ground paths are recommended for optimal noise reduction in the SiC413CB converter. These grounds should both be connected at the GND pin. Connect the ground pin of the input and output capacitors to the power ground. Connect the ground pin for the VREG decoupling caps, the compensation network grounds, and the output voltage sampling network grounds to the analog ground. It is preferred to use low inductance ground planes when ever possible. If single sided board is being used then try to keep the ground traces short and going a star configuration at the GND pin. Power Traces: The power path is formed starting at VIN. It then branches to PGND and VSW to VOUT. The trace thickness for the power path should be kept to a minimum of 50 mils. Placement of components should focus on keeping these traces as short as possible to minimize parasitic inductance and resistances. They have minimum 50 mil trace width (at the VIN pin area) and this segment is very short, which is good enough for the power level handled by this chip. Figure 6 and Figure 7 below show a recommended board layout for converters using SiC413CB. Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 www.vishay.com 13 SiC413 www.vishay.com 14 C7 4.7 µF R1 100K EN U1 SiC413 C8 0.1 µF Vishay Siliconix 8 FB VREG VIN GND VSW 4 BOOT 3 EN 2 COMP 1 7 6 5 1 VIN C9 100 pF C10 10 nF R10 750K J1 VIN C2 10 µF C3 10 µF R11 20K C14 0.1 µF L1 10 µH C5 0.1 µF C6 0.01 µF C4 10 µF R5 0R + C1 100 µF R6 6K65 1 J2 VIN_GND SIC413 SCHEMATIC FOR THE SUGGESTED PCB LAYOUT J3 VO 1 C15 3.3 nF R7 10K Vo Figure 5. Reference Board Schematic + C17 100 µF C16 C R9 2K21 C18 100 µF + + C19 100 µF C20 4.7 µF R8 R C21 C J4 VO_GND 1 Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 SiC413 Vishay Siliconix SUGGESTED PCB LAYOUT Figure 6. PCB Layout - Top Layer Figure 7. PCB Layout - Bottom Layer BILL OF MATERIALS FOR THE SUGGESTED PCB LAYOUT VIN = 12 V, VOUT = 3.3 V Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 QTY 1 3 3 1 1 1 2 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reference C1 C2, C3, C4 C5, C8, C14 C6 C7 C9 C10, C15 C16, C21 C17 C18, C19 C20 J1 J2 J3 J4 L1 R1 R5 R6 R7 R8 R9 R10 R11 U1 Part 100 µF 10 µF 0.1 µF 0.01 µF 4.7 µF 100 pF 3.3 nF Not populated 100 µF 100 µF 4.7 µF VIN VIN_GND VO VO_GND 10 µH 100K 0R 6K65 10K Not populated 2K21 750K 20K SiC413 50 V 50 V 50 V 50 V 50 V 50 V 50 V 50V Voltage 35 V 25 V 50 V 50 V 10 V 50 V 50 V 50 V 20 V 20 V 16 V PCB Footprint D6.3X11.2-D0.6X2.5 SM/C_1210 SM/C_0603 SM/C_0402 SM/C_0805 SM/C_0603 SM/C_0603 SM/C_0603 595D-D 595D-D SM/C_1206 Probe Hook Probe Hook Probe Hook Probe Hook IHLP2525 SM/C_0603 SM/C_0603 SM/C_0603 SM/C_0603 SM/C_0603 SM/C_0603 SM/C_0603 SM/C_0603 SO-8 CRCW06032K21FKEA CRCW0603750KFKEA CRCW060320K0FKEA SiC413 595D107X9020D2T 595D107X9020D2T C3216X7R1C106M 1540-2 1540-2 1540-2 1540-2 IHLP2525EZER100M01 CRCW0603100KFKEA CRCW06030000FKEA CRCW06036K65FKEA CRCW060310K0FKEA Part Number ECA-1VHG101I TMK325B7106MN-T VJ0603Y104KXACW1BC VJ0402Y103KXACW1BC LMK212B7475KG-T VJ0603Y102KXACW1BC VJ0603Y333KXACW1BC Manufacturer Panasonic Taiyo Yuden Vishay Vishay Taiyo Yuden Vishay Vishay Vishay Vishay Vishay TDK Keystone Keystone Keystone Keystone Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 www.vishay.com 15 SiC413 Vishay Siliconix PACKAGE DIMENSIONS SOIC (NARROW): 8-LEAD JEDEC Part Number: MS-012 8 7 6 5 E 1 2 3 4 H S D 0.25 mm (Gage Plane) A h x 45 C All Leads q L 0.101 mm 0.004" e B A1 MILLIMETERS DIM. A A1 B C D E e H h L q S 5.80 0.25 0.50 0° 0.44 Min. 1.35 0.10 0.35 0.19 4.80 3.80 1.27 BSC 6.20 0.50 0.93 8° 0.64 0.228 0.010 0.020 0° 0.018 Max. 1.75 0.20 0.51 0.25 5.00 4.00 Min. 0.053 0.004 0.014 0.0075 0.189 0.150 INCHES Max. 0.069 0.008 0.020 0.010 0.196 0.157 0.050 BSC 0.244 0.020 0.037 8° 0.026 ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498 Figure 10. SO-8 dimensions Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?69057. www.vishay.com 16 Document Number: 69057 S09-2250-Rev. D, 26-Oct-09 Package Information Vishay Siliconix SOIC (NARROW): 8-LEAD JEDEC Part Number: MS-012 8 7 6 5 E 1 2 3 4 H S D 0.25 mm (Gage Plane) A h x 45 C All Leads q L 0.101 mm 0.004" e B A1 MILLIMETERS DIM A A1 B C D E e H h L q S 5.80 0.25 0.50 0° 0.44 Min 1.35 0.10 0.35 0.19 4.80 3.80 1.27 BSC 6.20 0.50 0.93 8° 0.64 0.228 0.010 0.020 0° 0.018 Max 1.75 0.20 0.51 0.25 5.00 4.00 Min 0.053 0.004 0.014 0.0075 0.189 0.150 INCHES Max 0.069 0.008 0.020 0.010 0.196 0.157 0.050 BSC 0.244 0.020 0.037 8° 0.026 ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498 Document Number: 71192 11-Sep-06 www.vishay.com 1 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1