SIC714CD10-T1-E3

SiC714CD10 Vishay Siliconix Fast Switching MOSFETs With Integrated Driver PRODUCT SUMMARY Input Voltage Range Output Voltage Range Operating Frequency Continuous Output Current Peak Efficiency Optimized Duty Cycle Ratio 3.3 to 15 V 0.5 to 6 V 100 kHz to 1 MHz Up to 27 A > 94 % at 300 kHz 10 % FEATURES • Low-side MOSFET control pin for prebias start-up • Undervoltage Lockout for safe operation • Internal boostrap diode reduces component count • Break-Before-Make operation • Turn-on/Turn-off Capability • Compatible with any single or multi-phase PWM controller • Low profile, thermally enhanced PowerPAK® MLF 10 x 10 Package PowerPAK MLF 10 x 10 1 APPLICATIONS • DC-to-DC Point-of-Load Converters - 3.3 V, 5 V, or 12 V Intermediate BUS - Examples - 12 VIN/0.8 - 2.5 VOUT - 5 VIN/0.8 - 1.5 VOUT • Servers and Computers Bottom View Ordering Information: SiC714CD10-T1 SiC714CD10-T1-E3 (Lead (Pb)-free) *see page 2 for peak temperature • Single and Multi-Phase Conversion DESCRIPTION The SiC714CD10 is an integrated solution which contains two PWM-optimized MOSFETs (high side and low side MOSFETs) and a driver IC. Integrating the driver allows better optimization of Power MOSFETs. This minimizes the losses and provides better performance at higher frequency. The SiC714CD10 is packed in Vishay Siliconix’s high performance PowerPAK MLF 10 x 10 package. Compact copacking of components helps to reduce stray inductance, and hence increases efficiency. FUNCTIONAL BLOCK DIAGRAM CBOOT VIN UVLO VDD SHDN + - BBM SW VDD PWM SYNC CGND PGND Figure 1. * Pb containing terminations are not RoHS compliant, exemptions may apply. Document Number: 73569 S-62659–Rev. C, 25-Dec-06 www.vishay.com 1 SiC714CD10 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Logic Supply Logic Inputs Common Switch Node Drain Voltage Bootstrap Voltage Maximum Power Dissipation (Measured at 25 °C ) Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) a, b Symbol VDD VPWM VSW VIN VBOOT PD Tj, Tstg Steady State 7 7.3 30 30 SW + 7 6 - 65 to 125 240 Unit V W °C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Drain Voltage Logic Supply Input Logic PWM Voltage Bootstrap Capacitor Symbol VIN VDD VPWM CBOOT Steady State 3.0 to 15 4.5 to 5.5 5 100 n to 1 µ Unit V F THERMAL RESISTANCE RATINGS Parameterc Maximum Junction-to-Case Maximum Junction-to-Ambient (PCB = Copper 25 mm x 25 mm) Symbol RthJC Steady State RthJA Typical 2.1 50 Maximum 2.6 75 Unit °C/W Notes: a. See Reliability Manual for profile. The PowerPAK MLF 10 x 10 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot guaranteed and is not required to ensure adequate bottom side soldering interconnection. b. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. c. Junction-to-case thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with the thermal impedance of the PC board pads to ambient (RthJA = RthJC + RthPCB-A). It can also be used to estimate chip temperature if power dissipation and the lead temperature of heat carrying (drain) lead is known. www.vishay.com 2 Document Number: 73569 S-62659–Rev. C, 25-Dec-06 SiC714CD10 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Specified TA = 25 °C 4.5 V < VDD < 5.5 V, 4.5 V < VD1 < 20 V Limits Min 4.5 VDD = 4.5 V, SYNC = H, PWM = H, SHDN = H VDD = 4.5 V, SYNC = H, PWM = H, SHDN = L VDD = 5 V, fclk = 250 kHzc VDD = 5 V, fclk = 0.7 MHz c Parameter Controller Logic Voltage Logic Current (Static) Symbol VDD IDD(EN) IDD(DIS) IDD1(DYN) IDD2(DYN) Typa Max 5.5 Unit V µA 1166 120 27.5 Logic Current (Dynamic) Logic Input Logic Input (VPWM) Logic Input Voltage (VSYNC) Logic Input Voltage (VSHDN) Input Voltage Hysteresis (PWM) Logic Input Current Protection Break-Before-Make Reference Under-Voltage Lockout Under-Voltage Lockout Hysteresis MOSFETs Drain-Source Voltage Drain-Source On-State Resistancea Diode Forward Voltagea Dynamicb, c Turn On Delay Time Turn Off Delay Time High Low mA 59.5 2.5 1.35 2.0 2.0 400 mV µA 117 120 2.4 3.5 4 0.4 20 High-Side Low-Side High-Side Low-Side 22 10.2 3 0.7 0.67 12.75 3.6 1.1 1.1 V mΩ V 4.25 V V VPWMH VPWML VSYNC VSHDN VHYS ISHDN IPWM VBBM VUVLO VH VDS rDS(on)1 rDS(on)2 VSD1 VSD2 td(on) td(off) VDD = 5 V, SYNC = H, SHDN = H VDD = 5 V, PMW = H, SHDN = H VDD = 5 V, PMW = H, SYNC = H VDD = 5.5 V, SHDN = 0 V VDD = 5.5 V, PMW = 5.5 V VDD = 5.5 V VDD = 5 V, SYNC = H, SHDN = H ID = 250 µA VDD = 5 V, ID = 10 A TA = 25 °C IS = 2 A, VGS = 0 V 50 % - 50 %c 66 32 ns Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. Using application board SiDB766707. Document Number: 73569 S-62659–Rev. C, 25-Dec-06 www.vishay.com 3 SiC714CD10 Vishay Siliconix TIMING DIAGRAM SHDN SYNC PWM HS MOSFET Gate LS MOSFET Gate SW td(on) td(off) Figure 2. APPLICATION INFORMATION (25 °C, unless noted, LFM = 0) 94 92 300 kHz 90 Total Loss (W) Efficiency (%) 88 86 84 82 80 78 76 0 10 20 30 Output Current – (A) 500 kHz 700 kHz 7 6 5 500 kHz 4 3 2 1 0 0 5 10 15 20 25 30 Output Current – (A) 300 kHz 700 kHz 9 8 Figure 3. Total Efficiency 12VIN/1.3 VOUT Notes: a. Experimental results using an evaluation board with a specific set of operating conditions. Figure 4. Total Loss 12 VIN/1.3 VOUT www.vishay.com 4 Document Number: 73569 S-62659–Rev. C, 25-Dec-06 SiC714CD10 Vishay Siliconix PIN CONFIGURATION PowerPAK MLF 10 mm x 10 mm (Bottom View) SW SW SW SW SW SW SW SW SW VIN VIN VIN VIN VIN VIN VIN 62 NC 61 58 56 55 52 53 54 57 59 60 65 66 64 67 63 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 (SW) CGND Driver Tab Low-Side MOS Tab VIN High-Side MOS Tab 68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VIN VIN VIN VIN VIN VIN VIN VIN VIN NC CGND CBOOT NC CBOOT VDD NC NC 25 23 18 27 26 24 22 21 20 19 32 30 28 33 NC 31 29 34 NC SW NC CGND PWM NC VDD NC VDD NC SYNC NC NC NC NC SHDN TRUTH TABLE SHDN L H H H H SYNC X L L H H PWM X L H L H HS MOSFET OFF OFF ON OFF ON LS MOSFET OFF OFF OFF ON OFF PIN DESCRIPTION Pin Number 1 - 9, 62 - 68 10, 13, 16 - 18, 20, 22, 25, 11, 24 11, 24 12, 14 15, 19, 21 23 27 28 35 - 51 26, 52 - 60 Symbol VIN NC CGND CBOOT VDD PMW SYNC SHDN PGND SW Description Input-Voltage (High-Side MOSFET Drain) No Connect Control Ground. Should be connected to PGND externally Contol Ground. Should be connected to PGND externally Connection pin for Bootstrap Capacitor for Upper MOSFET Logic Supply Voltage - decoupling to GND with a CAP is strongly recommended Pulse Width Modulation (PWM) Signal Input Disable Low-Side MOSFET Drive Disable All Functions (Active Low) Power Ground (Low-Side MOSFET Source) Connection Pin for Output Inductor (High-Side MOSFET Source/Low-Side MOSFET Drain) Document Number: 73569 S-62659–Rev. C, 25-Dec-06 www.vishay.com 5 SiC714CD10 Vishay Siliconix DEVICE OPERATION Pulse Width Modulator (PWM) This is a CMOS compatible logic input that receives the drive signals from the controller circuit. The PWM signal drives the buck switch. Break-Before-Make (BBM) The SiC714CD10 has an intrenal break-before-make function to ensure that both high-side and low-side MOSFETs are not turned on the same time. The low-side MOSFET will not turn on until the high-side gate drive voltage is less than VBBM, thus ensuring that the high-side MOSFET is turned off. This parameter is not user adjustable. SHDN CMOS logic signal. In the low state, the SHDN disables both high-side and low-side MOSFET’s. Capacitor to Boot Input (CBOOT) Connected to VDD by an internal diode via the CBOOT pin, the boot capacitor is used to sustain rail for the high-side MOSFET gate drive circuit. Under Voltage Lockout (UVLO) During the start up cycle, the UVLO disables the gate drive holding high-side and low-side MOSFET’s low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. The UVLO is not user adjustable. SYNC Pin for Pre-Bias Start-Up The low side MOSFET can be individually enable or disabled by using the SYNC pin. In the low state (SYNC = low), the low-side MOSFET is turned off. In the high state, the low-side MOSFET is enabled and follows the PWM input signal (see timing diagram, Figure 2). SYNC is a CMOS compatible logic input and is used for a pre–biased output voltage. Voltage Input (VIN) This is the power input to the drain of the high-side Power MOSFET. This pin is connected to the high power intermediate BUS rail. Switch Node (SW) The Switch node is the circuit PWM regulated output. This is the output applied to the filter circuit to deliver the regulated high output for the buck converter. Power Ground (PGND) This is the output connection from the source of the low-side MOSFET. This output is the ground return loop for the power rail. It should be externally connected to CGND. Control Ground (CGND) This is the control voltage return path for the driver and logic input circuitry to the SiC714CD9. This should externally connected to PGND. APPLICATION CIRCUIT 3.3 V to 16 V Power Up Sequence: The presence of VDD prior to applying the VIN and PWM is recommended to ensure a safe turn on Power Down Sequence: The sequence should be reverse of the on sequence, turn off the VIN before turning off the VDD. 5V VDD CBOOT VIN Q1 SW CBOOT L VOUT + LS Q2 PGND PGND HS SYNC DC-DC Controller PWM SHDN CGND CGND MOSFET Drive Circuitry with Break-BeforeMake Figure 7. The SiC711CD10 has a built-in delay time that is optimized for the MOSFET pair. When the PWM signal goes low, the high-side driver will turn off, after circuit delay (tdoff), and the output will start to ramp down, (tf). After a further delay, the low-side driver turns on. When the PWM goes high, the low-side driver turns off, (tdon). As the body diode starts to conduct, the high-side MOSFET turns on after a short dalay. The delay is minimized to limit body diode conduction. The output then ramps up, (tr). www.vishay.com 6 Document Number: 73569 S-62659–Rev. C, 25-Dec-06 SiC714CD10 Vishay Siliconix TYPICAL APPLICATION 12 V 5V VDD SYNC SHDN PWM CGND VIN CBOOT SW PGND SiC714CD10 VDD SYNC PWM1 PWM Control Circuit PWM2 PWM3 PWM4 SHDN PWM CGND VIN CBOOT SW PGND SiC714CD10 VOUT VDD SYNC SHDN PWM CGND VIN CBOOT SW PGND SiC714CD10 VDD SYNC SHDN PWM CGND VIN CBOOT SW PGND SiC714CD10 Figure 8. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73569. Document Number: 73569 S-62659–Rev. C, 25-Dec-06 www.vishay.com 7 Package Information Vishay Siliconix PowerPAKr MLF 10 10 2x 9 0.10 C A 0.08 C A D D/2 D1 N D1/2 A A2 2x 0.10 C B 4 P P D4 b D2 0.10 M C A B 0.05 M C A1 A3 4 4 D3 D2/2 N 1 2 3 Pin 1 ID 0.20 R. 5 6 E1/2 0.80 DIA E/2 1 2 3 0.45 E3 E2/2 0.25 min B q C Side View L Seating Plane 0.25 min (Nd−1)Xe Ref. e D4 Bottom View 4 b A1 Section “C−C” Scale: None 10 2x 0.10 C B 2x 0.10 C A Top View CC C L C L e Terminal Tip Odd Terminal Side e Even Terminal Side EXPOSED PAD VARIATIONS (Millimeters) D2 Min 7.95 E2 Max Min 8.25 7.95 D3 Max Min 8.25 3.15 E3 Max Min 3.45 4.15 D4 Max Min 4.45 3.15 E4 Max Min 3.45 3.25 Nom 8.10 Nom 8.10 Nom 3.30 Nom 4.30 Nom 3.30 Nom 3.40 Max Min 3.55 4.25 Nom 4.40 E4 D5 Max 4.55 EXPOSED PAD VARIATIONS (Inches) D2 Min 0.313 E2 Max Min 0.325 0.313 D3 Max Min 0.325 0.124 E3 Max Min 0.136 0.163 D4 Max Min 0.175 0.124 E4 Max Min 0.136 0.128 D5 Max Min 0.140 0.167 Nom 0.319 Nom 0.319 Nom 0.130 Nom 0.169 Nom 0.130 Nom 0.134 Nom 0.173 NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Die thickness allowable is 0.305-maximum (0.12-inches maximum) Dimensioning and tolerancing conform to ASME Y14.5M-1994. N is the total number of terminals. Pad from measuring, Nd is the number of terminals in the X-direction and Ne is the number of terminals in the Y-direction. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. The pin #1 identifier must exist on the top surface of the package. The identifier may be an indentation mark or othe feature of the package body. Exact shape and size of this feature is optional. Millimeters will govern. Package warpage maximum is 0.08 mm. Applied for exposed pad and terminals exclude embedding part of exposed. Applied only for terminals. www.vishay.com Document Number: 73280 14-Feb-05 (Ne−1)Xe Ref. E1 E2 E Max 0.179 1 of 2 Package Information Vishay Siliconix PowerPAKr MLF 10 10 DIMENSIONS MILLIMETERS* Dim A A1 A2 A3 b D D1 e INCHES Min — 0.000 — 0.007 Min — 0.00 — Nom Max 0.90 0.05 0.80 0.30 Nom 0.033 — 0.026 0.008 REF 0.009 0.394 BSC 0.384 BSC 0.020 BSC 0.394 BSC 0.384 BSC 0.024 68 17 17 0.017 — Max 0.035 0.002 0.031 0.012 NOTE 10 0.85 0.01 0.65 0.20 REF 0.18 0.23 10.00 BSC 9.75 BSC 0.50 BSC E 10.00 BSC E1 9.75 BSC L 0.50 0.60 N 68 Nd 17 Ne 17 P 0.24 0.42 q — — * Use millimeters as the primary measurement. ECN: T-04698—Rev. A, 14-Feb-05 DWG: 5944 4 0.75 0.020 0.030 3 3 3 0.024 12_ 0.60 12_ 0.009 — www.vishay.com 2 Document Number: 73280 14-Feb-05 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1