SIC734CD9-T1

SiC734CD9 Vishay Siliconix Fast Switching MOSFETs With Integrated Driver PRODUCT SUMMARY Input Voltage Range Output Voltage Range Operating Frequency Continuous Output Current Peak Efficiency Optimized Duty Cycle Ratio 3.3 to 24 V 0.5 to 6 V 100 kHz to 1 MHz Up to 25 A 92.8 10 % FEATURES • Low-side MOSFET control pin for pre-bias start-up • Undervoltage Lockout for safe operation • Internal boostrap diode reduces component count • Break-Before-Make operation • Turn-on/Turn-off Capability • Compatible with any single or multi-phase PWM controller • Low profile, thermally enhanced PowerPAK® MLF 9 x 9 Package PowerPAK MLF 9 x 9 APPLICATIONS • DC-to-DC Point-of-Load Converters - 3.3 V, 5 V, or 12 V Intermediate BUS - Examples - 12 VIN/0.8 - 2.5 VOUT - 5 VIN/0.8 - 1.5 VOUT • Servers and Computers • Single and Multi-Phase Conversion Bottom View Ordering Information: SiC734CD9-T1 DESCRIPTION The SiC734CD9 is an integrated solution which contains two PWM-optimized MOSFETs (high side and low side MOSFETs) and a driver IC. Integrating the driver allows better optimization of Power MOSFETs. This minimizes the losses and provides better performance at higher frequency. The SiC734CD9 is packed in Vishay Siliconix’s high performance PowerPAK MLF 9 x 9 package. Compact co-packing of components helps to reduce stray inductance, and hence increases efficiency. FUNCTIONAL BLOCK DIAGRAM VDD CBOOT VIN UVLO SHDN + - BBM SW VDD PWM SYNC CGND PGND Figure 1. Document Number: 73672 S-62656–Rev. C, 25-Dec-06 www.vishay.com 1 SiC734CD9 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Logic Supply Logic Inputs Common Switch Node Drain Voltage Bootstrap Voltage Maximum Power Sissipation (Measured at 25 °C ) Operating Juncyion and Storage Temperature Range Soldering Recommendations (Peak Temperature) a, b Symbol VDD VPWM VSW VIN CBOOT PD Tj, Tstg Steady State 7 7.3 30 30 SW + 7 6 - 65 to 125 225 Unit V W °C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Drain Voltage Logic Supply Input Logic PWM Voltage Bootstrap Capacitor Symbol VIN VDD VPWM CBOOT Steady State 3.3 to 24 4.5 to 5.5 5 100 n to 1 µ Unit V F THERMAL RESISTANCE RATINGS Parameterc Maximum Junction-to-Case Maximum Junction-to-Ambient (PCB = Copper 25 mm x 25 mm) Symbol RthJC Steady State RthJA Typical 3.5 60 Maximum 4.5 75 Unit °C/W Notes: a. See Reliability Manual for profile. The PowerPAK MLF 9 x 9 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot guaranteed and is not required to ensure adequate bottom side soldering interconnection. b. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. c. Junction-to-case thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with the thermal impedance of the PC board pads to ambient (RthJA = RthJC + RthPCB-A). It can also be used to estimate chip temperature if power dissipation and the lead temperature of heat carrying (drain) lead is known. www.vishay.com 2 Document Number: 73672 S-62656–Rev. C, 25-Dec-06 SiC734CD9 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Specified TA = 25 °C 4.5 V < VDD < 5.5 V, 4.5 V < VIN < 20 V Limits Min 4.5 VDD = 4.5 V, SYNC = H, PWM = H, SHDN = H VDD = 4.5 V, SYNC = H, PWM = H, SHDN = L VDD = 5 V, fPWM = 250 kHzc VDD = 5 V, fPWM = 700 kHz c Parameter Controller Logic Voltage Logic Current (Static) Symbol VDD IDD(EN) IDD(DIS) IDD1(DYN) IDD2(DYN) High VPWMH VPWML VSYNC VSHDN VHYS ISHDN Typa Max 5.5 Unit V µA 1185 115 24 Logic Current (Dynamic) Logic Input Logic Input (VPWM) Logic Input Voltage (VSYNC) Logic Input Voltage (VSHDN) Input Voltage Hysteresis (PWM) Logic Input Current Protection Break-Before-Make Reference Under-Voltage Lockout Under-Voltage Lockout Hysteresis MOSFETs Drain-Source Voltage Drain-Source On-State Resistancea Diode Forward Voltagea Dynamicb, c Turn On Delay Time Turn Off Delay Time Low mA 52 2.5 1.35 2.0 2.0 400 mV µA 117 114 2.4 3.5 4.1 0.4 30 High-Side Low-Side High-Side Low-Side 32 9.5 3.7 0.7 0.67 12.3 4.5 1.1 1.1 4.25 V V VDD = 5 V, SYNC = H, SHDN = H VDD = 5 V, PMW = H, SHDN = H VDD = 5 V, PMW = H, SYNC = H VDD = 5.5 V, SHDN = 0 V VDD = 5.5 V, PMW = 5.5 V VDD = 5.5 V VDD = 5 V, SYNC = H, SHDN = H ID = 250 µA VDD = 5 V, ID = 10 A TA = 25 °C IS = 2 A, VGS = 0 V IPWM VBBM VUVLO VH VDS rDS(on)1 rDS(on)2 VSD1 VSD2 td(on) td(off) V mΩ V 58 50 % - 50 %c 31 ns Notes: a. Pulse test; pulse width ≤ 300 ms, duty cycle ≤ 2 %. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. Using application board SiDB766706. Document Number: 73672 S-62656–Rev. C, 25-Dec-06 www.vishay.com 3 SiC734CD9 Vishay Siliconix TIMING DIAGRAM SHDN SYNC PWM HS MOSFET Gate LS MOSFET Gate SW td(on) td(off) Figure 2. APPLICATION INFORMATIONa (25 °C, unless noted, LFM = 0) 96 94 92 90 88 300 kHz 86 84 700 kHz 82 80 3 5 7 9 11 13 15 17 19 21 23 25 Output Current – (A) 1 0 3 5 7 9 11 13 15 17 19 21 23 25 Output Current – (A) 500 kHz Total Loss (W) Efficiency (%) 7 6 700 kHz 5 500 kHz 4 300 kHz 3 2 Figure 3. Total Efficiency 12 VIN/1.3 VOUT Notes: a. Experimental results using an evaluation board with a specific set of operating conditions. Figure 4. Total Loss 12 VIN/1.3 VOUT www.vishay.com 4 Document Number: 73672 S-62656–Rev. C, 25-Dec-06 SiC734CD9 Vishay Siliconix PIN CONFIGURATION PowerPAK MLF 9 mm x 9 mm (Bottom View) SW SW SW SW SW VIN 30 27 28 29 31 25 VIN PGND PGND PGND PGND PGND PGND PGND PGND 24 23 22 21 20 19 18 17 CGND (SW) VIN Driver Tab Low-Side MOS Tab High-Side MOS Tab 26 32 VIN 1 2 3 VIN VIN VIN 4 5 6 7 8 VIN CGND CBoot CBoot VDD 11 9 16 PGND 15 PGND 14 SHDN 13 SYNC 12 CGND 10 VDD VDD PWM TRUTH TABLE SHDN L H H H H SYNC X L L H H PWM X L H L H HS MOSFET OFF OFF ON OFF ON LS MOSFET OFF OFF OFF ON OFF PIN DESCRIPTION Pin Number 1 - 4, 30 - 32 5, 12 6, 7 8, 9, 10 11 13 14 15 - 24 25 - 29 Symbol VIN CGND CBOOT VDD PMW SYNC SHDN PGND SW Description Input-Voltage (High-Side MOSFET Drain) Control Ground. Should be connected to PGND externally Connection pin for Bootstrap Capacitor for High-Side MOSFET Logic Supply Voltage - decoupling to GND with a CAP is strongly recommended Pulse Width Modulation (PWM) Signal Input Disable Low-Side MOSFET Drive Disable All Functions (Active Low) Power Ground (Low-Side MOSFET Source) Connection Pin for Output Inductor (High-Side MOSFET Source/Low-Side MOSFET Drain) Document Number: 73672 S-62656–Rev. C, 25-Dec-06 www.vishay.com 5 SiC734CD9 Vishay Siliconix DEVICE OPERATION Pulse Width Modulator (PWM) This is a CMOS compatible logic input that receives the drive signals from the controller circuit. The PWM signal drives the buck switch. Break-Before-Make (BBM) The SiC730CD9 has an intrenal break-before-make function to ensure that both high-side and low-side MOSFETs are not turned on the same time. The low-side MOSFET will not turn on until the high-side gate drive voltage is less than VBBM, thus ensuring that the high-side MOSFET is turned off. This parameter is not user adjustable. SHDN CMOS logic signal. In the low state, the SHDN disables both high-side and low-side MOSFET’s. Capacitor to Boot Input (CBOOT) Connected to VDD by an internal diode via the CBOOT pin, the boot capacitor is used to sustain rail for the high-side MOSFET gate drive circuit. Under Voltage Lockout (UVLO) During the start up cycle, the UVLO disables the gate drive holding high-side and low-side MOSFET’s low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. The UVLO is not user adjustable. SYNC Pin for Pre-Bias Start-Up The low side MOSFET can be individually enable or disabled by using the SYNC pin. In the low state (SYNC = low), the low-side MOSFET is turned off. In the high state, the low-side MOSFET is enabled and follows the PWM input signal (see timing diagram, Figure 2). SYNC is a CMOS compatible logic input and is used for a pre–biased output voltage. Voltage Input (VIN) This is the power input to the drain of the high-side Power MOSFET. This pin is connected to the high power intermediate BUS rail. Switch Node (SW) The Switch node is the circuit PWM regulated output. This is the output applied to the filter circuit to deliver the regulated high output for the buck converter. Power Ground (PGND) This is the output connection from the source of the low-side MOSFET. This output is the ground return loop for the power rail. It should be externally connected to CGND. Control Ground (CGND) This is the control voltage return path for the driver and logic input circuitry to the SiC730CD9. This should externally connected to PGND. APPLICATION CIRCUIT 3.3 V to 16 V Power Up Sequence: The presence of VDD prior to applying the VIN and PWM is recommended to ensure a safe turn on Power Down Sequence: The sequence should be reverse of the on sequence, turn off the VIN before turning off the VDD. 5V VDD CBOOT VIN Q1 SW CBOOT L VOUT + LS Q2 PGND PGND HS SYNC DC-DC Controller PWM SHDN CGND CGND MOSFET Drive Circuitry with Break-BeforeMake Figure 7 The SiC714CD10 has a built-in delay time that is optimized for the MOSFET pair. When the PWM signal goes low, the high-side driver will turn off, after circuit delay (tdoff), and the output will start to ramp down,(t f ). After a further delay, the low-side driver turns on. The SiC734CD9 has a built-in delay time that is optimized for the MOSFET pair. When the PWM signal goes low, the highside driver will turn off, after circuit delay (tdoff), and the output will start to ramp down, (tf). After a further delay, the lowside driver turns on. www.vishay.com 6 When the PWM goes high, the low-side driver turns off,(t don). As the body diode starts to conduct, the high-side MOSFET turns on after a short delay . The delay is minimized to limit body diode conduction. The output then ramps up,(tr). When the PWM goes high, the low-side driver turns off, (tdon). As the body diode starts to conduct, the high-side MOSFET turns on after a short dalay. The delay is minimized to limit body diode conduction. The output then ramps up, (tr). Document Number: 73672 S-62656–Rev. C, 25-Dec-06 SiC734CD9 Vishay Siliconix TYPICAL APPLICATION 12 V 5V VDD SYNC SHDN PWM CGND VIN CBOOT SW PGND SiC734CD9 VDD SYNC PWM1 PWM Control Circuit PWM2 PWM3 PWM4 SHDN PWM CGND VIN CBOOT SW PGND SiC734CD9 VOUT VDD SYNC SHDN PWM CGND VIN CBOOT SW PGND SiC734CD9 VDD SYNC SHDN PWM CGND VIN CBOOT SW PGND SiC734CD9 Figure 8. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73672. Document Number: 73672 S-62656–Rev. C, 25-Dec-06 www.vishay.com 7 Package Information Vishay Siliconix PowerPAKr MLF 9 9 2x 10 0.10 C A 0.08 C 4 4 4 0.45 P P b D2 D6 D3 D2/2 N 1 2 3 Pin 1 ID 0.20 R. 0.10 M C A B A D D/2 D1 N D1/2 A A2 2x 0.10 C B A1 A3 5 6 E/2 0.80 DIA E3 0.25 min 2x 0.10 C B 2x 0.10 C A B Top View q C Side View Seating Plane L D5 0.25 min e D4 (Nd−1)Xe Ref. Bottom View CC C L C L 4 b A1 Section “C−C” Scale: None 11 e Terminal Tip Odd Terminal Side e Even Terminal Side NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Die thickness allowable is 0.305-maximum (0.12-inches maximum) Dimensioning and tolerancing conform to ASME Y14.5M-1994. N is the total number of terminals. Nd is the number of terminals in the X-direction and Ne is the number of terminals in the Y-direction. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. The pin #1 identifier must exist on the top surface of the package. The identifier may be an indentation mark or other feature of the package body. Exact shape and size of this feature is optional. Millimeters will govern. The shape shown on four corners are not actual I/O. Package warpage maximum is 0.08 mm. Applied for exposed pad and terminals exclude embedding part of exposed pad from measuring. Applied only for terminals. Document Number: 73386 02-May-05 E4 E2/2 E1 E www.vishay.com (Ne−1)Xe Ref. 1 2 3 E1/2 E2 1 of 2 Package Information Vishay Siliconix PowerPAKr MLF 9 9 EXPOSED PAD VARIATIONS (Millimeters) D2 Min 6.95 E2 Max 7.25 D3 Max 7.25 E3 Max 2.45 Nom 7.10 Min 6.95 Nom 7.10 Min 2.15 Nom 2.30 Min 3.55 Nom 3.70 Max 3.85 D4 Min 2.75 E4 Max 3.05 D5 Max 3.15 D6 Max 3.95 Nom 2.90 Min 2.85 Nom 3.00 Min 3.65 Nom 3.80 Min 4.25 Nom 4.40 Max 4.55 EXPOSED PAD VARIATIONS (Inches) D2 Min 0.274 E2 Max 0.285 D3 Max 0.285 E3 Max 0.096 Nom 0.280 Min 0.274 Nom 0.280 Min 0.085 Nom 0.091 Min 0.140 Nom 0.146 Max 0.152 D4 Min 0.108 E4 Max 0.120 D5 Max 0.124 D6 Max 0.155 Nom 0.114 Min 0.112 Nom 0.118 Min 0.144 Nom 0.150 Min 0.167 Nom 0.173 Max 0.179 DIMENSIONS MILLIMETERS* Dim A A1 A2 A3 b D D1 e INCHES Min — 0.000 — 0.010 Min — 0.00 — Nom Max 0.90 0.05 0.80 0.35 Nom 0.033 — 0.026 0.008 REF 0.012 0.354 BSC 0.344 BSC 0.031 BSC 0.354 BSC 0.344 BSC 0.024 32 8 8 0.017 — Max 0.035 0.002 0.031 0.014 NOTE 11 0.85 0.01 0.65 0.20 REF 0.25 0.30 9.00 BSC 8.75 BSC 0.80 BSC E 9.00 BSC E1 8.75 BSC L 0.50 0.60 N 32 Nd 8 Ne 8 P 0.24 0.42 q — — * Use millimeters as the primary measurement. ECN: T-05143—Rev. A, 02-May-05 DWG: 5948 4 0.75 0.020 0.030 3 3 3 0.024 12_ 0.60 12_ 0.009 — www.vishay.com 2 Document Number: 73386 02-May-05 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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