SIC769ADB

SiC769ACD Vishay Siliconix Integrated DrMOS Power Stage DESCRIPTION The SiC769ACD is an integrated solution that contains PWM optimized n-channel MOSFETs (high side and low side) and a full featured MOSFET driver IC. The device complies with the Intel DrMOS standard for desktop and server Vcore power stages. The SiC769ACD delivers up to 35 A continuous output current and operates from an input voltage range of 3 V to 16 V. The integrated MOSFETs are optimized for output voltages in the ranges of 0.8 V to 2.0 V with a nominal input voltage of 12 V. The device can also deliver very high power at 5 V output for ASIC applications. The SiC769ACD incorporates an advanced MOSFET gate driver IC. This IC accepts a single PWM input from the VR controller and converts it into the high side and low side MOSFET gate drive signals. The driver IC is designed to implement the skip mode (SMOD) function for light load efficiency improvement. Adaptive dead time control also works to improve efficiency at all load points. The SiC769ACD has a thermal warning (THDN) that alerts the system of excessive junction temperature. The driver IC includes an enable pin, UVLO and shoot through protection. The SiC769ACD is optimized for high frequency buck applications. Operating frequencies in excess of 1 MHz can easily be achieved. The SiC769ACD is packaged in Vishay Siliconix high performance PowerPAK MLP6 x 6 package. Compact co-packaging of components helps to reduce stray inductance, and hence increases efficiency. FEATURES • Integrated Gen III MOSFETs and DrMOS compliant gate driver IC • Enables Vcore switching at 1 MHz • Easily achieve > 90 % efficiency in multi-phase, low output voltage solutions • Low ringing on the VSWH pin reduces EMI • Pin compatible with DrMOS 6 x 6 version 3.0 • Tri-state PWM input function prevents negative output voltage swing • 3.3 V logic levels on PWM • MOSFET threshold voltage optimized for 5 V driver bias supply • Automatic skip mode operation (SMOD) for light load efficiency • Under-voltage lockout • Built-in bootstrap Schottky diode • Adaptive deadtime and shoot through protection • Thermal shutdown warning flag • Low profile, thermally enhanced PowerPAK® MLP 6 x 6 40 pin package • Halogen-free according to IEC 61249-2-21 definition • Compliant to RoHS directive 2002/95/EC APPLICATIONS • CPU and GPU core voltage regulation • Server, computer, workstation, game console, graphics boards, PC SiC769ACD APPLICATION DIAGRAMM 5V VDRV GH V IN V IN VCIN SMOD DSBL# PWM THDN PWM Controller BOOT VSWH PHASE VO Gate Driver SiC769ACD CGND PGND Figure 1 GL Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 www.vishay.com 1 SiC769ACD Vishay Siliconix ORDERING INFORMATION Part Number SiC769ACD-T1-GE3 SiC769ADB Package PowerPAK MLP66-40 Reference board ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Input Voltage Switch Node Voltage (DC) Drive Input Voltage Control Input Voltage Logic Pins Boot Voltage DC (referenced to CGND) Boot Voltage < 200 ns Transient (referenced to CGND) Boot to Phase Voltage DC Boot to Phase Voltage < 200 ns Ambient Temperature Range Maximum Junction Temperature Storage Junction Temperature Symbol VIN VSW VDRV VCIN VPWM, VDSBL#, VTHDN, VSMOD VBS VBS_PH TA TJ TSTG - 65 Min. - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 40 Max. 20 20 7.0 7.0 VCIN + 0.3 27 29 7 9 125 150 150 260 °C V Unit Soldering Peak Temperature Note: a. TA = 25 °C and all voltages referenced to PGND = CGND unless otherwise noted. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Input Voltage Control Input Voltage Drive Input Voltage Switch Node Symbol VIN VCIN VDRV VSW_DC Min. 3.0 4.5 4.5 12 Typ. 12 Max. 16 5.5 5.5 16 V Unit Note: a. Recommended operating conditions are specified over the entire temperature range, and all voltages referenced to PGND = CGND unless otherwise noted. THERMAL RESISTANCE RATINGS Parameter Maximum Power Dissipation at TPCB = 25 °C Maximum Power Dissipation at TPCB = 100 °C Thermal Resistance from Junction to Top Thermal Resistance from Junction to PCB Symbol PD_25C PD_100C Rth_J_TOP Rth_J_PCB Typ. Max. 25 10 15 5 Unit W °C/W www.vishay.com 2 Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 SiC769ACD Vishay Siliconix ELECTRICAL SPECIFICATIONS Test Conditions Unless Specified VDSBL# = VSMOD = 5 V, VIN = 12 V, VVDRV = VVCIN = 5 V, TA = 25 °C VDSBL# = 0 V, no switching VCIN Control Input Current IVCIN VDSBL# = 5 V, no switching VDSBL# = 5 V, fs = 300 kHz, D = 0.1 Drive Input Current (Dynamic) Bootstrap Supply Bootstrap Switch Forward Voltage Control Inputs (PWM, DSBL#, SMOD) PWM Rising Threshold PWM Falling Threshold PWM Tristate Rising Threshold PWM Tristate Falling Threshold PWM Tristate Rising Threshold Hysteresis PWM Tristate Falling Threshold Hysteresis Tristate Hold-Off Timeb PWM Input Current SMOD, DSBL# Logic Input Voltage Pull Down Impedance THDN Output Low Protection Thermal Warning Flag Set Thermal Warning Flag Clear Thermal Warning Flag Hysteresis Under Voltage Lockout (VCIN) Under Voltage Lockout (VCIN) Under Voltage Lockout Hysteresis (VCIN) High Side Gate Discharge Resistorb VUVLO VUVLO_HYST RHS_DSCRG VVDRV = VVCIN = 0 V; VIN = 12 V Rising, on threshold Falling, off threshold 2.5 150 135 15 3.3 2.9 400 20.2 3.9 V mV kΩ °C Vth_pwm_r Vth_pwm_f Vth_tri_r Vth_tri_f Vhys_tri_r Vhys_tri_f tTSHO IPWM VLOGIC_LH VLOGIC_LH RTHDN VTHDNL VPWM = 3.3 V VPWM = 0 V Rising (low to high) Falling (high to low) 5 kΩ resistor pull-up to VCIN 40 0.04 2.0 0.8 1.8 0.8 0.9 1.6 2 1.0 1.3 1.8 220 240 150 22 - 17 2.3 1.2 1.8 2 mV ns µA V Ω V V VBS Diode VVCIN = 5 V, forward bias current 2 mA 0.60 0.75 V IVDRV fs = 300 kHz, D = 0.1 fs = 1000 kHz, D = 0.1 Parameter Power Supplies Symbol Min. Typ.a 20 400 600 14 40 Max. Unit µA 18 54 mA Notes: a. Typical limits are established by characterization and are not production tested. b. Guaranteed by design. MOSFET SPECIFICATIONS Test Conditions Unless Specified VVCIN = VDSBL# = 5 V, VVIN = 12 V, TA = 25 °C VGS = 0 V, IDS = 250 µA VGH = 5 V, resistance measured at package pins VGS = 0 V, IDS = 250 µA VGL = 5 V, resistance measured at package pins 20 1.7 Typ.a Parameter High Side Symbol VDS RDS(on)_H VDS Min. 20 Max. Unit V mΩ V mΩ 6.0 Low Side RDS(on)_L Note: a. Typical MOSFET parameters are provided as a design guide. Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 www.vishay.com 3 SiC769ACD Vishay Siliconix TIMING SPECIFICATIONS Test Conditions Unless Specified VVDRV = VVCIN = VDSBL# = 5 V, VVIN = 12 V, TA = 25 °C 25 % of PWM to 90 % of GH 10 % to 90 % of GH 90 % to 10 % of GH 75 % of PWM to 90 % of GL 10 % to 90 % of GL 90 % to 10 % of GL 10 % of GL to 10 % of GH 10 % of GH to 10 % of GL 10 Parameter Turn Off Propagation Delay High Sidea Rise Time High Side Fall Time High Side Turn Off Propagation Delay Low Sidea Rise Time Low Side Fall Time Low Side Dead Time Rising Dead Time Falling Symbol td_off_HS tr_HS tf_HS td_off_LS tr_LS tf_LS tdead_on tdead_off Min. 10 Typ. 20 8 8 20 8 8 15 15 Max. 30 Unit 30 ns Note: a. Min. and Max. are not 100 % production tested. TIMING DEFINITIONS PWM 75 % 25 % GH 90 % GL 10 % SW 10 % 90 % 1 234 56 78 Region 1 2 3 4 5 6 7 Definition Turn off propagation delay LS Fall time LS Dead time rising Rise time HS Turn off propagation delay HS Fall time HS Dead time falling Symbol td_off_LS tf_LS tdead_on tr_HS td_off_HS tf_HS tdead_off tr_LS 8 Rise time LS Note: GH is referenced to the high side source. GL is referenced to the low side source. www.vishay.com 4 Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 SiC769ACD Vishay Siliconix SiC769ACD BLOCK DIAGRAM VDRV VCIN GH UVLO VIN BOOT DSBL# Thermal Warning PHASE THDN AST C NTL DCM DETECT VSWH PWM Tristate PWM SMOD PGND CGND GL Figure 2 Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 www.vishay.com 5 SiC769ACD Vishay Siliconix DETAILED OPERATIONAL DESCRIPTION PWM Input with Tristate Function The PWM input receives the PWM control signal from the VR controller IC. The PWM input is designed to be compatible with standard controllers using two state logic (H and L) and advanced controllers that incorporate Tristate logic (H, L and Tristate) on the PWM output. For two state logic, the PWM input operates as follows. When PWM is driven above Vth_pwm_r the low side is turned off and the high side is turned on. When PWM input is driven below Vth_pwm_f the high side turns off and the Low side turns on. For Tristate logic, the PWM input operates as above for driving the MOSFETs. However, there is an third state that is entered into as the PWM output of Tristate compatible controller enters its high impedance state during shut-down. The high impedance state of the controller's PWM output allows the SiC769ACD to pull the PWM input into the Tristate region (see the Tristate Voltage Threshold Diagram below). If the PWM input stays in this region for the Tristate Hold-Off Period, tTSHO, both high side and low side MOSFETs are turned off. This function allows the VR phase to be disabled without negative output voltage swing caused by inductor ringing and saves a Schottky diode clamp. The PWM and Tristate regions are separated by hysteresis to prevent false triggering. The SiC769ACD incorporates logic thresholds that are compatible with 3.3 V logic. Disable (DSBL#) In the low state, the DSBL# pin shuts down the driver IC and disables both high-side and low-side MOSFET. In this state, the standby current is minimized. If DSBL# is left unconnected an internal pull-down resistor will pull the pin down to CGND and shut down the IC. Diode Emulation Mode (SMOD) Skip Mode When SMOD pin is low the diode emulation mode is enabled. This is a non-synchronous conversion mode that improves light load efficiency by reducing switching losses. Conducted losses that occur in synchronous buck regulators when inductor current is negative are also reduced. Circuitry in the gate drive IC detects when inductor current crosses zero and automatically stops switching the low side MOSFET. See SMOD Operation Diagram for additional details. This function can also be used for a pre-biased output voltage. If SMOD is left unconnected, an internal pull up resistor will pull the pin up to VCIN (Logic High) to disable the diode emulation function. Thermal Shutdown Warning (THDN) The THDN pin is an open drain signal that flags the presence of excessive junction temperature. Connect a maximum of 20 kΩ to pull this pin up to VCIN. An internal temperature sensor detects the junction temperature. The temperature threshold is 150 °C. When this junction temperature is exceeded the THDN flag is set. When the junction temperature drops below 135 °C the device will clear the THDN signal. The SiC769ACD does not stop operation when the flag is set. The decision to shutdown must be made by an external thermal control function. Voltage Input (VIN) This is the power input to the drain of the high-side Power MOSFET. This pin is connected to the high power intermediate BUS rail. Switch Node (VSWH and PHASE) The Switch node VSWH is the circuit PWM regulated output. This is the output applied to the filter circuit to deliver the regulated high output for the buck converter. The PHASE pin is internally connected to the switch node VSWH. This pin is to be used exclusively as the return pin for the BOOT capacitor. A 20.2 kΩ resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET in the event that VCIN goes to zero while VIN is still applied. Ground connections (CGND and PGND) PGND (power ground) should be externally connected to CGND (control signal ground). The layout of the Printed Circuit Board should be such that the inductance separating the CGND and PGND should be a minimum. Transient differences due to inductance effects between these two pins should not exceed 0.5 V. Control and Drive Supply Voltage Input (VDRV,VCIN) VCIN is the bias supply for the gate drive control IC. VDRV is the bias supply for the gate drivers. It is recommended to separate these pins through a resistor. This creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the IC. Bootstrap Circuit (BOOT) The internal bootstrap switch and an external bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An integrated bootstrap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. Connect a boot strap capacitor with one leg tied to BOOT pin and the other tied to PHASE pin. Shoot-Through Protection and Adaptive Dead Time (AST) The SiC769ACD has an internal adaptive logic to avoid shoot through and optimize dead time. The shoot through protection ensures that both high-side and low-side MOSFET are not turned on the same time. The adaptive dead time control operates as follows. When PWM input goes high the LS gate starts to go low after a few ns. When this signal crosses through 1.7 V the logic to switch the HS gate on is activated. When PWM goes low the HS gate goes low. When the HS gate-to-source drive signal crosses through 1.7 V the logic to turn on the LS gate is activated. This feature helps to adjust dead time as gate transitions change with respect to output current and temperature. Under Voltage Lockout (UVLO) During the start up cycle, the UVLO disables the gate drive holding high-side and low-side MOSFET gate low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. The SiC769ACD also incorporates logic to clamp the gate drive signals to zero when the UVLO falling edge triggers the shutdown of the device. As an added precaution, a 20.2 kΩ resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET. www.vishay.com 6 Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 SiC769ACD Vishay Siliconix DEVICE TRUTH TABLE DSBL# Open L H H H H SMOD X X L L H H PWM X X L H H L GH L L L H H L GL L L H (IL > 0), L (IL ≤ 0) L L H TRISTATE PWM VOLTAGE THRESHOLD DIAGRAM PWM Vth_pwm_r Vth_tri_f Vth_tri_r Vth_pwm_f GH t TSHO GL t TSHO Figure 3 SMOD OPERATION DIAGRAM DSBL SMOD PWM GH GL VSW td(ON) td(OFF) IL > 0 IL = 0 Figure 4 Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 www.vishay.com 7 SiC769ACD Vishay Siliconix PIN CONFIGURATION 39 DSBL# 33 VSWH 40 PWM 35 VSWH 38 THDN 34 VSWH 37 CGND 31 VSWH 30 VSWH AGND P1 VSWH P3 VIN P2 29 VSWH 28 PGND 27 PGND 26 PGND 25 PGND 24 PGND 23 PGND 22 PGND 21 PGND 16 PGND 11 VIN 12 VIN 13 VIN 14 VIN 15 VSWH 17 PGND 18 PGND 19 PGND 20 PGND 32 VSWH SMOD 1 VCIN 2 VDRV 3 BOOT 4 CGND 5 GH 6 PHASE 7 VIN 8 VIN 9 VIN 10 Figure 5 - PowerPAK MLP 6 x 6 40P Pin Out - Top View PIN DESCRIPTION Pin Number 1 2 3 4 5, 37, PAD1 6 7 8 to 14, PAD2 15, 29 to 35, PAD3 16 to 28 36 38 39 40 Symbol SMOD VCIN VDRV BOOT CGND GH PHASE VIN VSWH PGND GL THDN DSBL# PWM Disable low side gate operation. Active low. This will be the bias supply input for control IC (5 V). IC bias supply and gate drive supply voltage (5 V). High side driver bootstrap voltage pin for external bootstrap capacitor. Control signal ground. It should be connected to PGND externally. All pins internally connected. Gate signal output pin for high side MOSFET. Pin for monitoring. Return pin for the HS bootstrap capacitor. Connect a 0.1 µF ceramic capacitor from this pin to the boot pin (4). Input voltage for power stage. It is the drain of the high-side MOSFET. It is the phase node between high side MOSFET source and low side MOSFET drain. It should be connected to an output inductor. All pins internally connected. Power ground. Gate signal output pin for low side MOSFET. Pin for monitoring. Thermal shutdown open drain output. Use a 10K pull up resistor to VCIN. Disable pin. Active low. PWM input logic signal. Compatible with Tristate controller function. Description www.vishay.com 8 36 GL Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 SiC769ACD Vishay Siliconix ELECTRICAL CHARACTERISTICS 1.0 0.9 18 0.8 0.7 IDRV (mA) ICIN (mA) 0.6 0.5 0.4 0.3 0.2 8 0.1 0 - 40 - 25 - 10 5 6 - 40 - 25 - 10 5 16 14 12 10 20 20 35 50 65 80 95 110 125 140 Temperature (°C) 20 35 50 65 80 95 110 125 140 Temperature (°C) ICIN (mA) vs. Temperature at Frequency = 300 kHz D = 10 %, VCIN = VDRV = 5 V 1.3 IDRV (mA) vs. Temperature at Frequency = 300 kHz D = 10 %, VCIN = VDRV = 5 V 3.0 2.8 1.2 2.6 2.4 PWM TSH (V) 1.1 PWM TSH (V) 2.2 2.0 1.8 1.6 1.0 0.9 1.4 1.2 0.8 - 40 - 25 - 10 5 20 35 50 65 80 95 110 125 140 Temperature (°C) 1.0 - 40 - 25 - 10 5 20 35 50 65 80 95 110 125 140 Temperature (°C) PWM Falling Threshold (V) vs. Temperature (°C) VCIN = VDRV = 5 V 1.6 1.5 1.4 DSBL TSH (V) 1.3 1.2 1.1 1.0 0.9 - 40 - 25 - 10 5 DSBL TSH (V) 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 PWM Rising Threshold (V) vs. Temperature (°C) VCIN = VDRV = 5 V 20 35 50 65 80 95 110 125 140 Temperature (°C) 1.40 - 40 - 25 - 10 5 20 35 50 65 80 95 110 125 140 Temperature (°C) DSBL Falling Threshold (V) vs. Temperature (°C) VCIN = VDRV = 5 V Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 DSBL Rising Threshold (V) vs. Temperature (°C) VCIN = VDRV = 5 V www.vishay.com 9 SiC769ACD Vishay Siliconix ELECTRICAL CHARACTERISTICS 1.6 1.5 1.4 SMOD TSH (V) 1.3 1.2 1.1 1.0 0.9 - 40 - 25 - 10 5 SMOD TSH (V) 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 - 40 - 25 - 10 5 20 35 50 65 80 95 110 125 140 Temperature (°C) 20 35 50 65 80 95 110 125 140 Temperature (°C) SMOD Falling Threshold (V) vs. Temperature (°C) VCIN = VDRV = 5 V 60 SMOD Rising Threshold (V) vs. Temperature (°C) VCIN = VDRV = 5 V 50 50 45 40 IDRV (mA) ICIN (mA) 40 30 35 20 30 10 0 - 40 - 25 - 10 5 20 35 50 65 80 95 110 125 140 Temperature (°C) 25 - 40 - 25 - 10 5 20 35 50 65 80 95 110 125 140 Temperature (°C) ICIN + IDRV (mA) vs. Temperature at Frequency = 1 MHz D = 10 %, VCIN = VDRV = 5 V 2.6 2.4 2.2 PWM TSH (V) PWM TSH (V) 2.0 1.8 1.6 1.4 1.2 1.0 - 40 - 25 - 10 5 IDRV (mA) vs. Temperature at Frequency = 1 MHz D = 10 %, VCIN = VDRV = 5 V 1.6 1.5 1.4 1.3 1.2 1.1 20 35 50 65 80 95 110 125 140 Temperature (°C) 1.0 - 40 - 25 - 10 5 20 35 50 65 80 95 110 125 140 Temperature (°C) PWM Falling Tristate (V) vs. Temperature (°C) VCIN = VDRV = 5 V www.vishay.com 10 PWM Rising Tristate Threshold (V) vs. Temperature (°C) VCIN = VDRV = 5 V Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 SiC769ACD Vishay Siliconix ELECTRICAL CHARACTERISTICS 2.5 2.3 2.1 1.9 DSBL TSH (V) 1.7 1.5 1.3 1.1 0.9 0.7 0.5 4.7 DSBL Tsh (V) 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 0.5 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 VCIN (V) VCIN (V) DSBL Falling Threshold vs. VCIN 2.5 2.3 2.1 1.9 SMOD Tsh (V) 1.7 1.5 1.3 1.1 0.9 0.7 0.5 4.7 SMOD Tsh (V) 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 DSBL Rising Threshold vs. VCIN 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 0.5 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 VCIN (V) VCIN (V) SMOD Falling Threshold vs. VCIN 1.20 2.6 2.4 2.2 1.10 PWM Tsh (V) PWM Tsh (V) 2.0 1.8 1.6 1.4 0.95 1.2 1.0 4.7 SMOD Rising Threshold vs. VCIN 1.15 1.05 1.00 0.90 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 VCIN (V) VCIN (V) PWM Falling Threshold vs. VCIN PWM Rising Threshold vs. VCIN Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 www.vishay.com 11 SiC769ACD Vishay Siliconix ELECTRICAL CHARACTERISTICS VDRV/VCIN: 2 V/div VDRV/VCIN: 2 V/div VO: 0.5 V/div VIN: 5 V/div VO: 0.5 V/div VIN: 5 V/div t: 2 ms/div PWM: 2 V/div PWM: 2 V/div t: 20 ms/div t: 2 ms/div Startup with VIN Ramping Up VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz Power Off with VIN Ramping Down VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz DSBL#: 2 V/div VO: 0.5 V/div VO: 0.5 V/div t: 20 μs/div DSBL#: 2 V/div VSWH: 5 V/div VSWH: 5 V/div t: 0.5 ms/div Enable with VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz Disable with VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz VIN: 5 V/div VIN: 5 V/div VDRV/VCIN: 2 V/div VDRV/VCIN: 2 V/div VO: 0.5 V/div VO: 0.5 V/div PWM: 2 V/div PWM: 2 V/div t: 50 μs/div t: 200 μs/div PWM Start with VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz PWM Turn-off with VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz www.vishay.com 12 Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 SiC769ACD Vishay Siliconix ELECTRICAL CHARACTERISTICS VIN: 5 V/div VIN: 5 V/div VDRV/VCIN: 2 V/div VO: 0.5 V/div VO: 0.5 V/div VDRV/VCIN: 2 V/div PWM: 2 V/div PWM: 2 V/div t: 2 ms/div t: 10 ms/div Startup with VDRV/VCIN Ramping Up VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz Power Off with VDRV/VCIN Ramping Down VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz GH: 10 V/div GH: 10 V/div GL: 5 V/div GL: 5 V/div VSWH: 8 V/div VSWH: 8 V/div IL: 4 A/div IL: 4 A/div t: 0.5 μs/div t: 0.5 μs/div Switching Waveforms with SMOD Enabled VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz, IOUT = 0 A Switching Waveforms with SMOD Disabled VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz, IOUT = 4 A PWM: 1 V/div PWM: 1 V/div GH: 5 V/div GH: 5 V/div VSWH: 5 V/div VSWH: 5 V/div GL: 2 V/div GL: 2 V/div t: 10 μs/div t: 10 ns/div Switching Waveforms at PWM Rising Edge VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz, IOUT = 0 A Switching Waveforms at PWM Falling Edge VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz, IOUT = 0 A Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 www.vishay.com 13 SiC769ACD Vishay Siliconix ELECTRICAL CHARACTERISTICS PWM: 1 V/div PWM: 1 V/div GH: 5 V/div GH: 5 V/div VSWH: 5 V/div VSWH: 5 V/div GL: 2 V/div GL: 2 V/div t: 20 ns/div t: 10 ns/div Switching Waveforms at PWM Rising Edge VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz, IOUT = 30 A Switching Waveforms at PWM Falling Edge VIN = 12 V, VOUT = 1.2 V, fS = 500 kHz, IOUT = 30 A TYPICAL POWER LOSS IN SiC769ACD PowerPAK MLP66-40 PACKAGE 10 9 8 Total Power Loss (W) 7 6 5 4 3 2 1 0 300 kHz 400 kHz 500 kHz 0 3 6 9 12 15 18 21 24 27 30 33 36 IOUT (A) VIN = 12 V, VOUT = 1.2 V, VDRV = VCIN = 5 V; No Air Flow IHLP5050FDERR33M01 Inductor L = 330 nH, DCR = 0.83 mΩ Figure 6 - Total Power Loss www.vishay.com 14 Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 SiC769ACD Vishay Siliconix TYPICAL EFFICIENCY CURVES 92 91 90 89 Efficiency (%) 88 87 86 85 84 83 82 81 300 kHz 400 kHz 500 kHz 0 3 6 9 12 15 18 21 24 27 30 33 36 Load Current (A) VIN = 12 V, VOUT = 1.2 V, VDRV = VCIN = 5 V; No Air Flow IHLP5050FDERR33M01 Inductor L = 330 nH, DCR = 0.83 mΩ Figure 7 - Efficiency Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 www.vishay.com 15 SiC769ACD Vishay Siliconix PACKAGE DIMENSIONS K1 2x 56 Pin 1 dot by marking 2x 0.10 C B e A D 0.10 C A A 0.08 C A1 A2 0.41 31 30 K2 D2-1 40 1 Pin #1 dent 0.10 M C A B B 21 10 20 D2-3 (Nd-1)X e ref. D2-2 11 C Top View Side View Bottom View DIM A(8) A1 A2 b(4) D e E L N(3) Nd(3) Ne(3) D2-1 D2-2 D2-3 E2-1 E2-2 E2-3 K1 MILLIMETERS Min. 0.70 0.00 0.20 Nom. 0.75 0.20 ref. 0.25 6.00 BSC 0.50 BSC 6.00 BSC 0.35 0.40 40 10 10 1.45 1.45 2.35 4.35 1.95 1.95 1.50 1.50 2.40 4.40 2.00 2.00 0.73 BSC 1.55 1.55 2.45 4.45 2.05 2.05 0.057 0.057 0.095 0.171 0.076 0.076 0.45 0.013 0.30 0.078 Max. 0.80 0.05 Min. 0.027 0.000 INCHES Nom. 0.029 0.008 ref. 0.098 0.236 BSC 0.019 BSC 0.236 BSC 0.015 40 10 10 0.059 0.059 0.094 0.173 0.078 0.078 0.028 BSC 0.061 0.061 0.096 0.175 0.080 0.080 0.017 0.011 Max. 0.031 0.002 K2 0.21 BSC 0.008 BSC Notes: 1. Use millimeters as the primary measurement. 2. Dimensioning and tolerances conform to ASME Y14.5M-1994. 3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction . 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body . 6. Exact shape and size of this feature is optional. 7. Package warpage max. 0.08 mm. 8. Applied only for terminals. www.vishay.com 16 Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 E2-3 4 (Nd-1)X e ref. E2-1 MLP66-40 (6 mm x 6 mm) E E2-2 SiC769ACD Vishay Siliconix LAND PATTERN DIMENSIONS 2.200 0.276 2.200 0.200 0.276 0.100 0.600 0.100 0.100 0.100 0.100 0.025 0.025 1 1 1.700 40 0.100 40 0.320 0.310 2.600 0.100 0.100 4.600 0.100 0.100 Figure 8 - PowerPAK MLP 66-40 TAPE AND REEL CARRIER TAPE DIMENSIONS Ø 1.5 - 0.0 12.00 Ø 1.50 min. 1.75 ± 0.1 A + 0.1 2.00 ± 0.10 see note 3 0.30 ± 0.05 4.00 see note 1 R 0.3 max. 7.5 ± 0.1 see note 3 Bo 16.0 ± 0.3 A Ko Ao 0.25 Section A-A Ao = 6.30 Bo = 6.30 Ko = 1.10 R 0.25 Notes: 1. 10 sprocket hole pitch cumulative tolerance ± 0.2. 2. Camber in compliance with EIA 481. 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. Figure 9 - PowerPAK MLP 66-40 Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?65708. Document Number: 65708 S10-0113-Rev. B, 18-Jan-10 www.vishay.com 17 Package Information Vishay Siliconix PowerPAK® MLP66-40 CASE OUTLINE K1 2x 56 Pin 1 dot by marking 2x 0.10 C B e A D 0.10 C A A 0.08 C A1 A2 0.41 31 30 K2 D2-1 40 1 Pin #1 dent 0.10 M C A B B 21 10 20 D2-3 (Nd-1)X e ref. D2-2 11 C Top View Side View Bottom View DIM. A (8) A1 A2 b (4) D e E L N (3) Nd (3) Ne (3) D2-1 D2-2 D2-3 E2-1 E2-2 E2-3 K1 K2 MILLIMETERS MIN. 0.70 0.00 0.20 NOM. 0.75 0.20 ref. 0.25 6.00 BSC 0.50 BSC 6.00 BSC 0.35 0.40 40 10 10 1.45 1.45 2.35 4.35 1.95 1.95 1.50 1.50 2.40 4.40 2.00 2.00 0.73 BSC 0.21 BSC 1.55 1.55 2.45 4.45 2.05 2.05 0.057 0.057 0.095 0.171 0.076 0.076 0.45 0.013 0.30 0.078 MAX. 0.80 0.05 MIN. 0.027 0.000 INCHES NOM. 0.029 0.008 ref. 0.098 0.236 BSC 0.019 BSC 0.236 BSC 0.015 40 10 10 0.059 0.059 0.094 0.173 0.078 0.078 0.028 BSC 0.008 BSC 0.061 0.061 0.096 0.175 0.080 0.080 0.017 0.011 MAX. 0.031 0.002 ECN: T09-0195-Rev. A, 04-May-09 DWG: 5986 Notes 1. Use millimeters as the primary measurement 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994 3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body 6. Exact shape and size of this feature is optional 7. Package warpage max. 0.08 mm 8. Applied only for terminals Document Number: 64846 04-May-09 www.vishay.com 1 E2-3 4 (Nd-1)X e ref. E2-1 MLP66-40 (6 mm x 6 mm) E E2-2 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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