SIE806DF

SPICE Device Model SiE806DF Vishay Siliconix N-Channel 30-V (D-S) MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74165 S-60243Rev. A, 20-Feb-06 www.vishay.com 1 SPICE Device Model SiE806DF Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 1.1 3290 0.0014 0.0017 180 0.83 Measured Data Unit VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = 250 µA VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 25 A VGS = 4.5 V, ID = 25 A VDS = 15 V, ID = 25 A IS = 10 A V A 0.0015 0.0017 130 0.90 Ω S V Drain-Source On-State Resistancea Forward Transconductancea Forward Voltagea Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Ciss Coss Crss Qg Qgs Qgd VDS = 15 V, VGS = 10 V, ID = 20 A VDS = 15 V, VGS = 0 V, f = 1 MHz 9401 1096 385 174 83 VDS = 15 V, VGS = 4.5 V, ID = 20 A 23 9.5 13000 1150 550 165 75 23 9.5 nC pF Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 74165 S-60243Rev. A, 20-Feb-06 SPICE Device Model SiE806DF Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 74165 S-60243Rev. A, 20-Feb-06 www.vishay.com 3