SIHB24N65E-GE3

SiHB24N65E www.vishay.com Vishay Siliconix E Series Power MOSFET PRODUCT SUMMARY VDS (V) at TJ max. RDS(on) max. at 25 °C () Qg max. (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 122 21 37 Single D FEATURES 700 0.145 • Halogen-free According to IEC 61249-2-21 Definition • Low Figure-of-Merit (FOM) Ron x Qg • • • • • Low Input Capacitance (Ciss) Reduced Switching and Conduction Losses Ultra Low Gate Charge (Qg) Avalanche Energy Rated (UIS) Compliant to RoHS Directive 2002/95/EC APPLICATIONS D2PAK (TO-263) G • • • • S N-Channel MOSFET GD S Server and Telecom Power Supplies Switch Mode Power Supplies (SMPS) Power Factor Correction Power Supplies (PFC) Lighting - High-Intensity Discharge (HID) - Fluorescent Ballast Lighting • Industrial - Welding - Induction Heating - Motor Drives - Battery Chargers - Renewable Energy - Solar (PV Inverters) ORDERING INFORMATION Package Lead (Pb)-free and Halogen-free D2PAK (TO-263) SiHB24N65E-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage Gate-Source Voltage AC (f > 1 Hz) Continuous Drain Current (TJ = 150 °C) Pulsed Drain Currenta VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL VDS VGS ID IDM EAS PD TJ, Tstg TJ = 125 °C for 10 s dV/dt LIMIT 650 ± 20 30 24 16 70 2 508 250 - 55 to + 150 37 11 300c W/°C mJ W °C V/ns °C A V UNIT Linear Derating Factor Single Pulse Avalanche Energyb Maximum Power Dissipation Operating Junction and Storage Temperature Range Drain-Source Voltage Slope Reverse Diode dV/dtd Soldering Recommendations (Peak Temperature) Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 6 A. c. 1.6 mm from case. d. ISD  ID, dI/dt = 100 A/μs, starting TJ = 25 °C. S11-2088 Rev. B, 31-Oct-11 1 Document Number: 91477 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB24N65E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient Maximum Junction-to-Case (Drain) SYMBOL RthJA RthJC TYP. MAX. 62 0.5 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Input Resistance Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Current Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current IS ISM VSD trr Qrr IRRM TJ = 25 °C, IF = IS = 24 A, dI/dt = 100 A/μs, VR = 20 V MOSFET symbol showing the integral reverse p - n junction diode D SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VDS/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf Rg VGS = 0 V, ID = 250 μA Reference to 25 °C, ID = 250 μA VDS = VGS, ID = 250 μA VGS = ± 20 V VDS = 650 V, VGS = 0 V VDS = 520 V, VGS = 0 V, TJ = 125 °C VGS = 10 V I D = 12 A VDS = 8 V, ID = 5 A 650 2 - 0.72 0.120 7.1 2740 122 4 81 21 37 24 84 70 69 0.68 4 ± 100 1 10 0.145 122 48 126 105 104 - V V/°C V nA μA  S VGS = 0 V, VDS = 100 V, f = 1 MHz pF VGS = 10 V ID = 24 A, VDS = 520 V nC VDD = 520 V, ID = 24 A, VGS = 10 V, Rg = 9.1  f = 1 MHz, open drain ns  - 517 9.7 30 24 A 96 1.2 V ns μC A G S TJ = 25 °C, IS = 24 A, VGS = 0 V The information shown here is a preliminary product proposal, not a commercial product datasheet. Vishay Siliconix is not committed to produce this or any similar product. This information should not be used for design purposes, nor construed as an offer to furnish or sell such products. S11-2088 Rev. B, 31-Oct-11 2 Document Number: 91477 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB24N65E www.vishay.com TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Vishay Siliconix 80 3 ID, Drain-to-Source Current (A) RDS(on), Drain-to-Source On Resistance (Normalized) 60 TOP 15 V 14 V 13 V 12 V TJ = 25 °C 2.5 2 1.5 1 0.5 0 ID = 24 A 40 11 V 10 V VGS = 10 V 20 9V 5V 0 0 5 10 15 20 25 30 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 VDS, Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature 60 ID, Drain-to-Source Current (A) 40 Capacitance (pF) TOP 15 V 14 V 13 V 12 V 11 V 10 V 10 000 TJ = 150 °C 1000 Ciss VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 9V 20 8V 5V 0 0 5 10 15 20 25 30 100 Coss 10 Crss 1 0 100 200 300 400 500 600 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 80 24 VGS, Gate-to-Source Voltage (V) ID, Drain-to-Source Current (A) 20 16 12 8 4 0 60 VDS = 520 V VDS = 335 V VDS = 130 V 40 TJ = 150 °C 20 0 0 5 TJ = 25 °C 10 15 20 25 0 30 60 90 120 150 VDS, Drain-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S11-2088 Rev. B, 31-Oct-11 3 Qg, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91477 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB24N65E www.vishay.com Vishay Siliconix 100 25 ISD, Reverse Drain Current (A) 10 TJ = 150 °C ID, Drain Current (A) VGS = 0 V 20 15 TJ = 25 °C 1 10 5 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 25 50 75 100 125 150 VSD, Source-Drain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage TJ, Case Temperature (°C) Fig. 9 - Maximum Drain Current vs. Case Temperature 825 1000 Operation in this area limited by RDS(on) ID, Drain Current (A) 100 800 VDS, Drain-to-Source Brakdown Voltage (V) 775 750 725 700 675 10 Limited by RDS(on)* 1 100 μs TC = 25 °C TJ = 150 °C Single Pulse BVDSS Limited 1 1 ms 10 ms 0.1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified 650 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 10 - Temperature vs. Drain-to-Source Voltage Fig. 8 - Maximum Safe Operating Area 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case S11-2088 Rev. B, 31-Oct-11 4 Document Number: 91477 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB24N65E www.vishay.com Vishay Siliconix RD 10 V QG VDS VGS RG D.U.T. + - VDD QGS QGD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % VG Charge Fig. 12 - Switching Time Test Circuit Fig. 16 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. 50 kΩ 12 V VDS 90 % 0.2 µF 0.3 µF + 10 % VGS td(on) tr td(off) tf VGS 3 mA D.U.T. - VDS Fig. 13 - Switching Time Waveforms IG ID Current sampling resistors L Vary tp to obtain required IAS RG VDS Fig. 17 - Gate Charge Test Circuit D.U.T IAS + - V DD 10 V tp 0.01 Ω Fig. 14 - Unclamped Inductive Test Circuit VDS tp VDD VDS IAS Fig. 15 - Unclamped Inductive Waveforms S11-2088 Rev. B, 31-Oct-11 5 Document Number: 91477 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB24N65E www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer D.U.T. + - - + Rg • • • • dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Inductor current Body diode forward drop Ripple ≤ 5 % Note a. VGS = 5 V for logic level devices ISD Fig. 18 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91477. S11-2088 Rev. B, 31-Oct-11 6 Document Number: 91477 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 E 4 L1 4 4 A A c2 Gauge plane 0° to 8° D 1 L2 B B 2 C 3 C 5 H L3 Detail A L4 Detail “A” Rotated 90° CW scale 8:1 L A1 H B B Seating plane 2 x b2 2xb 0.010 M A M B 2xe c A E ± 0.004 M B 5 b1, b3 Base metal Plating D1 4 (c) c1 5 (b, b2) Lead tip Section B - B and C - C Scale: none E1 View A - A 4 MILLIMETERS DIM. A A1 b b1 b2 b3 c c1 c2 D MIN. 4.06 0.00 0.51 0.51 1.14 1.14 0.38 0.38 1.14 8.38 MAX. 4.83 0.25 0.99 0.89 1.78 1.73 0.74 0.58 1.65 9.65 MIN. INCHES MAX. 0.190 0.010 0.039 0.035 0.070 0.068 0.029 0.023 0.065 0.380 DIM. D1 E E1 e H L L1 L2 L3 L4 MILLIMETERS MIN. 6.86 9.65 6.22 2.54 BSC 14.61 1.78 15.88 2.79 1.65 1.78 0.25 BSC 4.78 5.28 MAX. 10.67 MIN. INCHES MAX. 0.420 - 0.160 0.000 0.020 0.020 0.045 0.045 0.015 0.015 0.045 0.330 0.270 0.380 0.245 0.100 BSC 0.575 0.070 - 0.625 0.110 0.066 0.070 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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