SIHFBC40LC-E3

IRFBC40LC, SiHFBC40LC Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) (Ω) Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 39 10 19 Single D FEATURES 600 V 1.2 • • • • • • • Ultra Low Gate Charge Reduced Gate Drive Requirement Enhanced 30 V, VGS Rating Reduced Ciss, Coss, Crss Extremely High Frequency Operation Repetitive Avalanche Rated Lead (Pb)-free Available Available RoHS* COMPLIANT TO-220 DESCRIPTION This new series of low charge Power MOSFETs achieve significantly lower gate charge over conventional Power MOSFETs. Utilizing the new LCDMOS technology, the device improvements are achieved without added product cost, allowing for reduced gate drive requirements and total system savings. In addition reduced switching losses and improved efficiency are achievable in a variety of high frequency applications. Frequencies of a few MHz at high current are possible using the new low charge Power MOSFETs. These device improvements combined with the proven ruggedness and reliability that are characteristic of Power MOSFETs offer the designer a new standard in power transistors for switching applications. G S G D S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free SnPb TO-220 IRFBC40LCPbF SiHFBC40LC-E3 IRFBC40LC SiHFBC40LC ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL VGS ID IDM EAS IAR EAR PD dV/dt TJ, Tstg LIMIT ± 30 6.2 3.9 25 1.0 530 6.2 13 125 3.0 - 55 to + 150 300d 10 1.1 UNIT V A W/°C mJ A mJ W V/ns °C lbf · in N·m TC = 25 °C for 10 s 6-32 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V, starting TJ = 25 °C, L = 25 mH, RG = 25 Ω, IAS = 6.2 A (see fig. 12). c. ISD ≤ 6.2 A, dI/dt ≤ 80 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91114 S-81567-Rev. A, 28-Jul-08 www.vishay.com 1 IRFBC40LC, SiHFBC40LC Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain) SYMBOL RthJA RthCS RthJC TYP. 0.50 MAX. 62 1.0 °C/W UNIT SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode D SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS ΔVDS/TJ VGS(th) IGSS IDSS RDS(on) gfs VGS = 0 V, ID = 250 µA Reference to 25 °C, ID = 1 mA VDS = VGS, ID = 250 µA VGS = ± 20 VDS = 600 V, VGS = 0 V VDS = 480 V, VGS = 0 V, TJ = 125 °C VGS = 10 V ID = 3.7 Ab VDS = 100 V, ID = 3.7 Ab 600 2.0 3.7 0.70 - 4.0 ± 100 100 500 1.2 - V V/°C V nA µA Ω S Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf LD LS VGS = 0 V VDS = 25 V f = 1.0 MHz, see fig. 5 - 1100 140 15 12 20 27 17 4.5 7.5 39 10 19 nH ns nC pF VGS = 10 V ID = 6.2 A, VDS = 360 V, see fig. 6 and 13b - VDD = 300 V, ID = 6.2 A RG = 9.1 Ω, RD = 47 Ω, see fig. 10b - Between lead, 6 mm (0.25") from package and center of die contact D - G S - 440 2.1 6.2 A 25 1.5 680 3.2 V ns µC G S TJ = 25 °C, IS = 6.2 A, VGS = 0 Vb TJ = 25 °C, IF = 6.2 A, dI/dt = 100 A/µsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. www.vishay.com 2 Document Number: 91114 S-81567-Rev. A, 28-Jul-08 IRFBC40LC, SiHFBC40LC Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 101 ID, Drain Current (A) 100 4.5 V ID, Drain Current (A) VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V Top 101 150 °C 25 °C 100 10-1 20 µs Pulse Width TC = 25 °C 10-1 100 101 102 10-2 10-2 91114_01 10-1 4 91114_03 20 µs Pulse Width VDS = 100 V 5 6 7 8 9 10 VDS, Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics, TC = 25 °C VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics RDS(on), Drain-to-Source On Resistance (Normalized) 101 ID, Drain Current (A) 100 VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V Top 3.5 3.0 2.5 2.0 1.5 1.0 0.5 ID = 6.2 A VGS = 10 V 4.5 V 10-1 10-2 10-2 91114_02 20 µs Pulse Width TC = 150 °C 10-1 100 101 102 0.0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 VDS, Drain-to-Source Voltage (V) 91114_04 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 2 - Typical Output Characteristics, TC = 150 °C Document Number: 91114 S-81567-Rev. A, 28-Jul-08 www.vishay.com 3 IRFBC40LC, SiHFBC40LC Vishay Siliconix 2400 2000 ISD, Reverse Drain Current (A) Capacitance (pF) VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd Ciss 1600 1200 Coss 800 400 0 100 101 Crss 101 150 °C 25 °C 100 0.6 91114_07 VGS = 0 V 0.8 1.0 1.2 1.4 91114_05 VDS, Drain-to-Source Voltage (V) VSD, Source-to-Drain Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage 20 VGS, Gate-to-Source Voltage (V) ID = 5.2 A VDS = 300 V 103 5 2 Operation in this area limited by RDS(on) 16 ID, Drain Current (A) 102 5 2 VDS = 240 V 12 VDS = 180 V 10 5 2 10 µs 100 µs 1 ms 10 ms TC = 25 °C TJ = 150 °C Single Pulse 0.1 2 5 8 1 5 2 4 For test circuit see figure 13 0.1 5 2 0 0 91114_06 10-2 8 16 24 32 40 91114_08 1 2 5 10 2 5 102 2 5 103 2 5 104 QG, Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Document Number: 91114 S-81567-Rev. A, 28-Jul-08 IRFBC40LC, SiHFBC40LC Vishay Siliconix RD VDS VGS RG D.U.T. + - VDD 10 V 7.0 6.0 Pulse width ≤ 1 µs Duty factor ≤ 0.1 % ID, Drain Current (A) 5.0 Fig. 10a - Switching Time Test Circuit 4.0 3.0 VDS 2.0 1.0 0.0 25 90 % 50 75 100 125 150 91114_09 TC, Case Temperature (°C) 10 % VGS td(on) tr td(off) tf Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms 10 Thermal Response (ZthJC) 1 0 − 0.5 PDM 0.2 0.1 0.1 0.05 0.02 0.01 10-2 10-5 10-4 10-3 10-2 0.1 Single Pulse (Thermal Response) t1 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 1 10 91114_11 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L Vary tp to obtain required IAS RG VDS tp VDD D.U.T. IA S 10 V tp 0.01 Ω IAS + V DD VDS VDS Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91114 S-81567-Rev. A, 28-Jul-08 Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5 IRFBC40LC, SiHFBC40LC Vishay Siliconix 1200 EAS, Single Pulse Energy (mJ) 1000 800 600 400 200 0 VDD = 50 V 25 50 75 100 ID 2.8 A 3.9 A Bottom 5.2 A Top 125 150 91114_12c Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. QG 12 V 50 kΩ 0.2 µF 0.3 µF 10 V QGS QGD D.U.T. + - VDS VG VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit www.vishay.com 6 Document Number: 91114 S-81567-Rev. A, 28-Jul-08 IRFBC40LC, SiHFBC40LC Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test + VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Inductor current Body diode forward drop Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 -For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91114. Document Number: 91114 S-81567-Rev. A, 28-Jul-08 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. 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Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1