SIHFI9610G-E3

IRFI9610G, SiHFI9610G Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) (Ω) Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration - 200 VGS = - 10 V 13 3.2 7.3 Single S FEATURES • Isolated Package • High Voltage Isolation = 2.5 kVRMS (t = 60 s; f = 60 Hz) • Sink to Lead Creepage Distance = 4.8 mm • P-Channel • Dynamic dV/dt Rating • Low Thermal Resistance • Lead (Pb)-free Available Available 3.0 RoHS* COMPLIANT TO-220 FULLPAK DESCRIPTION G GDS D P-Channel MOSFET Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The TO-220 FULLPAK eliminates the need for additional insulating hardware in commercial-industrial applications. The moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The FULLPAK is mounted to a heatsink using a single clip or by a single screw fixing. ORDERING INFORMATION Package Lead (Pb)-free SnPb TO-220 FULLPAK IRFI9640GPbF SiHFI9640G-E3 IRFI9640G SiHFI9640G ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque VGS at - 10 V TC = 25 °C TC = 100 °C SYMBOL VDS VGS ID IDM EAS IAR EAR PD dV/dt TJ, Tstg LIMIT - 200 ± 20 - 2.0 - 1.3 - 8.0 0.22 100 - 2.0 2.7 27 - 11 - 55 to + 150 300d 10 1.1 UNIT V A W/°C mJ A mJ W V/ns °C lbf · in N·m TC = 25 °C for 10 s 6-32 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 51 mH, RG = 25 Ω, IAS = - 2.0 A (see fig. 12). c. ISD ≤ - 2.0 A, dI/dt ≤ - 250 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91165 S-Pending-Rev. A, 16-Jun-08 www.vishay.com 1 WORK-IN-PROGRESS IRFI9610G, SiHFI9610G Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient Maximum Junction-to-Case (Drain) SYMBOL RthJA RthJC TYP. MAX. 65 4.6 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode D SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS ΔVDS/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf LD LS VGS = 0 V, ID = - 250 µA Reference to 25 °C, ID = - 1 mA VDS = VGS, ID = - 250 µA VGS = ± 20 V VDS = - 200 V, VGS = 0 V VDS = - 160 V, VGS = 0 V, TJ = 125 °C VGS = - 10 V ID = - 1.2 Ab Ab VDS = - 50 V, ID = - 1.2 - 200 - 2.0 0.7 - 0.22 - - 4.0 ± 100 - 100 - 500 3.0 - V V/°C V nA µA Ω S VGS = 0 V, VDS = - 25 V, f = 1.0 MHz, see fig. 5 - 180 66 12 12 17 19 15 4.5 7.5 13 3.2 7.3 nH ns nC pF VGS = - 10 V ID = - 2.0 A, VDS = - 160 V, see fig. 6 and 13b - VDD = - 100 V, ID = - 2.0 A, RG = 24 Ω, VGS = - 10 V, see fig. 10b - Between lead, 6 mm (0.25") from package and center of die contact D - G S - 130 700 - 2.0 A - 8.0 - 5.8 200 1050 V ns µC G S TJ = 25 °C, IS = - 2.0 A, VGS = 0 Vb TJ = 25 °C, IF = - 2.0 A, dI/dt = 100 A/µsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. www.vishay.com 2 Document Number: 91165 S-Pending-Rev. A, 16-Jun-08 IRFI9610G, SiHFI9610G Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 10 VGS -15V -10V -8.0V -7.0V -6.0V -5.5V -5.0V BOTTOM -4.5V TOP 10 TJ = 25°C -I D, Drain-to-Source Current (Α ) -I D, Drain-to-Source Current (A) T J = 150°C 1 -4.5V 0.1 1 0.01 0.1 1 20µs PULSE WIDTH Tj = 25°C 0 VDS = -50V 20µs PULSE WIDTH 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 10 100 -VDS, Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics, TC = 25 °C -VGS , Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics 10 TOP RDS(on) , Drain-to-Source On Resistance -I D, Drain-to-Source Current (A) 1 VGS -15V -10V -8.0V -7.0V -6.0V -5.5V -5.0V BOTTOM -4.5V 2.5 ID = -2.0A VGS = -10V 2.0 (Normalized) -4.5V 0.1 1.5 1.0 20µs PULSE WIDTH Tj = 150°C 0.01 0.1 1 10 100 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 -VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics, TC = 150 °C T J , Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91165 S-Pending-Rev. A, 16-Jun-08 www.vishay.com 3 IRFI9610G, SiHFI9610G Vishay Siliconix 400 350 300 10.0 VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds Crss = Cgd Coss = Cds + Cgd SHORTED -I SD, Reverse Drain Current (A) T J = 150°C C, Capacitance (pF) 250 200 150 Ciss 1.0 TJ = 25°C Coss 100 50 0 1 10 100 Crss 0.1 0.0 1.0 2.0 3.0 VGS = 0V 4.0 5.0 -VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage -VSD, Source-toDrain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage 20 ID= -2.0A 100 VDS= -160V VDS= -100V VDS= -40V -V GS, Gate-to-Source Voltage (V) 16 -I D, Drain-to-Source Current (A) OPERATION IN THIS AREA LIMITED BY R DS(on) 10 12 100µsec 1 1msec Tc = 25°C Tj = 150°C Single Pulse 10 100 -VDS , Drain-toSource Voltage (V) Fig. 8 - Maximum Safe Operating Area 8 4 FOR TEST CIRCUIT SEE FIGURE 13 10msec 0 0 2 4 6 8 10 12 14 Q G Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage 0.1 1000 www.vishay.com 4 Document Number: 91165 S-Pending-Rev. A, 16-Jun-08 IRFI9610G, SiHFI9610G Vishay Siliconix RD 2.0 VGS VDS D.U.T. + - VDD 1.6 RG -ID , Drain Current (A) 10 V 1.2 Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 0.8 Fig. 10a - Switching Time Test Circuit VDS 0.4 90 % 0.0 25 50 75 100 125 150 10 % VGS td(on) tr td(off) tf T J , Junction Temperature (°C) Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms 10 Thermal Response ( Z thJC ) D = 0.50 1 0.20 0.10 0.05 0.02 0.1 0.01 SINGLE PULSE ( THERMAL RESPONSE ) 0.01 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L VDS IAS + Driver 0.01 Ω 15 V D.U.T. IAS VDD A RG - 20 V tp tp VDS Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5 Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91165 S-Pending-Rev. A, 16-Jun-08 IRFI9610G, SiHFI9610G Vishay Siliconix 240 EAS, Single Pulse Avalanche Energy (mJ) 200 ID -0.9A -1.3A BOTTOM -2.0A TOP 160 120 80 40 0 25 50 75 100 125 150 Starting T J , Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ 12 V - 10 V QGS QG 0.2 µF 0.3 µF VG VGS - 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit www.vishay.com 6 Document Number: 91165 S-Pending-Rev. A, 16-Jun-08 + D.U.T. - QGD VDS IRFI9610G, SiHFI9610G Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + P.W. Period Ripple ≤ 5 % D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer RG Compliment N-Channel of D.U.T. for driver Driver gate drive D= D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current Body diode forward drop * VGS = - 5 V for logic level and - 3 V drive devices Fig. 14 - For P-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91165. Document Number: 91165 S-Pending-Rev. A, 16-Jun-08 + + • dV/dt controlled by RG • ISD controlled by duty factor "D" • D.U.T. - device under test + - VDD P.W. Period VGS = - 10 V* VDD ISD www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1