SIHFIB5N50L-E3

IRFIB5N50L, SiHFIB5N50L Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) (Ω) Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 45 13 23 Single D FEATURES 500 0.67 • Super Fast Body Diode Eliminates the Need for External Diodes in ZVS Applications • Lower Gate Charge Results in Simpler Drive Reqirements RoHS COMPLIANT • Enhanced dV/dt Capabilities Offer Improved Ruggedness • Higher Gate Voltage Threshold Offers Improved Noise Immunity • Lead (Pb)-free TO-220 FULLPAK APPLICATIONS G • Zero Voltage Switching SMPS • Telecom and Server Power Supplies GDS S N-Channel MOSFET • Uninterruptible Power Supplies • Motor Control Applications ORDERING INFORMATION Package Lead (Pb)-free TO-220 FULLPAK IRFIB5N50LPbF SiHFIB5N50L-E3 ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL VDS VGS ID IDM EAS IAR EAR PD dV/dt TJ, Tstg LIMIT 500 ± 30 4.7 3.0 16 0.33 140 4.0 3.0 42 13 - 55 to + 150 300d 10 1.1 UNIT V A W/°C mJ A mJ W V/ns °C lbf · in N·m TC = 25 °C for 10 s 6-32 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 18 mH, RG = 25 Ω, IAS = 4.0 A, dV/dt = 13 V/ns, (see fig. 12). c. ISD ≤ 4.0 A, dI/dt ≤ 280 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. Document Number: 91173 S-Pending-Rev. A, 24-Jun-08 WORK-IN-PROGRESS www.vishay.com 1 IRFIB5N50L, SiHFIB5N50L Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient Maximum Junction-to-Case (Drain) SYMBOL RthJA RthJC TYP. MAX. 65 3.0 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance Effective Output Capacitance (Energy Related) Total Gate Charge Gate-Source Charge Gate-Drain Charge Internal Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time IS ISM VSD trr MOSFET symbol showing the integral reverse p - n junction diode D SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS ΔVDS/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Coss Coss eff. Coss eff. (ER) Qg Qgs Qgd RG td(on) tr td(off) tf VGS = 0 V, ID = 250 µA Reference to 25 °C, ID = 1 mA VDS = VGS, ID = 250 µA VGS = ± 30 V VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 125 °C VGS = 10 V ID = 2.4 Ab 500 3.0 2.8 0.43 0.67 - 5.0 ± 100 50 2.0 0.80 - V V/°C V nA µA mA Ω S VDS = 50 V, ID = 2.4 A VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VDS = 1.0 V, f = 1.0 MHz VDS = 400 V, f = 1.0 MHz VGS = 0 V VDS = 0 V to 400 Vc - 1000 110 12 1360 31 75 55 2.0 13 17 26 10 45 13 23 ns Ω nC pF VGS = 10 V ID = 4.0 A, VDS = 400 V, see fig. 7 and 16b - f = 1 MHz, open drain VDD = 250 V, ID = 4.0 A, RG = 9.0 Ω, VGS = 10 V, see fig. 11a and 11bb - - 73 99 200 360 4.7 A 16 1.5 110 150 310 540 V ns G S TJ = 25 °C, IS = 4.0 A, VGS = 0 Vb TJ = 25 °C, IF = 4.0 A, TJ = 125 °C, dI/dt = 100 A/µsb TJ = 25 °C, IS = 4.0 A, TJ = 125 °C, dI/dt = 100 A/µsb Body Diode Reverse Recovery Charge Qrr nC www.vishay.com 2 Document Number: 91173 S-Pending-Rev. A, 24-Jun-08 IRFIB5N50L, SiHFIB5N50L Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER Drain-Source Body Diode Characteristics Body Diode Reverse Recovery Current Forward Turn-On Time IRRM ton TJ = 25 °C 6.7 10 A SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS. Coss eff. (ER) is a fixed capacitance that stores the same energy as Coss while VDS is rising from 0 to 80 % VDS. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 100 100 TOP VGS 15V 12V 10V 8.0V 7.0V 6.5V 6.0V 5.5V ID, Drain-to-Source Current (A) 10 10 TJ = 150 °C 1 BOTTOM I D, Drain-to-Source Current (A) 1 TJ = 25 ° C 0.1 5.5V 0.01 0.1 20µs PULSE WIDTH Tj = 25°C 0.001 0.1 1 10 100 0.01 5.0 6.0 7.0 V DS 50V = 20µs PULSE W IDTH 8.0 9.0 VDS, Drain-to-Source Voltage (V) V GS Gate-to-Source Voltage (V) , Fig. 1 - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics 100 TOP VGS 15V 12V 10V 8.0V 7.0V 6.5V 6.0V 5.5V 3.0 I D = 4.0A ID, Drain-to-Source Current (A) 2.5 RDS(on) , Drain-to-Source On Resistance 10 BOTTOM 2.0 1 5.5V (Normalized) 1.5 1.0 0.1 20µs PULSE WIDTH Tj = 150°C 0.01 0.1 1 10 100 0.5 V GS = 10V 0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 VDS, Drain-to-Source Voltage (V) ° Tj, Junction Temperature (°C) Fig. 2 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91173 S-Pending-Rev. A, 24-Jun-08 www.vishay.com 3 IRFIB5N50L, SiHFIB5N50L Vishay Siliconix 100000 12 10000 VGS = 0V, f = 1 MHZ Ciss = C + Cgd, C SHORTED gs ds Crss = C gd Coss = C + C ds gd VGS , Gate-to-Source Voltage (V) I D = 4.0A 10 VDS = 400V VDS = 250V VDS = 100V C, Capacitance(pF) 8 1000 Ciss Coss Crss 6 100 4 10 2 1 1 10 100 1000 0 0 5 10 15 20 25 30 35 VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 10 9 8 I SD , Reverse Drain Current (A) 100 7 10 Energy (µJ) 6 5 4 3 2 1 0 0 100 200 300 400 500 600 T J= 25 ° C TJ = 150 ° C 1 V GS = 0 V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 V SD Source-to-Drain Voltage (V) , VDS, Drain-to-Source Voltage (V) Fig. 6 - Typical Output Capacitance Stored Energy vs. VDS Fig. 8 - Typical Source-Drain Diode Forward Voltage www.vishay.com 4 Document Number: 91173 S-Pending-Rev. A, 24-Jun-08 IRFIB5N50L, SiHFIB5N50L Vishay Siliconix 100 OPERATION IN THIS AREA LIMITED BY R DS(on) 10 RG VDS VGS RD ID, Drain-to-Source Current (A) D.U.T. + - VDD 100µsec 1 Tc = 25°C Tj = 150°C Single Pulse 0.1 1 10 100 1msec 10msec 1000 10000 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 11a - Switching Time Test Circuit VDS 90 % VDS, Drain-to-Source Voltage (V) Fig. 9 - Maximum Safe Operating Area 5.0 10 % VGS t d(on) tr t d(off) t f 4.0 Fig. 11b - Switching Time Waveforms ID , Drain Current (A) 3.0 2.0 1.0 0.0 25 50 75 100 125 150 TC , Case Temperature ( °C) Fig. 10 - Maximum Drain Current vs. Case Temperature 10 (Z thJC ) D = 0.50 1 0.20 Thermal Response 0.10 0.05 P DM 0.1 0.02 0.01 t1 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = 2. Peak T 0.01 0.00001 0.0001 0.001 0.01 0.1 t1 / t 2 +TC 1 10 t2 J = P DM x Z thJC t 1, Rectangular Pulse Duration (sec) Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 91173 S-Pending-Rev. A, 24-Jun-08 www.vishay.com 5 IRFIB5N50L, SiHFIB5N50L Vishay Siliconix 6.0 V DS tp VGS(th) Gate threshold Voltage (V) 5.0 ID = 250µA 4.0 I AS 3.0 Fig. 15b - Unclamped Inductive Waveforms 2.0 -75 -50 -25 0 25 50 75 100 125 150 10 V QG QGS VG Q GD T J , Temperature ( °C ) Fig. 13 - Threshold Voltage vs. Temperature 320 ID TOP BOTTOM 1.8A 2.5A 4.0A EAS , Single Pulse Avalanche Energy (mJ) 240 Charge Fig. 16a - Basic Gate Charge Waveform 160 Current regulator Same type as D.U.T. 50 kΩ 80 12 V 0.2 µF 0.3 µF D.U.T. 0 25 50 75 100 125 150 + V - DS Starting Tj, Junction Temperature ( ° C) VGS 3 mA Fig. 14 - Maximum Avalanche Energy vs. Drain Current IG ID Current sampling resistors 15 V Fig. 16b - Gate Charge Test Circuit VDS L Driver RG 20 V tp D.U.T IAS 0.01 Ω + A - VDD A Fig. 15a - Unclamped Inductive Test Circuit www.vishay.com 6 Document Number: 91173 S-Pending-Rev. A, 24-Jun-08 IRFIB5N50L, SiHFIB5N50L Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test + VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Inductor current Body diode forward drop Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 17 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91173. Document Number: 91173 S-Pending-Rev. A, 24-Jun-08 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1