SIHFPS37N50A

IRFPS37N50A, SiHFPS37N50A Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) (Max.) (Ω) Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 180 46 71 Single D FEATURES 500 0.13 • Low Gate Charge Qg Results in Simple Drive Requirement • Improved Gate, Avalanche and Dynamic dV/dt Ruggedness Available RoHS* COMPLIANT • Fully Characterized Capacitance and Avalanche Voltage and Current • Effective Coss Specified • Lead (Pb)-free Available SUPER-247TM APPLICATIONS G S D G S N-Channel MOSFET • Switch Mode Power Supply (SMPS) • Uninterruptible Power Supply • High Speed Power Switching TYPICAL SMPS TOPOLOGIES • Full Bridge Converters • Power Factor Correction Boost ORDERING INFORMATION Package Lead (Pb)-free SnPb SUPER-247TM IRFPS37N50APbF SiHFPS37N50A-E3 IRFPS37N50A SiHFPS37N50A ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 1.94 mH, RG = 25 Ω, IAS = 36 A (see fig. 12). c. ISD ≤ 36 A, dI/dt ≤ 145 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91258 S-81368-Rev. B, 21-Jul-08 www.vishay.com 1 TC = 25 °C EAS IAR EAR PD dV/dt TJ, Tstg VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL VDS VGS ID IDM LIMIT 500 ± 30 36 23 144 3.6 1260 36 44 446 3.5 - 55 to + 150 300d W/°C mJ A mJ W V/ns °C A UNIT V IRFPS37N50A, SiHFPS37N50A Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain) SYMBOL RthJA RthCS RthJC TYP. 0.24 MAX. 40 0.28 °C/W UNIT SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER Static Drain-Source Breakdown Voltage Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode D SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Coss Coss eff. Qg Qgs Qgd td(on) tr td(off) tf VGS = 0 V, ID = 250 µA VDS = VGS, ID = 250 µA VGS = ± 30 V VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 150 °C VGS = 10 V ID = 2 2 A b Ab VDS = 50 V, ID = 22 500 2.0 20 - 4.0 ± 100 25 250 0.13 - V V nA µA Ω S VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VDS = 1.0 V , f = 1.0 MHz VGS = 0 V VDS = 400 V , f = 1.0 MHz VDS = 0 V to 400 V VGS = 10 V ID = 36 A, VDS = 400 V, see fig. 6 and 13b - 5579 810 36 7905 221 400 23 98 52 80 180 46 71 ns nC pF VDD = 250 V, ID = 36 A, RG = 2.15 Ω, RD = 7.0 Ω, see fig. 10b - - 570 8.6 36 A 144 1.5 860 13 V ns µC G S TJ = 25 °C, IS = 36 A, VGS = 0 Vb TJ = 25 °C, IF = 36 A, dI/dt = 100 A/µsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS. www.vishay.com 2 Document Number: 91258 S-81368-Rev. B, 21-Jul-08 IRFPS37N50A, SiHFPS37N50A Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 1000 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 1000 I D , Drain-to-Source Current (A) 100 I D , Drain-to-Source Current (A) 100 TJ = 150 ° C 10 TJ = 25 ° C 10 1 4.5V 0.1 0.1 20µs PULSE WIDTH TJ = 25 °C 1 10 100 1 4.0 V DS = 50V 20µs PULSE W IDTH 5.0 6.0 7.0 8.0 9.0 VDS , Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics VGS , Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics 100 TOP RDS(on) , Drain-to-Source On Resistance (Normalized) I D , Drain-to-Source Current (A) VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 3.0 ID = 36A 2.5 2.0 10 1.5 4.5V 1.0 0.5 1 0.1 20µs PULSE WIDTH TJ = 150 ° C 1 10 100 0.0 -60 -40 -20 VGS = 10V 0 20 40 60 80 100 120 140 160 VDS , Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics TJ , Junction Temperature ( °C) Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91258 S-81368-Rev. B, 21-Jul-08 www.vishay.com 3 IRFPS37N50A, SiHFPS37N50A Vishay Siliconix 100000 C, Capacitance (pF) 10000 C iss ISD , Reverse Drain Current (A) V GS = 0V, f = 1MHz C iss = C gs + C gd, C dsSHORTED C rss = C gd C oss = C ds + C gd 1000 100 TJ = 150 ° C 10 1000 C oss TJ = 25 ° C 1 100 Crss 10 1 10 100 1000 A 0.1 0.2 V GS = 0 V 0.4 0.6 0.8 1.0 1.2 1.4 VDS , D rain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage VSD ,Source-to-Drain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage 20 ID = 36A VDS = 400V VDS = 250V VDS = 100V 1000 VGS , Gate-to-Source Voltage (V) OPERATION IN THIS AREA LIMITED BY RDS(on) 16 ID , Drain Current (A) 100 10us 12 100us 8 10 1ms 4 0 0 40 80 FOR TEST CIRCUIT SEE FIGURE 13 120 160 200 1 TC = 25 ° C TJ = 150 ° C Single Pulse 10 100 10ms 1000 10000 QG , Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage VDS , Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area www.vishay.com 4 Document Number: 91258 S-81368-Rev. B, 21-Jul-08 IRFPS37N50A, SiHFPS37N50A Vishay Siliconix 40 VGS RG VDS RD D.U.T. + - VDD ID , Drain Current (A) 30 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 20 Fig. 10a - Switching Time Test Circuit VDS 10 90 % 0 25 50 75 100 125 150 TC , Case Temperature ( ° C) Fig. 9 - Maximum Drain Current vs. Case Temperature 10 % VGS td(on) tr td(off) tf Fig. 10b - Switching Time Waveforms 1 Thermal Response (Z thJC ) D = 0.50 0.1 0.20 0.10 0.05 0.02 0.01 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 0.01 0.001 0.00001 t1 , Rectangular Pulse Duration (sec) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case VDS 15 V tp VDS L Driver RG 20 V tp D.U.T. IAS 0.01 Ω + A - VDD IAS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms Document Number: 91258 S-81368-Rev. B, 21-Jul-08 www.vishay.com 5 IRFPS37N50A, SiHFPS37N50A Vishay Siliconix 580 EAS , Single Pulse Avalanche Energy (mJ) 3000 2500 BOTTOM V DSav , Av alanche Voltage (V) TOP ID 16A 23A 36A 560 2000 1500 540 1000 520 500 0 25 50 75 100 125 150 500 0 10 20 30 40 A Starting TJ , Junction Temperature ( °C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current I av , Av alanche Current (A) Fig. 12d - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ 12 V 10 V QGS QG 0.2 µF 0.3 µF QGD D.U.T. + - VDS VG VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit www.vishay.com 6 Document Number: 91258 S-81368-Rev. B, 21-Jul-08 IRFPS37N50A, SiHFPS37N50A Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test + VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Inductor current Body diode forward drop Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91258. Document Number: 91258 S-81368-Rev. B, 21-Jul-08 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. 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