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SIHFPS40N50L

SIHFPS40N50L

  • 厂商:

    VISHAY

  • 封装:

  • 描述:

    SIHFPS40N50L - Power MOSFET - Vishay Siliconix

  • 数据手册
  • 价格&库存
SIHFPS40N50L 数据手册
IRFPS40N50L, SiHFPS40N50L Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) (Ω) Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 380 80 190 Single D FEATURES 500 0.087 • Superfast Body Diode Eliminates the Need for External Diodes in ZVS Applications • Lower Gate Charge Results in Simpler Drive Requirements Available RoHS* COMPLIANT • Enhanced dV/dt Capabilities Offer Improved Ruggedness • Higher Gate Voltage Threshold Offers Improved Noise Immunity • Lead (Pb)-free Available SUPER-247TM APPLICATIONS G S D G S N-Channel MOSFET • Zero Voltage Switching SMPS • Telecom and Server Power Supplies • Uninterruptible Power Supplies • Motor Control Applications ORDERING INFORMATION Package Lead (Pb)-free SnPb SUPER-247TM IRFPS40N50LPbF SiHFPS40N50L-E3 IRFPS40N50L SiHFPS40N50L ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL VDS VGS ID IDM EAS IAR EAR TC = 25 °C PD dV/dt TJ, Tstg for 10 s LIMIT 500 ± 30 46 29 180 4.3 920 46 54 540 34 - 55 to + 150 300d W/°C mJ A mJ W V/ns °C A UNIT V Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 0.86 mH, RG = 25 Ω, IAS = 46 A (see fig. 12). c. ISD ≤ 46 A, dI/dt ≤ 550 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91260 S-81367-Rev. B, 21-Jul-08 www.vishay.com 1 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambienta Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain)a Note a. Rth is measured at TJ approximately 90 °C. SYMBOL RthJA RthCS RthJC TYP. 0.24 MAX. 40 0.23 °C/W UNIT SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance Effective Output Capacitance (Energy Related) Total Gate Charge Gate-Source Charge Gate-Drain Charge Internal Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Reverse Recovery Current IS ISM VSD trr Qrr IRRM MOSFET symbol showing the integral reverse p - n junction diode D SYMBOL VDS ΔVDS/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Coss Coss eff. Coss eff. (ER) Qg Qgs Qgd RG td(on) tr td(off) tf TEST CONDITIONS VGS = 0 V, ID = 250 µA Reference to 25 °C, ID = 1 mA VDS = VGS, ID = 250 µA VGS = ± 30 V VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 125 °C VGS = 10 V ID = 2 8 Ab VDS = 50 V, ID = 46 A MIN. 500 3.0 21 - TYP. 0.60 0.087 8110 960 130 11200 240 440 310 0.90 27 170 50 69 MAX. 5.0 ± 100 50 2.0 0.100 380 80 190 - UNIT V V/°C V nA µA mA Ω S VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VDS = 1.0 V , f = 1.0 MHz VDS = 400 V , f = 1.0 MHz VGS = 0 V VDS = 0 V to 400 Vc pF - VGS = 10 V ID = 46 A, VDS = 400 V, see fig. 7 and 15b - nC Ω f = 1 MHz, open drain VDD = 250 V, ID = 46 A, RG = 0.85 Ω, VGS = 10 V, see fig. 14a and 14bb ns - 170 220 705 1.3 9.0 46 A 180 1.5 250 330 1060 2.0 V ns nC A G S TJ = 25 °C, IS = 46 A, VGS = 0 Vb TJ = 25 °C, IF = 46 A TJ = 125 °C, dI/dt = 100 A/µsb TJ = 25 °C, IS = 46 A, VGS = 0 Vb TJ = 125 °C, dI/dt = 100 TJ = 25 °C A/µsb Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 400 µs; duty cycle ≤ 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS. Coss eff. (ER) is a fixed capacitance that stores the same energy as Coss while VDS is rising from 0 to 80 % VDS. www.vishay.com 2 Document Number: 91260 S-81367-Rev. B, 21-Jul-08 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 1000 I D , Drain-to-Source Current (A) 100 I D , Drain-to-Source Current (A) VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 1000 100 TJ = 150° C 10 10 1 TJ = 25 ° C 1 4.5V 0.1 0.01 0.1 20μs PULSE WIDTH TJ = 25 °C 1 10 100 0.1 V DS= 50V 20µs PULSE WIDTH 4 5 6 7 8 9 10 11 VDS , Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics VGS , Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics TOP RDS(on) , Drain-to-Source On Resistance (Normalized) 1000 I D , Drain-to-Source Current (A) 100 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V 3.0 ID = 47A 2.5 2.0 10 4.5V 1.5 1.0 1 0.5 0.1 0.1 20µs PULSE W IDTH TJ = 150 °C 1 10 100 0.0 -60 -40 -20 VGS = 10V 0 20 40 60 80 100 120 140 160 VDS , Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics TJ , Junction Temperature ( ° C) Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91260 S-81367-Rev. B, 21-Jul-08 www.vishay.com 3 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix 20 1000000 VGS , Gate-to-Source Voltage (V) 100000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd ID = 47A V DS= 400V V DS= 250V V DS= 100V C, Capacitance(pF) 15 10000 Ciss 10 1000 Coss 100 Crss 5 10 1 10 100 1000 0 0 100 200 300 400 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage QG , Total Gate Charge (nC) Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 40 35 30 1000 ISD , Reverse Drain Current (A) 100 Energy (µJ) 25 20 15 10 5 0 0 100 200 300 400 500 600 TJ = 150° C 10 TJ = 25 ° C 1 0.1 0.2 V GS = 0 V 0.7 1.2 1.7 2.2 VDS, Drain-to-Source Voltage (V) Fig. 6 - Typical Output Capacitance Stored Energy vs. VDS VSD ,Source-to-Drain Voltage (V) Fig. 8 - Typical Source Drain Diode Forward Voltage www.vishay.com 4 Document Number: 91260 S-81367-Rev. B, 21-Jul-08 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix 50 VGS VDS RD D.U.T. + - VDD 40 RG ID , Drain Current (A) 10 V 30 Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit 20 VDS 90 % 10 0 25 50 75 100 125 150 TC , Case Temperature ( °C) Fig. 9 - Maximum Drain Current vs. Case Temperature 1 10 % VGS td(on) tr td(off) tf Fig. 10b - Switching Time Waveforms Thermal Response (Z thJC ) 0.1 D = 0.50 0.20 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 0.01 0.001 0.00001 t1 , Rectangular Pulse Duration (sec) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case 15 V VDS tp VDS L Driver RG 20 V tp D.U.T. IAS 0.01 Ω + A - VDD IAS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms Document Number: 91260 S-81367-Rev. B, 21-Jul-08 www.vishay.com 5 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix 1000 OPERATION IN THIS AREA LIMITED BY RDS(on) Current regulator Same type as D.U.T. 50 kΩ 12 V ID , Drain Current (A) 100 10us 0.2 µF 0.3 µF 100us D.U.T. + - VDS 10 1ms VGS 3 mA 1 TC = 25 °C TJ = 150 °C Single Pulse 10 100 10ms IG ID Current sampling resistors 100 VDS , Drain-to-Source Voltage (V) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Fig. 13a - Gate Charge Test Circuit EAS , Single Pulse Avalanche Energy (mJ) 2000 TOP BOTTOM ID 21A 30A 46A QG 1500 VGS QGS 1000 QGD VG 500 Charge 0 25 50 75 100 125 150 Fig. 12d - Maximum Safe Operating Area Starting T , Junction Tem perature( °C) J Fig. 13b - Basic Gate Charge Waveform www.vishay.com 6 Document Number: 91260 S-81367-Rev. B, 21-Jul-08 IRFPS40N50L, SiHFPS40N50L Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test + VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Inductor current Body diode forward drop Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91260. Document Number: 91260 S-81367-Rev. B, 21-Jul-08 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1
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