SIHLZ24S

IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) () Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 5 V 18 4.5 12 Single D FEATURES 60 0.10 • Halogen-free According to IEC 61249-2-21 Definition • Surface Mount • Available in Tape and Reel • Dynamic dV/dt Rating • Logic-Level Gate Drive • RDS (on) Specified at VGS = 4 V and 5 V • 175°C Operating Temperature • Fast Switching • Compliant to RoHS Directive 2002/95/EC Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D2PAK is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. The through-hole version (IRLZ24L, SiHLZ24L) is available for low-profile application. I2PAK (TO-262) SiHLZ24L-GE3 IRLZ24LPbF SiHLZ24L-E3 I2PAK (TO-262) D2PAK (TO-263) DESCRIPTION G G D S D S G S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free and Halogen-free Lead (Pb)-free D2PAK (TO-263) SiHLZ24S-GE3 - ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Linear Derating Factor (PCB Mount)e Single Pulse Avalanche Energyb Maximum Power Dissipation Maximum Power Dissipation (PCB Mount)e Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) VGS at 5 V TC = 25 °C TC = 100 °C SYMBOL VDS VGS ID IDM LIMIT 60 ± 10 17 12 68 0.40 0.025 110 60 3.7 4.5 - 55 to + 175 300d UNIT V A W/°C mJ W V/ns °C EAS TC = 25 °C TA = 25 °C PD dV/dt TJ, Tstg for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 444 μH, Rg = 25 , IAS = 17 A (see fig. 12). c. ISD  17 A, dI/dt  140 A/μs, VDD  VDS, TJ  175 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material) * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 90416 S11-1044-Rev. C, 30-May-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. 62 40 2.5 °C/W UNIT Maximum Junction-to-Ambient RthJA Maximum Junction-to-Ambient RthJA (PCB Mount)a Maximum Junction-to-Case (Drain) RthJC Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current VDS VDS/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf VDD = 30 V, ID = 17 A, Rg = 9 , RD = 1.7 , see fig. 10b VGS = 5 V ID = 17 A, VDS = 48 V, see fig. 6 and 13b VGS = 0, ID = 250 μA Reference to 25 °C, ID = 1 mA VDS = VGS, ID = 250 μA VGS = ± 10 V VDS = 60 V, VGS = 0 V VDS = 48 V, VGS = 0 V, TJ = 150 °C VGS = 5 V VGS = 4 V ID = 10 Ab ID = 8.5 Ab 60 1.0 7.3 0.060 2.0 ± 100 25 250 0.10 0.14 V V/°C V nA μA SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Dynamic Internal Drain Inductance Internal Source Inductance Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time  S VDS = 25 V, ID = 10 Ab VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 870 360 53 11 110 23 41 18 4.5 12 ns nC pF LD LS Between lead, 6 mm (0.25") from package and center of die contact D - 4.5 7.5 nH - G S IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode D - 110 0.49 17 A 68 1.5 260 1.5 V ns μC G S TJ = 25 °C, IS = 17 A, VGS = 0 Vb TJ = 25 °C, IF = 17 A, dI/dt = 100 A/μsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; duty cycle  2 %. www.vishay.com 2 Document Number: 90416 S11-1044-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 3 - Typical Transfer Characteristics Fig. 2 - Typical Output Characteristics, TC = 175 °C Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 90416 S11-1044-Rev. C, 30-May-11 www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area www.vishay.com 4 Document Number: 90416 S11-1044-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix VDS VGS Rg RD D.U.T. + - VDD 5V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % Fig. 9 - Maximum Drain Current vs. Case Temperature 10 % VGS td(on) tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 90416 S11-1044-Rev. C, 30-May-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix L Vary tp to obtain required IAS Rg VDS tp VDD D.U.T I AS 5V tp 0.01 W IAS + V DD VDS VDS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ 12 V 0.2 µF 0.3 µF 5V QGS QG QGD D.U.T. + - VDS VG VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit www.vishay.com 6 Document Number: 90416 S11-1044-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer D.U.T. + - - + Rg • • • • dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Inductor current Body diode forward drop Ripple ≤ 5 % Note a. VGS = 5 V for logic level devices ISD Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?90416. Document Number: 90416 S11-1044-Rev. C, 30-May-11 www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-252AA (HIGH VOLTAGE) E b3 E1 L3 D1 D L4 H b2 A c2 b e A1 L c θ L2 L1 MILLIMETERS DIM. E L L1 L2 L3 L4 D H b b2 b3 e A A1 c c2 D1 E1 θ ECN: S-81965-Rev. A, 15-Sep-08 DWG: 5973 2.20 0.00 0.45 0.45 5.30 4.40 0' 0.89 0.64 6.00 9.40 0.64 0.77 5.21 2.286 BSC 2.38 0.13 0.60 0.58 10' 0.087 0.000 0.018 0.018 0.209 0.173 0' MIN. 6.40 1.40 2.743 REF 0.508 BSC 1.27 1.01 6.22 10.40 0.88 1.14 5.46 0.035 0.025 0.236 0.370 0.025 0.030 0.205 MAX. 6.73 1.77 MIN. 0.252 0.055 INCHES MAX. 0.265 0.070 0.108 REF 0.020 BSC 0.050 0.040 0.245 0.409 0.035 0.045 0.215 0.090 BSC 0.094 0.005 0.024 0.023 10' Notes 1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. The package top may be smaller than the package bottom. 4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. Document Number: 91344 Revision: 15-Sep-08 www.vishay.com 1 Package Information Vishay Siliconix TO-251AA (HIGH VOLTAGE) 4 E1 Thermal PAD E b4 θ2 D1 4 3 4 A A 0.010 0.25 M C A B L2 4 B D 3 5 (Datum A) L1 L3 C C c2 A θ1 C Seating plane L B B A 3 x b2 View A - A 2xe 3xb 0.010 0.25 M C A B Base metal A1 c Plating Lead tip (c) 5 b1, b3 c1 5 (b, b2) Section B - B and C - C MILLIMETERS DIM. A A1 b b1 b2 b3 b4 c c1 c2 D MIN. 2.18 0.89 0.64 0.65 0.76 0.76 4.95 0.46 0.41 0.46 5.97 MAX. 2.39 1.14 0.89 0.79 1.14 1.04 5.46 0.61 0.56 0.86 6.22 MIN. INCHES MAX. 0.094 0.045 0.035 0.031 0.045 0.041 0.215 0.024 0.022 0.034 0.245 DIM. D1 E E1 e L L1 L2 L3 θ1 θ2 MILLIMETERS MIN. 5.21 6.35 4.32 2.29 BSC 8.89 1.91 0.89 1.14 0' 25' 9.65 2.29 1.27 1.52 15' 35' MAX. 6.73 MIN. INCHES MAX. 0.265 - 0.086 0.035 0.025 0.026 0.030 0.030 0.195 0.018 0.016 0.018 0.235 0.205 0.250 0.170 2.29 BSC 0.350 0.075 0.035 0.045 0' 25' 0.380 0.090 0.050 0.060 15' 35' ECN: S-82111-Rev. A, 15-Sep-08 DWG: 5968 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension are shown in inches and millimeters. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 4. Thermal pad contour optional with dimensions b4, L2, E1 and D1. 5. Lead dimension uncontrolled in L3. 6. Dimension b1, b3 and c1 apply to base metal only. 7. Outline conforms to JEDEC outline TO-251AA. Document Number: 91362 Revision: 15-Sep-08 www.vishay.com 1 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1