SIP11205

SiP11205 Vishay Siliconix Feed-Forward Controller with Primary MOSFET Drivers for Intermediate Bus Converters DESCRIPTION SiP11205 is a feed-forward controller for the primary side of a half-bridge intermediate bus converter (IBC). It is ideally suited for isolated applications such as telecom, data communications and other products requiring an IBC architecture and conversion of standard bus voltages such as 48 V to a lower intermediate voltage, where high efficiency is required at low output voltages (24 V, 12 V, 9 V or 5 V). Designed to operate within the telecom voltage range of 36 V to 75 V and withstand 100 V transients for a period of 100 ms, the IC is designed for controlling and driving both the low- and high-side switching devices of a half-bridge converter. The feed-forward feature is designed to make the converter output semi-regulated and is beneficial for point-of-load applications that require narrow input range. SiP11205 has advanced current monitoring and control circuitry, which allows the user to set the maximum current in the primary circuit. This feature acts as protection against overcurrent and output short circuit. Current sensing is by means of a sense resistor connected in series with the primary low-side MOSFET. FEATURES • 36 V to 75 V input voltage range • Withstand 100 V, 100 ms transient capability • Integrated ± 1.6 A typical high- and low-side MOSFET drivers • Oscillator frequency is programmable from 200 kHz to 1 MHz (100 kHz to 500 kHz switching frequency) and can be externally synchronized • Voltage feed-forward compensation • High voltage pre-regulator operates during start-up • Current sensing on primary low-side switch • Hiccup mode • System low input voltage detection • Chip UVLO function • Programmable soft-start function • Over temperature protection (160 °C) • Greater than 95.5 % efficiency for 42 V to 55 V input range • Better than 2 % line regulation at 9 A APPLICATIONS • • • • • Intermediate bus architectures Telecom and Datacom Routers and servers Storage area network Base station • 1/8 and 1/4 bricks TYPICAL APPLICATION CIRCUIT Vin+ 42 V to 55 V 100 V/100 ms VinSi2303BDS 1 2 3 4 5 6 7 8 VINDET VIN VCC COMP CS AGND VREF ROSC SiP11205 BST DH LX DL PGND SS RDB COSC 16 15 13 12 11 10 Si7456DP 14 Vo+ Si7848DP Vo- Si7456DP 9 Document Number: 69233 S-81795-Rev. C, 04-Aug-08 RDB1 Si2303BDS Si7848DP RDB2 www.vishay.com 1 SiP11205 Vishay Siliconix TECHNICAL DESCRIPTION SiP11205 is a feed-forward controller on the primary side of a half-bridge intermediate bus converter. With 100 V depletion mode MOSFET in the chip, the SiP11205 is capable of being powered directly from the high voltage bus to VCC through an external PNP pass transistor, or may be powered by an external supply directly to the VCC pin. Without the use of an external pass transistor, failure of the converter output to power VCC above the VREG level will result in over temperature protection activating hiccup operation whenever the pre-regulator power dissipation becomes excessive. The external high- and low-side N-Channel power MOSFETs are driven by a built-in driver with ± 1.6 A peak current capability. SiP11205 is available in the MLP44-16 PowerPAK® package and TSSOP-16 PowerPAK® package and is specified over the ambient temperature range of - 40 °C to 85 °C. SIP11205 BLOCK DIAGRAM VIN VREG COMP Pre Reg VCC UVLO + VSD Level Shift BST DH VINDET VREF BG AGND SS 1.2 V+ V INDET /2 IDSS + - VUV VCC ISS + VUV Hi-side driver Driver EN LX 0.85 VSS + 250 mV SS Comp + D MAX EN OTP Control DL Le Low-side driver CS Over Current protection EN + PWM Comp Ramp OSC EN PGND I DSS 0.13 V Le EN VREF EN IBIAS I SS I BIAS VINDET /2 0.200 V VREF R OSC R DB C OSC www.vishay.com 2 Document Number: 69233 S-81795-Rev. C, 04-Aug-08 SiP11205 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS all voltages referenced to GND = 0 V Parameter VIN, VLX VCC VBST VBST - VLX Logic Inputs Linear Inputs HV Pre-Regulator Input Current (continuous) Storage Temperature Maximum Junction Temperature Power Dissipation Thermal Impedance (ΘJA) PowerPAK MLP44-16a, b PowerPAK TSSOP-16 a, c Limit Continuous 100 ms Continuous 100 ms 80 100 14.5 95 112 15 - 0.3 to VCC + 0.3 - 0.3 to VCC + 0.3 10 - 65 to 150 150 2564 2630 39 38 Unit V mA °C mW °C/W PowerPAK MLP44-16a, b PowerPAK TSSOP-16a, c Notes: a. Device Mounted with all leads soldered or welded to PC board. b. Derate 25.6 mW/°C above 25 °C. c. Derate 26.3 mW/°C above 25 °C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE all voltages referenced to GND = 0 V Parameter VIN VBST VBST - VLX VCC Logic Inputs Linear Inputs FOSC ROSC COSC CSS CCOMP VREF Capacitor to GND CBOOST VCC Capacitor to GND Continuous 100 ms Limit 36 to 75 100 VIN + 10.5 to VIN + 13.2 10.5 to 13.2 10.5 to 13.2 - 0.3 to VCC + 0.3 - 0.3 to VCC + 0.3 200 to 1000 40 to 200 100 to 220 10 to 100 2.2 1 0.1 4.7 µF kHz kΩ pF nF V Unit Document Number: 69233 S-81795-Rev. C, 04-Aug-08 www.vishay.com 3 SiP11205 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Otherwise Specified TA = - 40 °C to + 85 °C, FOSC = 800 kHz, 10.5 V ≤ VCC ≤ 13.2 V, VINDET = 4.8 V, VIN = 48 V, RDB1 = 47.5 kΩ, RDB2 = 28.7 kΩ, ROSC = 47.5 kΩ, COSC = 100 pF Limits Parameter Pre-Regulator VIN Range Pre-Reg Current (cut-off) Pre-Reg Current (standby) Pre-Reg Current (switching) Pre-Reg Output Voltage Pre-Reg Drive Current Pre-Reg Load Regulation Pre-Reg Line Regulation Regulator Compensation VCC Supply Voltage VCC Range Shut Down Current Quiescent Current Supply Current UVLO OFF-Threshold Hysteresis VCC Clamp Voltage Current Sense Current Limit Threshold 1 (MOC)a Current Limit Threshold 2 CS to DL Delay Leading Edge Blanking Period Pulse Width Modulator Maximum Duty Cyclec Maximum Duty Cycle Asymmetry RDB Voltage Oscillator Oscillator Frequencyd Oscillator Bias Voltage Soft Start Soft Start Charging Current SS Ramp Completion Voltage MOC Discharge Current SOC Discharge Current Reset Voltage Reference Output Voltage Short Circuit Current Load Regulation (SOC)b Symbol VIN IVINLKG IVINSD IVIN VREG ISTART LDR LNR ISRC ISNK VCC ISD IQ ICC UVLOH HUVLO VCLAMP VMOC VSOC TD TBL DMAX VRDB FOSC VROSC ISS VSS IDSS1 IDSS2 VSSL VREF IREFSC ΔVR/ΔIR Min. 36 Typ. 48 90 Max. 75 10 200 9 10.4 Unit V µA mA V mA mV %/V VIN = 75 V, VCC > 10.5 V VIN = 75 V, VINDET = 0 V VIN = 75 V, VINDET = 7.5 V VCC Voltage with VIN = 48 V VCC < VREG ILOAD: 0 to 20 mA - 35 40 10.5 VINDET = 0 V VINDET < VREF VINDET > VREF VCC rising Force 20 mA into VCC ISS = 20 µA ISS = 400 nA DL(ON) blanking time VIN = 42 V, VINDET = 4.2 V VIN = 42 V, VINDET = 4.2 V 680 50 3.0 5.0 7.6 14 105 165 3.6 7.8 20 100 0.05 VCC = 12 V - 20 87 12 150 4 6.6 9.0 1.2 15.3 130 200 150 20 47 1 2.06 800 2.36 VSS = 0 CS = VMOC CS = VSOC CS < VMOC VCC = 12 V VREF = 0 V 0 mA ≤ ILOAD ≤ 2.5 mA 3.2 - 50 - 33 - 26 14 - 20 4.5 20 400 0.25 3.3 - 42 - 16 6.2 9.3 - 10 130 13.2 350 5.2 8.5 10 µA V µA mA V 16.2 160 235 mV ns 50 % V 920 kHz V - 14 26 µA V µA nA V 3.4 V mA mV www.vishay.com 4 Document Number: 69233 S-81795-Rev. C, 04-Aug-08 SiP11205 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Otherwise Specified TA = - 40 °C to + 85 °C, FOSC = 800 kHz, 10.5 V ≤ VCC ≤ 13.2 V, VINDET = 4.8 V, VIN = 48 V, RDB1 = 47.5 kΩ, RDB2 = 28.7 kΩ, ROSC = 47.5 kΩ, COSC = 100 pF Limits Parameter VINDET Function VINDET Pin Input Impedance Shutdown Threshold High Voltage Shutdown Hysteresis Voltage Under Voltage OFF Voltage Under Voltage Hysteresis Voltage Over Temperature Protection (OTP) Activating Temperature De-Activating Temperature Output High Voltage (differential) Output Low Voltage (differential) Peak Output Sourcing Current Peak Output Sinking Current Driver Frequency Rise Time Fall Time Boost Pin Current (switching) LX Pin Current (switching) LX Pin Leakage Current Output High Voltage (differential) Output Low Voltage (differential) Peak Output Sourcing Current Peak Output Sinking Current Driver Frequency Rise Time Fall Time Symbol RVINDET VSDH HSD VUVH HUV OTPON OTPOFF VDHH VDHL IDHH IDHL FDH tHR tHF IBST ILX ILX-LKG VDLH VDLL IDLH IDLL FDL tLR tLF Min. 30 Typ. 46 0.58 0.15 3.3 0.26 Max. 70 0.76 3.46 Unit kΩ VINDET rising, VREF on VINDET rising at ICC 0.33 3.14 V TJ rising TJ falling Sourcing 10 mA, VDH - VBST Sinking 10 mA, VDH -VLX VCC = 10.5 V, CLOAD = 3 nF 340 CLOAD = 3 nF CLOAD = 3 nF VLX = 75 V, VBST = VLX + VCC VINDET = 0 V, VLX = 40 V Sourcing 10 mA, VDL - VCC Sinking 10 mA, VDL - VAGND VCC = 10.5 V, CLOAD = 3 nF 340 CLOAD = 3 nF CLOAD = 3 nF - 0.3 1.3 - 2.1 - 0.3 160 145 °C High-Side MOSFET Driver (DH Output) 0.3 - 2.2 1.6 400 20 20 2.6 - 1.4 3.9 - 0.7 10 460 V A kHz ns mA µA Low-Side MOSFET Driver (DL Output) 0.3 - 1.6 1.6 400 20 20 460 V A kHz ns Notes: a. MOC stands for moderate overcurrent voltage at CS pin. b. SOC stands for severe overcurrent voltage at CS pin. c. The maximum duty cycle is set by the resistor ratio (RDB1/RDB2) from pin RDB to VREF at minimum VIN = 42 V. d. Not tested. Guaranteed by driver frequency test. The driver frequency is half of the oscillator frequency. Document Number: 69233 S-81795-Rev. C, 04-Aug-08 www.vishay.com 5 SiP11205 Vishay Siliconix PACKAGE AND PIN CONFIGURATION MLP44-16 PowerPAK Package VI N DET TSSOP-16 PowerPAK Package BST VI N DH VCC COMP 1 TOP VIEW LX DL PGND SS CS AGND 1 2 3 4 5 6 7 8 Top View 16 15 14 13 12 11 10 9 R OSC C OSC VREF Notes: For MLP44-16 package the bottom pin 1 indicator is connected to EPAD or AGND. TSSOP-16 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 MLP44-16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol VCC COMP CS AGND VREF ROSC COSC RDB SS PGND DL LX DH BST VINDET VIN Pre-regulator compensation pin Current sense comparator input R DB Description Pre-regulator output and supply voltage for internal circuitry Analog ground (connected to package’s exposed pad) 3.3 V reference output and bypass capacitor connection pin Oscillator resistor connection Oscillator capacitor connection and external frequency sync. connection Dead time setting resistor connection Soft start capacitor connection Power ground Primary low-side MOSFET drive signal High-side MOSFET source and transformer connection node Primary high-side MOSFET drive signal Bootstrap voltage pin for the high-side driver Shut down/under voltage/enable control pin High voltage pre-regulator input ORDERING INFORMATION Part Number SiP11205DQP-T1-E3 SiP11205DLP-T1-E3 Package TSSOP-16 MLP44-16 Marking 11205 Temperature - 40 °C to + 85 °C www.vishay.com 6 Document Number: 69233 S-81795-Rev. C, 04-Aug-08 SiP11205 Vishay Siliconix TIMING DIAGRAM AND SOFT START DUTY CYCLE CONTROL RDB COSC SS DL DH DMAX. Time HICCUP RESPONSE TO MODERATE OVERCURRENT FAULTS SS Clamp Level DMAX. Clamp Level Hiccup Trigger Level SS DL DH Hiccup Triggered CS IN OC_DET CLK Over current protection operation showing reduction in duty cycle down to the hiccup trigger point. SS continues to discharge down to 250 mV (400 nA IDISCHARGE), and then will recharge at 20 µA. Document Number: 69233 S-81795-Rev. C, 04-Aug-08 www.vishay.com 7 SiP11205 Vishay Siliconix FEED-FORWARD FUNCTION DIAGRAM VROSC = VINDET/2 = 3.75 V VCOSC high line voltage VRDB = 1.89 V VCOSC low line voltage 2 VBE D = 90 % DL/DH D = 45 % CIRCUIT FOR FREQUENCY SYNCHRONIZATION 220 pF SYNC IN 2N3904 100 COSC 1k SiP11205 DETAILED OPERATIONAL DESCRIPTION Start Up The controller supply (VCC) is linearly regulated up to its target voltage VREG by the on chip pre-regulator circuit. During power up with VINDET ramping up from GND, the VCC capacitor minimum charge current is 20 mA and the pre-regulator voltage is typically 9.3 V. As VINDET exceeds VREF, the DL/DH outputs are capable of driving 3 nF MOSFET gate capacitances and hence the pre-regulator load regulation can easily handle 120 µA to 20 mA load step with a typical load regulation of 1 %. Startup current into the external VCC capacitor is limited to typically 20 mA by the internal N-Channel DMOS in the pre-regulator unless an external power source is connected to VCC pin. This source may be a DC supply or from external VIN by connecting a PNP pass transistor between VIN and VCC. The VCC pin is protected by a 20 mA clamp when this pin exceeds 14.5 V. The clamp turns on when VCC is between 14.5 and 16 V. When VCC exceeds the UVLO voltage (UVLOH) a soft start cycle of the switch mode supply is initiated. The VCC supply continues to be charged by the pre-regulator until VCC equals VREG. During this period, between UVLOH and VREG, excessive load may result in VCC falling below UVLOH and stopping switch mode operation. This situation is avoided by the hysteresis between VREG and UVLO Off-Threshold level UVLOL. PWM Operation During startup, DL always turns on before DH and both switch on and off at half the oscillator frequency. The SS comparator compares the SS ramp with the oscillator ramp hence the duty cycle increases as VSS increases. When SS ramp reaches a voltage that equals to RDB voltage, the PWM comparator, which compares RDB voltage to the oscillator ramp, takes over and the maximum duty cycle is now set by the oscillator ramp and RDB voltage. Refer to "Timing diagram and soft start duty cycle control" graph for better understanding. After soft start completion the duty cycle is modulated by the feed-forward voltage VFF = VROSC = VINDET/2. Since the oscillator frequency is fixed, the ramp amplitude must increase to reduce the duty cycle set by RDB. Mathematically, the total duty cycle is determined by the following formula: DTOTAL = VRDB/(VINDET/2) = 2 x VREF x RDB1/(RDB1 + RDB2)/VINDET Document Number: 69233 S-81795-Rev. C, 04-Aug-08 www.vishay.com 8 SiP11205 Vishay Siliconix And the duty cycle on DL or DH will then be approximately half of DTOTAL. Please note that due to oscillator comparator overshoot the exact duty cycle calculated using above formula may be slightly different. To better understand the PWM operation during start up refer to "Timing Diagram and Soft Start Duty Cycle Control" graph, for PWM operation after start up see "Feed-Forward Function Diagram". For each specific application the RDB1/RDB2 ratio must be chosen to provide maximum duty cycle with appropriate dead time at minimum supply voltage. The voltage at RDB pin that corresponds to maximum duty cycle at minimum input voltage can be determined by applying a precise voltage source on this pin for the dead time required. The SiP11205 has a stable 3.3 V reference with 3 % temperature accuracy, so a typical 3 % duty variation and 1 % DL/DH matching can be achieved. There will be 0.75 % duty reduction for each 1 V increase in the VIN supply range. For better system efficiency it is recommended that the input voltage range be limited to 42 V to 55 V. Soft Start The soft start circuit plays an important role in protecting the controller. At startup it prevents high in-rush current. During a normal start-up sequence (VCS < VMOC. VCS is the voltage at CS pin), or following any event that would cause a hiccup-and-soft-start sequence, CSS will be charged from about 0 V to a final voltage of 2 VBE + VINDET/2 at a 20 µA rate. As the voltage on the CSS rises towards the final voltage, the maximum permitted DL and DH duty cycles will increase from 0 % to a maximum defined by the RDB resistor divider. When a mild fault condition is detected (VCS = VMOC), CSS goes into a hiccup mode until fault condition is removed. The hiccup is activated when CSS discharges to 0.85 VSS at 20 µA and subsequently at 0.4 µA until the fault condition is removed. Refer to "Fault Conditions and Responses" for details. Fault Conditions and Responses The faults that can cause a hiccup-and-retry cycle are moderate over-current (MOC), severe over-current (SOC), chip level UVLO, system level UVLO, and over temperature protection (OTP). Prior to detailing the various fault conditions and responses, some definitions are given: 1. A complete switching period, T, consists of two oscillator cycles TDL and TDH. 2. TDL (TDH) is the oscillator cycle during which the DL (DH) output is in the high state. 3. T is defined as starting at the beginning of TDL, and terminating at the end of TDH. Response to MOC Faults (VMOC < VCS < VSOC): Once SiP11205 has completed a normal soft-start cycle, VSS will be clamped at the final voltage, allowing the maximum possible duty cycle on DL and DH. If an MOC fault occurs following the start-up (due to a condition such as an excessive load on the converter’s output), SiP11205 will respond by gradually reducing the available maximum duty cycle of its DL and DH outputs each to be equal to approximately 42 % of their possible 47 % maximum values. This is before any effects of deadtime introduced by RDB are added in. This reduction in available maximum duty cycle is achieved by reducing the voltage on the SS pin to 4 V, as follows: 1. If VMOC < VCS < VSOC at any time during TDL, a current of 20 µA will be drawn out of the SS pin until the beginning of the next TDL. 2. If the voltage on the SS pin remains above the value that would allow an available maximum DL and DH duty cycle of 42 %, SiP11205 will continue operating. 3. If the voltage on the SS pin goes below the value that would allow an available maximum DL and DH duty cycle of 42 %, a hiccup interval is started, during which both DL and DH are held in their low states. 4. The SS pin is discharged towards 0 V by a 400 nA sink current. 5. The hiccup interval is terminated when the SS pin is discharged to 0.25 V. After the above actions have been taken switching on the DL and DH outputs will then resume with a normal soft-start cycle. Response to MOC faults is enabled after the successful completion of any normal soft-start cycle. Response to SOC Faults (VCS > VSOC): This is an immediate, single-cycle response over current shutdown, followed by a hiccup delay and a normal soft-start cycle. Since this is a gross fault protection mechanism, its triggering mechanism is asynchronous to the timing of TDL and TDH. 1. If VCS > VSOC, a hiccup interval is started, during which both DL and DH are held in their low states. 2. The SS pin is discharged towards 0 V by a 400 nA sink current. 3. The hiccup interval is terminated when the SS pin is discharged to 0.25 V. 4. Switching on the DL and DH outputs will then resume with a normal soft-start cycle. Severe over current response is enabled at all times, including the initial ramp-up period of the soft-start pin. This allows SiP11205 to provide rapid fault protection for the converter’s power train. Document Number: 69233 S-81795-Rev. C, 04-Aug-08 www.vishay.com 9 SiP11205 Vishay Siliconix Immediate Response to UVLO Faults: The under voltage protection conditions at converter-level (VINDET pin UVLO) and chip-level (VCC UVLO) will immediately trigger a shutdown-and-retry SS response, with the restart requirements being that: 1. The SS pin has been discharged at a 20 µA rate to the 0.25 V level. 2. The affected supply has recovered to its turn-on threshold. Once these conditions are met, switching will resume with a normal soft-start cycle. Response to UVLO faults is enabled at all times, including the initial ramp-up period of the softstart pin. Immediate Response to an OTP Condition: Failure of the application circuit to provide an external voltage to the VCC pin above the VREG level may result in an OTP condition (TJ > OTPON). Other conditions, such as excessive ambient temperature or, where applicable, failure of airflow over the DC-DC converter circuit, can also trigger an OTP condition. An OTP condition will immediately trigger a shutdown-and-retry soft start response, with the restart requirements being that: 1. The SS pin has been discharged at a 20 µA rate to the 0.25 V level. 2. The chip junction temperature has fallen below the lower OTP threshold. Once these conditions are met, switching will resume with a normal soft-start cycle. Response to the OTP condition is enabled at all times, including the initial ramp-up period of the soft-start pin. Reference The reference voltage of SiP11205 is set at 3.3 V at VREF pin. This pin should be decoupled externally with a 0.1 µF to 1 µF capacitor to GND. Up to 5 mA may be drawn internally from this reference to power external circuits. Note that if the VINDET pin is pulled below 0.55 V (typical), the reference will be turned off, and SiP11205 will enter a low-power "standby" mode. During startup or when VREF is accidentally shorted to ground, this pin has internal short circuit protection limiting the source current to 50 mA. VREF load regulation for 5 mA step is typically 0.45 %. Oscillator The oscillator is designed to operate from 200 kHz to 1 MHz with temperature stability within 15 %. This operating frequency range allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. The oscillator frequency, and therefore the switching frequency, is programmable by the value of resistor and capacitor connected to the ROSC and COSC pins respectively. Note that the switching frequency at pins DL and DH is half of the oscillator frequency, i.e., the DL output Primary Side MOSFET Drivers The low-side MOSFET driver is powered directly from VCC of the chip. The high-side MOSFET however requires the gate voltage to be higher than VIN. This is achieved with a charge pump capacitor CBST between BST and LX, and an external diode to charge and bootstrap the initial charge up voltage across CBST to VCC level. On the alternate oscillator cycle the boost diode isolates BST from VIN and hence BST and LX steps up to VIN + VCC and VIN, respectively. This sequencing insures that DL will always turn on before DH during start-up. The boost capacitor value must be chosen to meet the application droop rate requirement. External Frequency Synchronization The oscillator frequency of this IC can be synchronized to an external source with a simple circuit shown in "Circuit for Frequency Synchronization" diagram. The synchronized frequency should not exceed 1.4 times the set frequency, and the synchronized frequency range should not exceed the IC frequency range. will be active during one oscillator cycle, and the DH during the next oscillator cycle. The feed-forward voltage appears at pin ROSC and equals to VINDET/2. This voltage sets the peak voltage of the oscillator waveform. Therefore the higher input voltage the higher VINDET/2 and the higher oscillator peak voltage. The pulse width of the drive signals DL and DH is then generated by comparing the voltage at RDB pin with the oscillator output saw tooth. The voltage at RDB pin is fixed so the higher input voltage the narrower DL/DH pulse width and the lower the duty cycle. (See Feed-forward Function Diagram.) VINDET The VINDET pin controls several modes of operation and the modes of operation are controlled by shutdown (VSD) and under voltage (VUV) comparators (see block diagram). When the IC is powered solely by VIN and VINDET is less than VSDH due to some external reset condition the pre-regulator is in low power standby mode and the internal bias network is powered down. When VINDET is greater than VSDH but less than VREF and VCC is forced to 12 V the pre-regulator shuts off drawing only leakage current from VIN and quiescent current from VCC. In this mode the controller output drivers remains static (non-switching). When VINDET is above VREF the controller is enabled and both drivers are switching at half the oscillator frequency. If SiP11205 is shut down via this pin, its restart will be by means of a soft-start cycle, as described under "Soft Start" and "Hiccup-Mode Operation" above. The input impedance to ground of this pin is typically 46K ± 30 % and must be taken into account when designing the feed-forward compensation. An external 10:1 resistor divider ratio of supply voltage to VINDET pin is required in a typical application. www.vishay.com 10 Document Number: 69233 S-81795-Rev. C, 04-Aug-08 SiP11205 Vishay Siliconix TYPICAL CHARACTERISTICS 10.2 10.0 9.8 9.6 VREG (V) IVIN (mA) 9.4 9.2 9.0 8.8 8.6 8.4 8.2 - 40 - 15 10 35 60 85 110 135 Temperature (°C) 7.5 7.0 6.5 VIN = 75 V 6.0 5.5 5.0 4.5 - 40 - 15 10 35 60 85 110 135 Temperature (°C) VREG vs. Temperature 3.35 3.30 VUVH 3.25 ICC, IQ (mA) IVIN vs. Temperature 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 - 40 IQ VCC = 12 V ICC VUV (V) 3.20 3.15 3.10 VUVL 3.05 3.00 - 40 - 15 10 35 60 85 110 135 - 15 10 35 60 85 110 135 Temperature (°C) Temperature (°C) VUV vs. Temperature 800 200 ICC and IQ vs. Temperature 700 180 600 VSD (mV) VSDH 500 ISD (µA) 85 110 135 160 140 400 VSDL 300 120 100 200 - 40 - 15 10 35 60 Temperature (°C) 80 - 40 - 15 10 35 60 85 110 135 Temperature (°C) VSD vs. Temperature ISD vs. Temperature Document Number: 69233 S-81795-Rev. C, 04-Aug-08 www.vishay.com 11 SiP11205 Vishay Siliconix TYPICAL CHARACTERISTICS 10 6.0 5.5 9.5 UVLOH UVLO (V) VSS (V) 9.0 7.5 V 5.0 4.5 4.8 V 4.0 3.5 3.0 8.5 8.0 UVLOL 7.5 - 40 - 15 10 35 60 85 110 135 VINDET = 3.6 V 2.5 2.0 - 40 - 15 10 35 60 85 110 135 Temperature (°C) Temperature (°C) UVLO vs. Temperature 23 22 21 20 ISS (µA) - 18 - 19 - 20 - 21 - 22 - 40 19 18 17 16 15 - 40 - 15 - 16 - 17 VSS vs. Temperature IDSS1 (µA) - 15 10 35 60 85 110 135 - 15 10 35 60 85 110 135 Temperature (°C) Temperature (°C) IDSS1 vs. Temperature 0.55 ISS vs. Temperature 140 120 0.50 100 IDSS2 (µA) 0.45 IVINSD (µA) - 15 10 35 60 85 110 135 80 60 40 0.40 0.35 20 0.30 - 40 0 - 40 - 15 10 35 60 85 110 135 Temperature (°C) Temperature (°C) IDSS2 vs. Temperature IVINSD vs. Temperature www.vishay.com 12 Document Number: 69233 S-81795-Rev. C, 04-Aug-08 SiP11205 Vishay Siliconix TYPICAL CHARACTERISTICS 3.5 3.3 3.1 2.9 RDSN (Ω) RDSP (Ω) 4.5 4.0 3.5 2.7 2.5 2.3 2.1 1.9 1.7 1.5 - 40 3.0 2.5 2.0 1.5 - 15 10 35 60 85 110 135 - 40 - 15 10 35 60 85 110 135 Temperature (°C) Temperature (°C) DL RDSN vs. Temperature 3.3 3.1 2.9 2.7 RDSN (Ω) 2.5 2.3 2.1 1.9 1.7 1.5 - 40 1.1 0.9 0.7 - 40 RDSP (Ω) 2.3 2.1 1.9 1.7 1.5 1.3 DL RDSP vs. Temperature - 15 10 35 60 85 110 135 - 15 10 35 60 85 110 135 Temperature (°C) Temperature (°C) DH RDSN vs. Temperature 430 3.304 3.302 420 3.300 410 FREQ (kHz) FDL 400 FDH 390 3.292 380 3.290 3.288 - 40 VREF (V) 3.298 3.296 3.294 DH RDSP vs. Temperature 370 - 40 - 15 10 35 60 85 110 135 Temperature (°C) - 15 10 35 60 85 110 Temperature (°C) FDL/FDH vs. Temperature VREF vs. Temperature Document Number: 69233 S-81795-Rev. C, 04-Aug-08 www.vishay.com 13 SiP11205 Vishay Siliconix TYPICAL CHARACTERISTICS 1.9615 1.9610 1.9605 1.9600 1.9595 VRDB (V) VRDB (V) 1.9590 1.9585 1.9580 RDB2/RDB1 = 33.2 kΩ/47.5 kΩ 2.169 2.167 RDB2/RDB1 = 25.5 kΩ/47.5 kΩ 2.165 2.163 1.9575 1.9570 1.9565 40 45 50 VIN (V) 55 60 2.161 40 45 50 55 60 VIN (V) 65 70 75 VRDB vs. VIN 1.9615 2.170 1.9610 1.9605 1.9600 VRDB (V) 2.169 2.168 VRDB vs. VIN VRDB (V) 1.9595 1.9590 1.9585 1.9580 1.9575 1.9570 1.9565 - 40 - 15 10 35 60 85 110 135 RDB2/RDB1 = 33.2 kΩ/47.5 kΩ VIN = 40 V 2.167 2.166 2.165 2.164 2.163 2.162 - 40 RDB2/RDB1 = 25.5 kΩ/47.5 kΩ VIN = 44 V Temperature (°C) - 15 10 35 60 85 110 135 VRDB Temperature Coefficient Temperature (°C) VRDB Temperature Coefficient 49.5 50 48 46 44 Duty (%) 49.0 RDB2/RDB1 = 25.5 kΩ/47.5 kΩ Duty (%) VIN = 44 V 48.5 RDB2/RDB1 = 25.5 kΩ/47.5 kΩ 42 40 38 36 34 32 30 36 41 46 VIN (V) RDB2/RDB1 = 33.2 kΩ/47.5 kΩ 48.0 VIN = 40 V RDB2/RDB1 = 25.5 kΩ/47.5 kΩ 47.5 47.0 51 56 61 46.5 - 40 - 15 10 35 60 85 110 135 Temperature (°C) Duty vs. VIN Duty vs. Temperature www.vishay.com 14 Document Number: 69233 S-81795-Rev. C, 04-Aug-08 SiP11205 Vishay Siliconix TYPICAL CHARACTERISTICS 65 225 60 200 VSOC 55 RVINDET (kΩ) VCS (mV) 175 50 150 VMOC 125 45 40 35 - 40 - 15 10 35 60 85 110 135 100 - 40 - 15 10 35 60 85 110 135 Temperature (°C) Temperature (°C) RVINDET vs. Temperature 14 96 VIN = 42 V 13 92 Output Voltage (V) VIN = 55 V 11 VIN = 48 V Efficiency (%) VCS vs. Temperature VIN = 48 V VIN = 55 V 12 88 10 VIN = 42 V 9 84 8 0 3 6 9 12 15 Load Current (A) 80 0 3 6 9 12 15 Load Current (A) Line and Load Regulation Efficiency vs. Current Document Number: 69233 S-81795-Rev. C, 04-Aug-08 www.vishay.com 15 SiP11205 Vishay Siliconix TYPICAL WAVEFORMS System Startup System Shutdown Primary Drive Signal DL vs. Inductor Voltage Hiccup when Output Shorted Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?69233. www.vishay.com 16 Document Number: 69233 S-81795-Rev. C, 04-Aug-08 Package Information Vishay Siliconix POWER IC THERMALLY ENHANCED PowerPAKR TSSOP: 14/16-LEAD 3 D 6 N CL 8 e −B− 7 R 0.25 − H− 4 CL E1 8 E GAUGE PLANE SEATING PLANE q1 R1 L L1 DETAIL A 0.7500 1 0.7500 e 23 0.07600 0.025−0.075 DP PIN 1 INDICATOR POLISH TOP VIEW 7 − A− CL aaa C DETAIL A ccc S CL A2 A SEATING PLANE B B 9 − C− b bbb M C B S A S A1 Y c1 CL X 5 (b) c b1 DETAIL B-B BOTTOM VIEW EXPOSED PAD Document Number: 72778 31-Mar-05 www.vishay.com 1 of 2 Package Information Vishay Siliconix POWER IC THERMALLY ENHANCED PowerPAKR TSSOP: 14/16-LEAD MILLIMETERS Dim A A1 A2 b b1 c c1 D e E E1 L L1 R R1 q1 N (14) N (16) X Y (14) Y (16) aaa bbb ccc ddd Min − 0.025 0.80 0.19 0.19 0.09 0.09 4.9 6.2 4.3 0.45 0.09 0.09 0 INCHES* Min − 0.001 0.0315 0.0075 0.0075 0.0035 0.0035 0.1929 0.2441 0.1693 0.0177 0.0035 0.0035 0 Nom − − 0.90 − 0.22 − − 5.0 0.65 BSC 6.4 4.4 0.60 1.0 REF − − − 14 16 Max 1.20 0.100 1.05 0.30 0.25 0.20 0.16 5.1 6.6 4.5 0.75 − − 0 Nom − − 0.0354 − 0.0087 − − 0.1968 0.0256 BSC 0.2520 0.1732 0.0236 0.0394 REF − − − 14 16 Max 0.0472 0.0039 0.0413 0.0118 0.0098 0.0079 0.0063 0.2008 0.2598 0.1772 0.0295 − − 0 2.95 3.15 2.95 3.0 3.2 3.0 0.10 0.10 0.05 0.20 3.05 3.25 3.05 0.116 0.124 0.116 0.118 0.126 0.118 0.0039 0.0039 0.0020 0.0079 0.120 0.128 0.120 ECN: S-50568—Rev. B, 04-Apr-05 DWG: 5913 *Dimensions are in mm converted to inches. NOTES: 1. All dimensions are in millimeters (angles in degrees). 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. 4. Dimension “E1” does not include internal flash or protrusion. 5. Dimension “b” does not include Dambar protrusion. 6. “N” is the maximum number of lead terminal positions for the specified package length. 7. Datums −A− and −B− to be determined at datum plane −H− . 8. Dimensions “D” and “E1” are to be determined at datum plane −H− . 9. Cross section B-B to be determined at 0.10 to 0.25 mm from the lead tip. 10. Refer to JEDEC MO-153, Issue C., Variation ABT. 11. Exposed pad will depend on the pad size of the L/F. www.vishay.com 2 of 2 Document Number: 72778 31-Mar-05 Package Information Vishay Siliconix PowerPAKr MLP44-16 (POWER IC ONLY) JEDEC Part Number: MO-220 D -BD/2 AA 4 aaa C 2 X aaa C 2 X // Nx ccc C 9 0.08 C A A1 NL D2 6 (NE-1) x e 2 1 N N-1 Detail A (ND-1) x e 8 Bottom View Document Number: 72802 16-May-05 ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ Top View Side View A3 D2/2 Index Area (D 2 E 2) E/2 E BB -ADD Detail A CC Seating Plane -C- Detail B Datum A or B Nr E2/2 E2 Terminal Tip Exposed Pad Nb 5 e Even Terminal/Side Detail B Odd Terminal/Side 8 e/2 5 e Terminal Tip 5 bbb M C A B www.vishay.com 1 Package Information Vishay Siliconix PowerPAKr MLP44-16 (Power IC Only) JEDEC Part Number: MO-220 MILLIMETERS* Dim Min Nom Max 1.00 0.05 − − − − 0.35 − − − 2.8 − 2.8 0.5 − − − INCHES Min 0.0315 0 − − − − 0.0098 − − − 0.1004 − 0.1004 0.0118 − − b(min)/2 Nom 0.0354 0.0008 0.0079 0.0136 0.0059 0.0136 0.0118 0.0039 0.0071 0.0039 0.1575 BSC 0.1063 0.0071 0.1575 BSC 0.1063 0.0256 BSC 0.0157 16 4 4 − Max 0.0394 0.0020 − − − − 0.138 − − − 0.1102 − 0.1102 0.0197 − − − Notes A 0.80 0.90 A1 0 0.02 A3 − 0.20 Ref AA − 0.345 aaa − 0.15 BB − 0.345 b 0.25 0.30 bbb − 0.10 CC − 0.18 ccc − 0.10 D 4.00 BSC D2 2.55 2.7 DD − 0.18 E 4.00 BSC E2 2.55 2.7 e 0.65 BSC L 0.3 0.4 N 16 ND − 4 NE − 4 r b(min)/2 − * Use millimeters as the primary measurement. ECN: S-50794—Rev. B, 16-May-05 DWG: 5905 5 3, 7 6 6 NOTES: 1. 2. 3. 4. Dimensioning and tolerancing conform to ASME Y14.5M-1994. All dimensions are in millimeters. All angels are in degrees. N is the total number of terminals. The terminal #1 identifier and terminal numbering convention shall conform to JESD 95-1 SPP-012. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1 identifier may be either a molded or marked feature. The X and Y dimension will vary according to lead counts. Dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. ND and NE refer to the number of terminals on the D and E side respectively. Depopulation is possible in a symmetrical fashion. Variation HHD is shown for illustration only. Coplanarity applies to the exposed heat sink slug as well as the terminals. 5. 6. 7. 8. 9. www.vishay.com 2 Document Number: 72802 16-May-05 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1