SiP1759
Vishay Siliconix
Buck-Boost Regulator
DESCRIPTION
The SiP1759 is a buck-boost regulating charge pump. It is designed to provide a regulated output from 1 cell Li Ion or 2/ 3 cell NiMH voltages found in handheld portable equipment, 1.6 V to 5.5 V. SiP1759 allows the option of a fixed 3.3 V output voltage, or an adjustable output which can be set from 2.5 V to 5.5 V. The output current is up to 100 mA. For flexibility in application, SiP1759 has a shutdown pin (SD) and an ERROR output to indicate when the output voltage is in regulation. SiP1759 is available in a 10 pin MSOP package and is rated over the industrial temperature range of - 40 °C to 85 °C.
FEATURES
• • • • • • • Output voltage - fixed 3.3 V or adjustable from 2.5 V to 5.5 V 1.6 V to 5.5 V input voltage range 100 mA output current 60 µA quiescent current Shutdown current < 1 µA Short circuit crotection Thermal shutdown • MSOP-10 package
APPLICATIONS
• • • • 1 cell Li ion battery powered equipment 2 to 3 cell NiMH battery powered equipment 2 to 3 cell alkaline battery powered equipment Backup battery boost converters
TYPICAL APPLICATION CIRCUIT
CX
CX
CXVIN CiN
CX+ VOUT VIN
CXPGND
CX+ VOUT
SiP1759
SD GND PGND ERROR FB
R
COUT
CiN
SiP1759
SD GND PGND ERROR FB
R
R1
COUT
R2
Fixed Output
Adjustable Output Voltage
Document Number: 72949 S09-1453-Rev. D, 03-Aug-09
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SiP1759
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (all voltages referenced to GND = 0 V)
Parameter Input Voltage (VIN) OUT SD, FB, ERROR to GND CX- to GND CX+ to GND Storage Temperature Maximum Junction Temperature Power Dissipationa,b MSOP-10 (TA = 70 °C) Notes: a. Device Mounted with all leads soldered or welded to PC board. b. Derate 5.6 mW/°C above 25 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Limit - 0.3 to 6 - 0.3 to 6 - 0.3 to (VIN + 0.3) - 0.3 to (the greater of VIN or VOUT) + 1) - 55 to 150 150 444
Unit
V
°C mW
RECOMMENDED OPERATING RANGE (all voltages referenced to GND = 0 V)
Parameter Input Voltage Range Output Voltage Adjustment Range CIN CX COUT Operating Temperature Range Limit 1.6 to 5.5 2.5 to 5.5 10 0.33 10 - 40 to 85 °C µF Unit V
SPECIFICATIONS
Test Condition Unless Specified VIN = VSD = 2 V, FB = PGND = GND CIN = 10 µF, Cx = 0.33 µF, COUT = 10 µF Limits - 40 °C to 85 °C Temp.a Full Full 1.6 V ≤ VIN ≤ 5.5 V 2 V ≤ VIN ≤ 5.5 V, 1 mA ≤ IOUT ≤ 50 mA Output Voltage VOUT 2.5 V ≤ VIN ≤ 5.5 V, 1 mA ≤ IOUT ≤ 100 mA 2 V ≤ VIN ≤ 5.5 V, 1 mA ≤ IOUT ≤ 50 mA 2.5 V≤ VIN ≤ 5.5 V, 1 mA ≤ IOUT ≤ 100 mA Maximum Output Current Transient Load Current Quiescent Supply Current Shutdown Supply Current Output Leakage Current in Shutdown SD Logic Input Voltage SD Input Leakage Current FB Regulation Voltage FB Input Current VFB IIFB IQ IQSD SD VIL VIH IOUT(max) 2.5 V ≤ VIN ≤ 5.5 V IOUT ≤ 100 mA (RMS) VIN = VSD = 4 V, VFB = 0 V, Stepping Down VIN = VSD = 2 V, VFB = 0 V, Stepping Up 1.6 V ≤ VIN ≤ 5.5 V, VSD = 0 V VIN = 2 V, VOUT = 3.3 V, VSD = 0 V 1 6 V ≤ VIN ≤ 5 5 V VSD = 5.5 V VIN = 1.65 V, VOUT = 3.3 V VFB = 1.27 V Full 0 °C to 85 °C Full Full 0 °C to 85 °C Full Full Full Full Full Full Full Full 0.7 * VIN -1 1.205 1.235 25 1 1.265 200 Min. 1.6 0.7 2.5 3.17 3.17 3.15 3.15 100 200 60 60 1 1 100 100 5 5 0.25 * VIN V µA V nA µA 3.3 3.3 1.0 Typ.b Max. 5.5 1.5 5.5 3.43 3.43 3.45 3.45 mA V Unit
Parameter Input Voltage Range Input Undervoltage Lockout Output Voltage Adjustment Range
Symbol VIN VUVLO
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Document Number: 72949 S09-1453-Rev. D, 03-Aug-09
SiP1759
Vishay Siliconix
SPECIFICATIONS
Test Condition Unless Specified VIN = VSD = 2 V, FB = PGND = GND CIN = 10 µF, Cx = 0.33 µF, COUT = 10 µF Internal feedback External feedback Falling edge at FB VOL fOSC IOL = 0.5 mA, VIN = 2 V VERROR = 5.5 V, VFB = 1.27 V 1.6 V ≤ VIN ≤ 5.5 V, VFB = 1 V VOUT = 0 V, 2.5 V ≤ VIN ≤ 5.5 V foldback current limit Temperature rising Limits - 40 °C to 85 °C Temp.a Full Full Full Full Full Full Full Full Full VIN = 3.6 V, IOUT = 10 mA Full 1.2 200 1.0 Min. Typ.b 100 100 1.1 5 0.01 1.5 110 160 20 90 % 1.2 100 0.2 1.8 Max. 50 Unit mV V mV µA MHz mA
Parameter FB Dual Mode Threshold ERROR Trip Voltage ERROR Output Low Voltage ERROR Leakage Current Switching Frequency Output Short-Circuit Current Thermal Shutdown Temperature Thermal Shutdown Hysteresis Efficiency
Symbol
°C
Notes: a. Full = as determined by the operating suffix. b. Typical values are for Design Aid only, not guaranteed nor subject to production testing.
PIN CONFIGURATION AND TRUTH TABLE
MSOP-10
ERROR SD VIN VIN GND
1 2 3 4 5 10 9 8 7 6
ORDERING INFORMATION
Part Number
FB VOUT CX+ CXPGND
Temperature Range - 40 °C to 85 °C Temperature Range - 40 °C to 85 °C
Marking 1759 Board Surface Mount
SiP1759DH-T1 Eval Kit SiP1759DB
Top View
PIN DESCRIPTION
Pin Number 1 2 3, 4 5 6 7 8 9 10 Name ERROR SD VIN GND PGND CXCX+ VOUT FB Shutdown input Input voltage Ground Power ground Negative terminal of the charge pump capacitor Positive terminal of the charge pump capacitor Regulated output voltage Feedback input - connected to GND for fixed 3.3 V output. Connected to a resistive divider for an adjustable output Function Open drain error flag - a low output indicates that the output voltage is out of range
Document Number: 72949 S09-1453-Rev. D, 03-Aug-09
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SiP1759
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
CXCX+
VIN
PGND
S1 Control
S2 VOUT
SD
Bias
Oscillator
+ + -
1.235 V ERROR
FB + -
+ + -
GND
+ -
DETAILED DESCRIPTION
The SiP1759 is a buck-boost regulating charge pump. This allows for the VIN to be a higher or lower voltage than the regulated output. This is done with a charge pump that when VIN is lower than VOUT is a regulated voltage doubler. When VIN is higher than VOUT the charge pump is a step down gated switch. In boost mode, the IC controls the transfer capacitor through CX+ and CX- pins, switching the charge to the output keeping it regulated. In this mode the charge pump only switches to maintain regulation, the output ripple does not increase with light loads. In buck mode, the CX- pin is internally connected to PGND and the CX+ is switched internally between VIN and VOUT. Unless VIN is significantly larger than VOUT (VIN ≥ VOUT + 1 V), in heavy load the IS will slip from buck mode to boost mode as necessary to charge the transfer capacitor. Shutdown Mode The IC is designed to conserve power by decreasing current consumption during normal operation as well as shutdown mode. Pulling the SD pin logic low, the output is disconnected from the input and is in high impedance; the internal circuitry of the oscillator, control logic, and the charge-pump switches are turned off, decreasing the current consumption to less than 1 µA. Undervoltage Lockout When VIN falls below 1 V the undervoltage lockout disables the SiP1759.
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Power OK Output POK is an open-drain output that goes low when the regulator feedback voltage falls below 1.1 V. A 10 kΩ to 1 MΩ pull-up resistor from POK to OUT should be used to provide a logic output and keep current consumption to a minimum. Connect POK to GND or leave floating if not used. The POK output is high impedance when the IC is in shutdown mode. Fixed Output The SiP1759 can be configured as a fixed 3.3 V output regulator or as an adjustable output from 2.5 V to 5.5 V. In the fixed 3.3 V output mode the feedback voltage is generated from the internal resistor-divider network. The FB pin must be tied to GND. Soft-Start and Short Circuit Protection The IC features a soft-start mechanism that limits the inrush current during start-up and if the output is short circuited the SiP1759 limits the output current to 110 mA. Thermal Shutdown The SiP 1759 is designed with a thermal shutdown circuit that will shut down the IC when the die temperature exceeds 160 °C. The thermal shutdown has 20 °C of hysteresis, insuring when the die cools down the IC will turn on again.
SiP1759
Vishay Siliconix
DESIGNS CONSIDERATIONS
Setting the Adjustable Output Voltage The SiP1759 regulated output can be adjusted from 2.5 V to 5.5 V via resistor divider network from VOUT to GND (see Typical Application Circuits). R1 and R2 should be kept in the 50 kΩ to 100 kΩ range for low power consumption, while maintaining adequate noise immunity. The value R1 is calculated using the following formula: R1 = R2 {(VOUT/VFB) - 1} VFB is nominally 1.235 V. Capacitor Selection Capacitor selection for CIN, COUT and CX will have an impact in the voltage output ripple, output current and overall physical size of the circuit. Ceramic capacitors are recommenced for their low ESR (≤ 20 mΩ) which will help keep the output voltage ripple at a minimum. The initial values for the CIN and COUT capacitors should be 10 µF, the CX capacitor should be 0.33 µF. Output Voltage Ripple The SiP1759 automatically decides whether to be in step up mode or step down mode depending on the VIN, VOUT and current load conditions, therefore the voltage output ripple will vary. In step-up mode the voltage output ripple is higher than step-down mode. But unless VIN is significant larger than VOUT (VIN ≥ VOUT + 1 V) , in heavy load the IC will slip from buck mode to boost mode as necessary to charge the transfer capacitor and the ripple will increase. Reducing the CX capacitor value will cause an increase in the switching frequency and a reduction of the output ripple.
TYPICAL CHARACTERISTICS
120 IOUT at 10 mA Quiescent Current (A) IOUT at 50 mA Efficiency (%) 80 IOUT at 100 mA 1.00E-01 1.00E-02
100
1.00E-03
60
1.00E-04
40
1.00E-05
20
1.00E-06
0 1.5
1.00E-07 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.5 1.5 Input Voltage (V) 2.5 3.5 Input Voltage (V) 4.5 5.5
Efficiency vs. Input Voltage
4.0 Output Ripple Voltage (V) 3.5 3.0 2.5 2.0 1.5 1.0 (VOUT < VIN) RLOAD = 33 Ω
Quiescent Current vs. Input Voltage (No Load)
0.20
0.16 100 mA 0.12
Output Voltage (V)
0.08 50 mA 0.04
0.5 10 mA 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.00 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
Input Voltage (V)
Start-Up Input Voltage
Output voltage Ripple vs. Input Voltage
Document Number: 72949 S09-1453-Rev. D, 03-Aug-09
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SiP1759
Vishay Siliconix
TYPICAL WAVEFORMS
VOUT 50 mV/div
VOUT 50 mV/div
VC+ 5 V/div
VC+ 5 V/div
VIN 50 mV/div
VIN 50 mV/div
5 µs/div VIN = 2.5 V VOUT = 3.3 V RLOAD = 33 Ω
5 µs/div VIN = 4.2 V VOUT = 3.3 V RLOAD = 33 Ω
Figure 1. Typical Switching Waveform (VOUT > VIN)
Figure 2. Typical Switching Waveforms (VOUT > VIN)
VOUT 50 mV/div
VOUT 50 mV/div
IOUT 100 mA/div 100 µs/div VIN = 2.5 V VOUT = 3.3 V IOUT Step: 10 mA - 100 mA
100 µs/div VIN = 4.2 V VOUT = 3.3 V IOUT Step: 10 mA - 100 mA
IOUT 100 mA/div
Figure 3. Load Transient Response (VOUT > VIN)
Figure 4. Load Transient Response (VOUT < VIN)
VOUT 1 V/div IIN 200 mA /div VERROR 5 V /div
VOUT 1 V/div IIN 200 mA /div VERROR 5 V /div
VSD 2 V/div 0.5 ms/div VIN = 2.5 V VOUT = 3.3 V
0.5 ms/div VIN = 4.2 V VOUT = 3.3 V
VSD 2 V/div
Figure 5. Turn On/Off Response (VIN = 2.5 V)
Figure 6. Turn On/Off Response (VIN = 4.2 V)
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72949.
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Document Number: 72949 S09-1453-Rev. D, 03-Aug-09
Package Information
Vishay Siliconix
MSOP:
JEDEC Part Number: MO-187, (Variation AA and BA)
5
10-LEADS (POWER IC ONLY)
(N/2) Tips) 2X
A B C 0.20
N N-1
0.60
0.48 Max Detail “B” (Scale: 30/1) Dambar Protrusion
E
0.50
0.60
12 Top View
e1
N/2 b b1 With Plating A c1
0.10 C 0.08 M C B S AS
7
e
See Detail “B”
c
6
-H-
D
3
A1
-A-
Seating Plane
Base Metal
Section “C-C” Scale: 100/1 (See Note 8)
0.25 BSC Parting Line
Side View
See Detail “A”
C C
0.07 R. Min 2 Places Seating Plane A2
0.05 S
ς E1
L4 T
0.95 Detail “A” (Scale: 30/1)
-C-
-B3
End View
NOTES: 1. 2. 3. Die thickness allowable is 0.203"0.0127. Dimensioning and tolerances per ANSI.Y14.5M-1994. Dimensions “D” and “E1” do not include mold flash or protrusions, and are measured at Datum plane -H- , mold flash or protrusions shall not exceed 0.15 mm per side. Dimension is the length of terminal for soldering to a substrate. Terminal positions are shown for reference only. Formed leads shall be planar with respect to one another within 0.10 mm at seating plane. The lead width dimension does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the lead width dimension at maximum material condition. Dambar cannot be located on the lower radius or the lead foot. Minimum space between protrusions and an adjacent lead to be 0.14 mm. See detail “B” and Section “C-C”. Section “C-C” to be determined at 0.10 mm to 0.25 mm from the lead tip. Controlling dimension: millimeters.
N = 10L
MILLIMETERS Dim A A1 A2 b b1 c c1 D E E1 e e1 L N T Min
− 0.05 0.75 0.17 0.17 0.13 0.13
Nom
− 0.10 0.85 − 0.20 − 0.15 3.00 BSC 4.90 BSC
Max
1.10 0.15 0.95 0.27 0.23 0.23 0.18
Note
4. 5. 6. 7.
8 8
3 3.10 3
2.90
3.00 0.50 BSC 2.00 BSC
8. 9.
10. This part is compliant with JEDEC registration MO-187, variation AA and BA. 11. Datums -A- and -B- to be determined Datum plane -H- . 12. Exposed pad area in bottom side is the same as teh leadframe pad size.
0.40 0_
0.55 10 4_
0.70 6_
4 5
ECN: S-40082—Rev. A, 02-Feb-04 DWG: 5922 www.vishay.com
Document Number: 72817 28-Jan-04
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Vishay
Disclaimer
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Document Number: 91000 Revision: 11-Mar-11
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