SIP21106_09

SiP21106, SiP21107, SiP21108 Vishay Siliconix 150-mA Low Noise, Low Dropout Regulator DESCRIPTION The SiP21106 BiCMOS 150 mA low noise LDO voltage regulators are the perfect choice for low battery operated low powered applications. An ultra low ground current and low dropout voltage of 135 mV at 150 mA load helps to extend battery life for portable electronics. Systems requiring a quiet voltage source, such as RF applications, will benefit from the SiP21106 low output noise. The SiP21107 do not require a noise bypass capacitor and provides an error flag pin (POK or Power OK). POK output requires an external pull-up resistor and goes low when the supply has not come up to voltage. The SiP21108 output is adjusted with an external resistor network. The SiP21106, SiP21107, SiP21108 regulators allow stable operation with very small ceramic output capacitors, reducing board space and component cost. They are designed to maintain regulation while delivering 330 mA peak current upon turn-on. During start-up, an active pull-down circuit improves the output transient response and regulation. In shutdown mode, the output automatically discharges to ground through a 100 Ω NMOS. The SiP21106, SiP21107, SiP21108 are available in TSOT23-5L a super thin lead (Pb)-free TSC75-6L and SC70-5L packages for operation over the industrial operation range (- 40 °C to 85 °C). FEATURES • SC70-5L (2.1 mm x 2.1 mm x 0.95 mm) • TSOT23-5L (3.05 mm x 2.85 mm x 1.0 mm) • TSC75-6L package (1.6 mm x 1.6 mm RoHS COMPLIANT x 0.55 mm), TSOT23-5L and SC70-5L Package Options • 1.0 % output voltage accuracy at 25 °C • Low dropout voltage: 135 mV at 150 mA • SiP21106 low noise: 60 µV(rms) (10 Hz to 100 kHz bandwidth) with 10 nF over full load range • 35 µA (typical) ground current at 1 mA load • 1 µA maximum shutdown current at 85 °C • Output auto discharge at shutdown mode • Built-in short circuit (330 mA typical) and thermal protection (160 °C typical) • SiP21108 adjustable output voltage • SiP21107 POK Error Flag • - 40 °C to + 125 °C junction temperature range for operation • Uses low ESR ceramic capacitors • Fixed voltage output 1.2 V to 5 V in 50 mV steps • Compliant to RoHS Directive 2002/95/EC APPLICATIONS • • • • • • Cellular phones, wireless handsets PDAs MP3 players Digital cameras Pagers Wireless modem • Noise-sensitive electronic systems TYPICAL APPLICATION CIRCUIT VIN C IN = 1 µF 1 VIN VOUT 5 VOUT C OUT = 1 µF EN EN BP C Bypass = 10 nF 2 GND SiP21106 GND SiP21106 BP 4 C Bypass = 10 nF VIN C IN = 1 µF VIN NC EN 3 EN VOUT VOUT COUT = 1 µF TSOT23-5L/SC70-5LPackage TSC75-6L Package Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 www.vishay.com 1 SiP21106, SiP21107, SiP21108 Vishay Siliconix TYPICAL APPLICATION CIRCUIT 1 CIN = 1 µF 2 VIN VOUT 5 VOUT COUT = 1 µF EN EN POK POK GND SiP21107 GND SiP21107 4 POK VIN CIN = 1 µF VIN NC 3 EN POK VOUT VOUT C OUT =1 µF TSOT23-5L/SC70-5LPackage TSC75L-6 Package VIN C IN = 1 µF 1 VIN VOUT 5 COUT = 1 µF VOUT EN EN Adj 2 GND SiP21108 GND SiP21108 NC EN 3 EN Adj 4 VIN CIN = 1 µF VIN VOUT VOUT C OUT = 1 µF TSOT23-5L/SC70-5L Package TSC75-6L Package ABSOLUTE MAXIMUM RATINGS Parameter Input Voltage, VIN to GND VEN (See Detailed Description) Output Current (IOUT) Output Voltage (VOUT) TSC75-6L Package Power Dissipation (PD)a Package Thermal Resistance (θJA) Storage Temperature, TSTG Lead Temperature, TL c b Limit - 0.3 to 6.5 - 0.3 to 6.5 Short Circuit Protected - 0.3 to VIN + 0.3 TSOT23-5L 305 180 125 - 65 to 150 260 SC70-5L 187 294 420 131 Unit V V mW °C/W Maximum Junction Temperature, TJ(max) °C Notes: a. Derate 7.6 mW/°C for TSC75-6L package, 5.5 mW/°C for TSOT23-5L and 3.4 mW/°C for SC70-5L package above TA = 70 °C. b. Device mounted with all leads soldered or welded to multilayer 1S2P PC board. c. Soldering for 5 s. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Parameter Input Voltage, VIN Operating Ambient Temperature TA Limit 2.2 to 6 - 40 to 85 Unit V °C www.vishay.com 2 Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 SiP21106, SiP21107, SiP21108 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Specified VIN = VOUT(nom) + 1.0 V = VEN IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF - 40 °C < TA < 85 °C for full Parameter Input Voltage Range Symbol VIN Temp.a Min.b Full 2.2 - 1.0 - 2.5 - 1.5 -4 Room Full Room Full Full Full Typ.c Max.b 6 1.0 2.5 1.5 4 Unit V IOUT = 1 mA Output Voltage Accuracy VOUT SiP21106/7 (1.2 V) IOUT = 1 mA Feedback Voltage (SiP21108 Version only) Line Regulation VAdj LNR VOUT ≥ 2.6 V, IOUT: 1 mA to 150 mA VOUT < 2.6 V, IOUT: 1 mA to 150 mA IOUT = 1 mA Ground Pin Currente IGND IOUT = 150 mA Shutdown Supply Current ICC(off) VEN = 0 V SiP21106 VOUT(nom) = 2.8 V, BW = 10 Hz to 100 kHz, 1 mA < IOUT < 150 mA, CBP = 0.01 µF SiP21107/8 VOUT(nom) = 2.8 V, BW = 10 Hz to 100 kHz, 1 mA < IOUT < 150 mA EN to VOUT delay; IOUT = 1 mA SiP21106, CBP = 0.01 µF IOUT = 10 mA Ripple Rejection PSRR SiP21107/8 SiP21106, CBP = 0 µF IOUT = 10 mA Output Current Limit Auto Discharge Resistance IO_LIM RDIS VOUT = 0 V EN = 0 V, VOUT = 1 V For VOUT < 2.2 V, EN = 0 V, VOUT = 1 V IOUT = 50 mA Dropout Voltaged (2.2 V ≤ VOUT(nom) < 2.6 V) VDO IOUT = 100 mA IOUT = 150 mA IOUT = 50 mA Dropout Voltage (VOUT(nom) ≥ 2.6 V) VDO IOUT = 100 mA IOUT = 150 mA EN Pin Input Voltage EN Pin Input Current VENH VENL IEN High = Regulator On (Rising) Low = Regulator Off (Falling) f = 1 kHz f = 10 kHz f = 100 kHz f = 1 kHz f = 10 kHz f = 100 kHz % Room 1.188 1.170 - 0.2 1.2 0.006 0.003 0.005 35 39 0.02 60 1.212 1.230 0.2 0.006 V %/V Room Room Room Full Room Full Full Room Load Regulation LDR %/mA 0.009 75 85 75 85 1 µA µA Output Noise Voltagef (RMS) eN µV Room 350 70 Room Room Room Room Room Room Room Room Room Room Full Room Full Room Full Room Full Room Full Room Full Full Full Room 0.009 1.2 0.4 170 75 56 40 72 53 38 330 100 120 45 55 90 106 135 160 45 55 90 106 135 160 180 220 V µA 250 300 mV 600 mA Ω dB µs Output Voltage Turn-On Time ton Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 www.vishay.com 3 SiP21106, SiP21107, SiP21108 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Specified VIN = VOUT(nom) + 1.0 V IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF - 40 °C < TA < 85 °C for full Parameter Thermal Shutdown Junction Temperature Thermal Hysteresis Error Flag Section (SiP21107 Version only) POK(OFF) Leakage POK(ON) Voltage Symbol TJ(S/D) THYST IOFF VPOKL Temp.a Min.b Typ.c Max.b Room Room 160 20 1 0.4 90 Full 91 Room 1.5 40 93 96 Unit °C RPU to VOUT or VIN EN = 0 V, IPOK = 0.5 mA VOUT rising, POK goes high VOUT(nom) ≥ 2.2 V, IOUT = 1 mA VOUT rising, POK goes high VOUT(nom) < 2.2 V, IOUT = 1 mA VIN falling, IOUT = 1 mA, POK goes low VOUT to POK delay, IOUT = 1 mA Full Full µA V POK Threshold g VPOKLH % POK Hysteresis POK Voltage Delay Time VHYST TP_Delay µs Notes: a. Room = 25 °C, Full = - 40 to 85 °C. Derate 7.6 mW/°C for TSC75 and 5.5 mW/°C for SOT23 above TA = 70 °C. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. Dropout voltage is defined as the input-to-output differential voltage at which the output voltage drops 2 % below its nominal value with constant load. For outputs = 2.2 V, dropout voltage is not applicable due to 2.2 V minimum input voltage requirement. e. Ground current is specified for normal operation as well as “drop-out” operation. f. Output noise is proportional to output voltage. Use formula eN = 60 µV(rms)*VOUT/2.8 V. g. POK threshold percentage is calculated by VIN/VOUT x 100 %. The POK is measured with a differential voltage across VIN and VOUT until POK turn on (low threshold) or off (high threshold). For VOUT less than 2.2 V, POK is guaranteed functionality only. TIMING WAVEFORMS VIN VEN tr 0V 1 µs tON VNOM 0.95 VNOM VOUT Figure 1. www.vishay.com 4 Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 SiP21106, SiP21107, SiP21108 Vishay Siliconix PIN CONFIGURATION EN BP/Adj/POK BP/Adj/POK 6 GND NC NC 5 1 2 3 GND EN VIN TOP VIEW VOUT VOUT 4 VIN TSC75-6L Package (1.6 mm x 1.6 mm x 0.55 mm) BOTTOM VIEW VIN GND EN 1 2 3 5 VOUT VOUT 5 1 2 VIN GND EN 4 BP/Adj/POK BP/Adj/POK 4 3 TOP VIEW TSOT23-5L/SC70-5LPackage Figure 2. BOTTOM VIEW PIN DESCRIPTION Pin Number TSC75-6L Pin Number TSOT23-5L/ SC70-5L 3 2 1 5 Name Function By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to VIN if unused. Do not leave floating. Ground pin. For better thermal capability, directly connected to large ground plane. Input supply pin. Bypass this pin with a 1 µF ceramic or tantalum capacitor to ground. Output voltage. Connect COUT between this pin and ground. No Connection. - BP (SiP21106): Noise bypass pin. For low noise applications, a 10 nF ceramic capacitor should be connected from this pin to ground. - Adj (SiP21108): Adjust input pin. Connect feedback resistors to program the output voltage for trim value of 1.2005 V. - POK (SiP21107): Power OK (error flag) pin. Open-drain output, which requires connecting a pull-up resistor to VIN or VOUT. POK pin is actively high to indicate an output normal operation condition on regulator and goes low to indicate under-voltage fault condition. 1 2 3 4 5 EN GND VIN VOUT NC 6 4 BP/Adj/POK Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 www.vishay.com 5 SiP21106, SiP21107, SiP21108 Vishay Siliconix ORDERING INFORMATION Part Number SiP21108DVP-T1-E3 SiP21106DVP-12-E3 SiP21106DVP-18-E3 SiP21106DVP-25-E3 SiP21106DVP-26-E3 SiP21106DVP-28-E3 SiP21106DVP-285-E3 SiP21106DVP-30-E3 SiP21106DVP-33-E3 SiP21106DVP-46-E3 SiP21106DVP-475-E3 SiP21107DVP-12-E3 SiP21107DVP-18-E3 SiP21107DVP-25-E3 SiP21107DVP-26-E3 SiP21107DVP-28-E3 SiP21107DVP-30-E3 SiP21107DVP-33-E3 SiP21107DVP-46-E3 SiP21107DVP-285-E3 SiP21108DT-T1-E3 SiP21106DT-12-E3 SiP21106DT-18-E3 SiP21106DT-25-E3 SiP21106DT-26-E3 SiP21106DT-28-E3 SiP21106DT-285-E3 SiP21106DT-30-E3 SiP21106DT-33-E3 SiP21106DT-45-E3 SiP21106DT-46-E3 SiP21106DT-475-E3 SiP21107DT-12-E3 SiP21107DT-18-E3 SiP21107DT-25-E3 SiP21107DT-26-E3 SiP21107DT-28-E3 SiP21107DT-285-E3 SiP21107DT-30-E3 SiP21107DT-33-E3 SiP21107DT-46-E3 Marking AA BA BG BP BR BT CT BV BY CM CU DA DG DP DR DT DV DY EM ET N9 NP N1 NA NC N2 NE NG N3 NM N4 NJ NQ N5 NB ND N6 NF NH N7 N8 Voltage Adjustable 1.2 1.8 2.5 2.6 2.8 2.85 3 3.3 4.6 4.75 1.2 1.8 2.5 2.6 2.8 3 3.3 4.6 2.85 Adjustable 1.2 1.8 2.5 2.6 2.8 2.85 3 3.3 4.5 4.6 4.75 1.2 1.8 2.5 2.6 2.8 2.85 3 3.3 4.6 - 40 °C to 85 °C TSOT23-5L - 40 °C to 85 °C TSC75-6L Temperature Range Package www.vishay.com 6 Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 SiP21106, SiP21107, SiP21108 Vishay Siliconix ORDERING INFORMATION SiP21108DR-T1-E3 SiP21106DR-12-E3 SiP21106DR-18-E3 SiP21106DR-25-E3 SiP21106DR-26-E3 SiP21106DR-28-E3 SiP21106DR-285-E3 SiP21106DR-30-E3 SiP21106DR-33-E3 SiP21106DR-46-E3 SiP21106DR-475-E3 SiP21107DR-12-E3 SiP21107DR-18-E3 SiP21107DR-25-E3 SiP21107DR-26-E3 SiP21107DR-28-E3 SiP21107DR-285-E3 SiP21107DR-30-E3 SiP21107DR-33-E3 SiP21107DR-46-E3 N9 NP N1 NA NC N2 NE NG N3 N4 NJ NQ N5 NB ND N6 NF NH N7 N8 Adjustable 1.2 1.8 2.5 2.6 2.8 2.85 3 3.3 4.6 4.75 1.2 1.8 2.5 2.6 2.8 2.85 3 3.3 4.6 - 40 °C to 85 °C SC70-5L Note: Other fixed output voltage options are available. Please contact your Vishay sales representative or distributor for details. Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 www.vishay.com 7 SiP21106, SiP21107, SiP21108 Vishay Siliconix TYPICAL CHARACTERISTICS 3.0 2.5 2.0 VOUT (V) I OUT = 0 mA 1.5 I OUT = 150 mA 1.0 0.5 SiP21106: 2.8 V 0.0 0 1 2 3 4 5 6 - 1.50 - 40 - 15 10 35 1.00 0.50 Deviation (%) 0.00 I OUT = 1 mA - 0.50 - 1.00 SiP21106: 2.8 V 60 85 VIN (V) Temperature (°C) Output Voltage vs. Input Voltage Output Voltage Accuracy vs. Temperature 180 160 140 120 V DO (mV) 100 80 60 40 20 SiP21106: 2.8 V 0 0 25 50 75 100 125 150 TA = - 40 °C TA = + 85 °C TA = + 25 °C V DO (mV) 180 SiP21106: 2.8 V 160 IOUT = 150 mA 140 120 100 IOUT = 100 mA 80 60 2.0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 6.0 IOUT (mA) Dropout Voltage vs. Load Current Dropout Voltage vs. Input Voltage 180 160 I OUT = 150 mA 140 V DO (mV) 120 100 80 60 40 SiP21106: 2.8 V 20 I OUT = 100 mA 41 40 39 38 37 36 I OUT = 50 mA 35 SiP21106: 2.8 V 34 - 15 10 35 60 85 - 40 - 15 10 35 60 85 Temperature (°C) Temperature (°C) I OUT = 1 mA I OUT = 150 mA - 40 Dropout Voltage vs. Temperature Ground Current vs. Temperature www.vishay.com 8 Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 SiP21106, SiP21107, SiP21108 Vishay Siliconix TYPICAL CHARACTERISTICS 50 VIN = 5.5 V 45 VIN = 3.8 V I GND (µA) I GND (µA) 50 IOUT = 150 mA 40 40 30 IOUT = 1 mA 35 20 30 SiP21106: 2.8 V 25 0 25 50 75 I OUT (mA) 100 125 150 10 SiP21106: 2.8 V 0 0 1 2 3 VIN (V) 4 5 6 Ground Current vs. Output Current Ground Current vs. Input Voltage at 25 °C 80 70 60 PSRR (dB) 50 40 30 20 10 0 10 100 1000 10 000 100 000 1 000 000 V OUT (V) SiP21106 C BP = 10 nF I OUT = 10 mA 2.820 SiP21106: 2.8 V VIN = 3.8 V 2.800 IOUT = 1 mA 2.780 IOUT = 50 mA 2.760 IOUT = 150 mA 2.740 2.720 - 40 - 15 10 35 60 85 Temperature (°C) Frequency (Hz) PSRR Output Voltage Accuracy vs. Load Current 400 SiP21106: 2.8 V 350 300 Output Noise (µV) 250 200 150 100 50 0 0.001 0.0056 0.01 0.056 0.1 BP Capacitance (µF) Output Noise vs. BP Capacitance Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 www.vishay.com 9 SiP21106, SiP21107, SiP21108 Vishay Siliconix TYPICAL OPERATING WAVEFORMS IOUT (100 mA/DIV) IOUT (100 mA/DIV) VOUT (50 mV/DIV) SiP21106: 4.6 V VIN = 5.5 V VOUT = 4.6 V CIN = 1 µF COUT = 1 µF CBP = 10 nF VOUT (50 mV/DIV) SiP21106: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 µF COUT = 1 µF CBP = 10 nF 50 µs/DIV Load Transient Response 50 µs/DIV Load Transient Response SiP21106: 4.6 V VIN = 5.0 to 5.5 V VOUT = 4.6 V IOUT = 150 mA CIN = 1 µF COUT = 1 µF CBP = 10 nF AC Coupling VIN (200 mV/DIV) SiP21106: 2.8 V VIN = 3.8 to 4.8 V VOUT = 2.8 V IOUT = 150 mA CIN = 1 µF COUT = 1 µF CBP = 10 nF VIN (1 V/DIV) AC Coupling VOUT (10 mV/DIV) VOUT (10 mV/DIV) 200 µs/DIV Line Transient Response 200 µs/DIV Line Transient Response SiP21106: 2.8 V VIN = 3.8 to 4.8 V VOUT = 2.8 V IOUT = 1 mA CIN = 1 µF COUT = 1 µF CBP = 10 nF VIN (1 V/DIV) AC Coupling SiP21106: 4.6 V VIN = 5.0 to 5.5 V VOUT = 4.6 V IOUT = 1 mA CIN = 1 µF COUT = 1 µF CBP = 10 nF AC Coupling VIN (200 mV/DIV) VOUT (10 mV/DIV) VOUT (10 mV/DIV) 200 µs/DIV Line Transient Response www.vishay.com 10 200 µs/DIV Line Transient Response Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 SiP21106, SiP21107, SiP21108 Vishay Siliconix TYPICAL OPERATING WAVEFORMS SiP21106: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 µF COUT = 1 µF CBP = 10 nF SiP21106: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 µF COUT = 1 µF CBP = 10 nF IOUT (100 mA/DIV) IOUT (50 mA/DIV) 50 ms/DIV Output Short Circuit Current 50 ms/DIV Output Short Thermal Cycling SiP21106: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 µF COUT = 1 µF CBP = 10 nF IOUT = 150 mA VEN (500 mV/DIV) VEN (1 V/DIV) SiP21106: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 µF COUT = 1 µF CBP = 10 nF IOUT = 150 mA VOUT (500 mV/DIV) VOUT (500 mV/DIV) 20 µs/DIV Output Voltage Power-Down 20 µs/DIV Output Voltage Start-Up VOUT (500 mV/DIV) SiP21107: 1.8 V VIN = 2.8 V VOUT = 1.8 V CIN = 1 µF COUT = 1 µF CBP = 10 nF IOUT = 1 mA VOUT (500 mV/DIV) POK (1 V/DIV) POK (1 V/DIV) SiP21107: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 µF COUT = 1 µF CBP = 10 nF IOUT = 1 mA 20 ms/DIV POK pin goes low to indicate output under-voltage fault condition 20 ms/DIV POK pin goes low to indicate output under-voltage fault condition Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 www.vishay.com 11 SiP21106, SiP21107, SiP21108 Vishay Siliconix TYPICAL OPERATING WAVEFORMS SiP21107: 1.8 V VIN = 2.8 V VOUT = 1.8 V CIN = 1 µF COUT = 1 µF CBP = 10 nF IOUT = 1 mA VOUT (500 mV/DIV) VOUT (500 mV/DIV) SiP21107: 2.8 V POK (1 V/DIV) VOUT = 2.8 V CIN = 1 µF COUT = 1 µF CBP = 10 nF IOUT = 1 mA VIN = 3.8 V POK (1 V/DIV) 20 µs/DIV POK pin is actively high to indicate an output normal operation condition on regular 20 µs/DIV POK pin is actively high to indicate an output normal operation condition on regular TYPICAL WAVEFORMS 1 Noise Spectral Density (µV/√Hz) 0.1 SiP21106: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 µF COUT = 1 µF CBP = 10 nF IOUT = 100 mA VOUT (100 µV/DIV) VNOISE = 60 µVRMS SiP21106: 2.8 V VIN = 4.5 V VOUT = 2.8 V CIN = 1 µF COUT = 1 µF CBP = 10 nF IOUT = 150 mA 0.01 10 100 1K 10K 100K 1M Frequency (Hz) 2 ms/DIV Output Noise Output Noise Spectral Density FUNCTIONAL BLOCK DIAGRAM VIN EN Enable Error-Amp Bandgap Reference Current Limit and Thermal VOUT * ** *** BP/Adj/POK + POK - 0.94 VOUT SiP21106: BP SiP21107: POK SiP21108: Adj * SiP21106: BP *** SiP21107: POK ** SiP21108: Adj GND Figure 3. www.vishay.com 12 Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 SiP21106, SiP21107, SiP21108 Vishay Siliconix DETAILED DESCRIPTION As shown in the block diagram, the circuit consists of a bandgap reference, error amplifier, P-channel pass transistor and an internal feedback resistor voltage divider, which is used to monitor and control the output voltage. A constant 1.2 V bandgap reference voltage is applied to the non-inverting input of the error amplifier. The error amplifier compares this reference with the feedback voltage on its inverting input and amplifies the difference. If the feedback voltage is lower than the reference voltage, the pass-transistor gate is pulled low. This increases the PMOS's gate to source voltage and allows more current to pass through the transistor to the output which increases the output voltage. Conversely, if the feedback voltage is higher than the reference voltage, the pass transistor gate is pulled high, decreasing the gate-to-source voltage, thereby allowing less current to pass to the output and causing it to drop. Internal P-Channel Pass Transistor A 0.9 Ω (typical) P-channel MOSFET is used as the pass transistor for the SiP21106, SiP21107, SiP21108 part series. The MOSFET transistor offers many advantages over the more, formerly, common PNP pass transistor designs, which ultimately result in longer battery lifetime. The main disadvantage of PNP pass transistors is that they require a certain base current to stay on, which significantly increases under heavy load conditions. In addition, during dropout, when the pass transistor saturates, the PNP regulators waste considerable current. In contrast, P-channel MOSFETS require virtually zero-base drive and do not suffer from the stated problems. These savings in base drive current translate to lower quiescent current which is typical around 35 µA as shown in the Typical Characteristics. Shutdown and Auto-Dischage/No-Discharge Bringing the EN voltage low will place the part in shutdown mode where the device output enters a high-impedance state and the quiescent current is reduced to below 1 µA, reducing the drain on the battery in standby mode and increasing standby time. Connect EN pin to input for normal operation. The output has an internal pull down to discharge the output to ground when the EN pin is low. The internal pull down is a 100 Ω typical resistor, which can discharge a 1 µF in less than 1 ms. Refer to Typical Operating Waveforms for turn-off waveforms. Output Voltage Selection The SiP21106 has fixed voltage outputs that are preset to voltages from 1.2 V to 4.6 V (see Ordering Information). VIN 1.2 V Reference + Error-Amp - VOUT R1 R2 Figure 4. The SiP21108 has a user-adjustable output that can be set through the resistor feedback network consisting of R1 and R2. R2 range of 100K to 400K is recommended to be consistent with ground current specification. R1 can then be determined by the following equation: R1 = R 2 x ( VOUT Vref - 1) Where Vref is typically 1.2005 V. Use 1 % or better resistors for better output voltage accuracy (see Figure 4). Current Limit The SiP21106, SiP21107, SiP21108 include a current limit block which monitors the current passing through the pass transistor through a current mirror and controls the gate voltage of the MOSFET, limiting the output current to 330 mA (typical). This current limit feature allows for the output to be shorted to ground for an indefinite amount of time without damaging the device. Thermal-Overload Protection The thermal overload protection limits the total power dissipation and protects the device from being damaged. When the junction temperature exceeds TJ = 150 °C, the device turns the P-channel pass transistor off allowing the device to cool down. Once the temperature drops by about 20 °C, the thermal sensor turns the pass transistor on again and resumes normal operation. Consequently, a continuous thermal overload condition will result in a pulsed output. It is generally recommended to not exceed the junction temperature rating of 125 °C for continuous operation. Noise Reduction in SiP21106 For the SiP21106, an external 10 nF bypass capacitor at BP pin is used to create a low pass filter for noise reduction. The startup time is fast, since a power-on circuit pre-charges the bypass capacitor. After the power-up sequence the pre-charge circuit is switched to standby mode in order to save current. It is therefore not recommended to use larger bypass capacitor values than 50 nF. When the circuit is used without a capacitor, stable operation is guaranteed. Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 www.vishay.com 13 SiP21106, SiP21107, SiP21108 Vishay Siliconix POK Status in SiP21107 The POK comparator monitors the output until the supply comes up to specified percentage of VIN. This open drain NMOS output requires an external pull-up resistor to either VOUT or VIN. The internal NMOS can drive up to 0.5 mA loads. POK pin is active high to indicate that output is within percentage tolerance. POK goes low when output is outside of this tolerance as when in dropout, over current and thermal shutdown. The GND pin of the SiP2110 acts as both the electrical connection to GND as well as a path for channeling away heat. Connect this pin to a GND plane to maximize heat dissipation. Once maximum power dissipation is calculated using the equation above, the maximum allowable output current for any input/output potential can be calculated as IOUT(max) = P (max) VIN - VOUT APPLICATION INFORMATION Input/Output Capacitor Selection and Regulator Stability It is recommended that a low ESR 1 µF capacitor be used on the SiP21106, SiP21107, SiP21108 input. A larger input capacitance with lower ESR would improve noise rejection and line-transient response. A larger input bypass capacitor may be required in applications involving long inductive traces between the source and LDO. The circuit is stable with only a small output capacitor equal to 6 nF/mA (≈ 1 µF at 150 mA) of load. Since the bandwidth of the error amplifier is around 1 MHz - 3 MHz and the dominant pole is at the output node, the capacitor should be capacitive in this range, i.e., for 150 mA load current, an ESR < 0.4 Ω is necessary. Parasitic inductance of about 10 nH can be tolerated. Applying a larger output capacitor would increase power supply rejection and improve load-transient response. Some ceramic dielectrics such as the Z5U and Y5V exhibit large capacitance and ESR variation over temperature. If such capacitors are used, a 2.2 µF or larger value may be needed to ensure stability over the industrial temperature range. If using higher quality ceramic capacitors, such as those with X7R and Y7R dielectrics, a 1 µF capacitor will be sufficient at all operating temperatures. Operating Region and Power Dissipation An important consideration when designing power supplies is the maximum allowable power dissipation of a part. The maximum power dissipation in any application is dependant on the maximum junction temperature, TJ(max) = 125 °C, the ambient temperature, TA, and the junction-to-ambient thermal resistance for the package, which is the summation of θJ-C, the thermal resistance of the package, and θC-A, the thermal resistance through the PC board and copper traces. Power dissipation may be expressed as: PCB Layout The component placement around the LDO should be done carefully to achieve good dynamic line and load response. The input and noise capacitor should be kept close to the LDO. The rise in junction temperature depends on how efficiently the heat is carried away from junction-to-ambient. The junction-to-lead thermal impedance is a characteristic of the package and is fixed. The thermal impedance between lead-to-ambient can be reduced by increasing the copper area on PCB. Increase the input, output and ground trace area to reduce the junction-to-ambient thermal impedance. P(max) = TJ (max) - TA θ J-C + θ C-A Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?74442. www.vishay.com 14 Document Number: 74442 S09-1047-Rev. G, 08-Jun-09 Package Information Vishay Siliconix THIN SOT-23 : 5- AND 6-LEAD (POWER IC ONLY) e1 e1 5 4 6 5 4 E1 E E1 E 1 2 3 −B− 1 2 3 − B− e b 0.15 M CB A e b 0.15 M C B A SOT23-5L Format −A− SOT23-6L Format 4xq1 0.17 Ref D C R A2 A R Seating Plane Q 4xq1 L (L1) L 2 Gauge Plane Seating Plane 0.08 C −C− A1 MILLIMETERS Dim A A1 A2 b c D E E1 e e1 L L1 L2 R Q Q1 Min 0.91 0.01 0.90 0.30 0.10 2.90 2.70 1.525 1.80 0.30 INCHES Min 0.036 0.0004 0.035 0.012 0.004 0.114 0.106 0.060 0.070 0.012 Nom 1.00 0.05 0.95 0.32 0.15 3.05 2.85 1.65 0.95 BSC 1.90 0.40 0.60 REF 0.25 BSC Max 1.10 0.10 1.00 0.45 0.20 3.10 2.98 1.70 2.00 0.60 Nom 0.039 0.002 0.037 0.013 0.006 0.120 0.112 0.065 0.0374 BSC 0.075 0.016 0.024 REF 0.010 BSC Max 0.043 0.004 0.039 0.018 0.008 0.122 0.117 0.067 0.080 0.024 0.10 0_ 4_ − 4_ 10_ NOM − 8_ 12_ 0.004 0_ 4_ − 4_ 10_ NOM − 8_ 12_ ECN: S-40083—Rev. A, 02-Feb-04 DWG: 5926 Document Number: 72821 29-Jan-04 www.vishay.com 1 Package Information Vishay Siliconix SC-70: 3/4/5/6-LEADS (PIC ONLY) D e1 D N5 N4 N3 0.15 (0.006) C A A E/2 E1/2 E/1 E 0.15 (0.006) C Pin 1 N1 e N2 B See Detail A C 0.10 (0.004) M C A B b U1 A2 A SEATING PLANE A1 C 0.10 (0.004) C (b) b1 0.15 (0.0059) H GAGE PLANE c1 Base Metal SECTIION A-A c L DETAIL A U Pin Code N1 N2 N3 N4 N5 LEAD COUNT 3 − 2 − 3 − NOTES: 4 − 2 3 − 4 5 2 3 4 − 5 6 2 3 4 5 6 1. 2. 3. Dimensioning and tolerancing per ANSI Y14.5M-1994. Controlling dimensions: millimeters converted to inch dimensions are not necessarily exact. Dimension “D” does not include mold flash, protrusion or gate burr. Mold flash, protrusion or gate burr shall not exceed 0.15 mm (0.006 inch) per side. The package top shall be smaller than the package bottom. Dimension “D” and “E1” are determined at the outer most extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 4. Document Number: 73201 19-Nov-04 www.vishay.com 1 Package Information Vishay Siliconix MILLIMETERS Dim A A1 A2 b b1 c c1 D E E1 e e1 L U U1 0.26 0_ 4_ INCHES Min 0.031 0.000 0.031 0.006 0.006 0.003 0.003 0.074 0.078 0.045 Min 0.80 0.00 0.80 0.15 0.15 0.08 0.08 1.90 2.00 1.15 Nom − − 0.90 − 0.20 − 0.13 2.10 2.10 1.25 0.65 BSC 1.30 BSC 0.36 − Max 1.10 0.10 1.00 0.30 0.25 0.25 0.20 2.15 2.20 1.35 Nom − − 0.035 − 0.008 − 0.005 0.082 0.082 0.050 0.0255 BSC 0.0512 BSC Max 0.043 0.004 0.040 0.012 0.010 0.010 0.008 0.084 0.086 0.055 0.46 8_ 10_ 0.010 0_ 4_ 0.014 − 0.018 8_ 10_ ECN: S-42145—Rev. A, 22-Nov-04 DWG: 5941 www.vishay.com 2 Document Number: 73201 19-Nov-04 Package Information Vishay Siliconix PowerPAK ® TSC75-6L (Power IC only) D1 Exposed pad e D b Pin4 Pin 5 Pin6 K E PPAK TSC75 (1.6 x 1.6 mm) K L Pin3 K2 Top View Bottom View Pin 2 e1 Pin 1 Dot By Marking K2 Pin1 E1 Exposed pad A C A1 Side View MILLIMETERS DIM A A1 b C D D1 E E1 e e1 K K2 L 0.15 0.20 0.20 Min 0.50 0 0.20 0.10 1.55 0.95 1.55 0.55 Nom 0.55 0.25 0.15 1.60 1.00 1.60 0.60 0.50 BSC 1.00 BSC 0.25 0.30 0.006 0.008 0.008 Max 0.65 0.05 0.30 0.20 1.65 1.05 1.65 0.65 Min 0.020 0 0.008 0.006 0.0061 0.037 0.061 0.022 INCHES Nom 0.022 0.010 0.008 0.063 0.039 0.063 0.024 0.020 BSC 0.039 BSC 0.010 0.012 Max 0.026 0.002 0.012 0.010 0.065 0.041 0.065 0.026 ECN: S-61919-Rev. A, 02-Oct-06 DWG: 5955 Document Number: 74416 02-Oct-06 www.vishay.com 1 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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