VSC6048

VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6048 Features • 8 Fully Integrated Timing Generators for ATE Applications • 10/5ns Delay Range, 10ps Resolution • Fully Digital Interface. No Off-Chip DACs or Trim Components Required • ± 4 LSB Differential Non-Linearity High-Speed Octal Programmable Timing Generator • 100MHz/200MHz Dynamic Reprogram Frequency for Incrementing and Decrementing • Internal or External High-Speed Clock Option • Low Power: 8 Watts, max • Low Cost 160-Pin PQFP Packaging VSC6048 Block Diagram CAL_DAT 6 Register 6 SPAN CAL DAC DAC_WR IN0A Input Interleve IN0B Variable Shift Register Vernier Delay Element Out 0 400MHz Clock 800MHz Clock 3 7 Register Register TEST[0:9] 10 Channel 0 Channel 1 Channel 2 7 Channel 7 DIN ADR[0:2] DCLK SHIFT RCK RCKN BYP FSEL PLLRST PLL Clock Multiplier Unit x8, x16 400MHz Clock Calibration Register 6 CAL_DAT 800MHz Clock G52335-0, Rev. 4.0 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION High-Speed Octal Programmable Timing Generator Data Sheet VSC6048 Functional Description Reference Clock Selection Clock multiplication of x8 or x16 may be selected via the FSEL pin, requiring a reference clock of 100 ±2.5MHz or 50 ±1.25MHz, respectively. For system applications with 800MHz on board clock, the CMU can be bypassed by asserting BYP signal and RCK will accept an external 800MHz clock. In Bypass mode (BYP = 1, RCK = 800MHz) the skew from INX to RCK at the pin is 550ps +/-250ps. Table 1: Reference Clock Selection BYP 0 0 1 X = don’t care. FSEL 0 1 X RCK 100MHz 50MHz 800MHz Mode of Operations There are 6 basic modes of operation. These modes are based on two inputs per channel (INA and INB) that can be interleaved and refire rate. The maximum refire rate for full 10ns span is 100MHz, where the maximum refire rate for 5ns span is 200MHz. The maximum refire rate at the input to the fine vernier must not be sooner than 4 cycles of the high-speed clock (800MHz). Table 2: Suggested Operating Modes Program Rate 200Mbps 100Mbps 200Mbps 100Mbps 200Mbps 100Mbps Interleaved Yes Yes No No No No INA 100MHz 50MHz 200MHz 100MHz Low Low INB 100MHz 50MHz Low Low 200MHz 100MHz TSET[0:9] Range 000 to 1FF 000 to 3FF 000 to 1FF 000 to 3FF 000 to 1FF 000 to 3FF Data Input (INA, INB) There are two interleaved inputs per channel. Each input is capable of running at full rate (200MHz). The input is first retimed off of the internal 400MHz clock generated from the PLL. This means there is a 2.5ns edge placement window that defines the setup time. This also means that the input pulse must span at least one 400MHz clock edge. The inputs are low to high edge sensitive. Figure 1 illustrates an equivalent circuit of the input structure for each channel. Note that the TSET input clock is generated based on the input data. Page 2 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52335-0,Rev.4.0 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6048 Figure 1: Input Interleave INxA High-Speed Octal Programmable Timing Generator D SET Q TSET_CLK D CLR Q D SET Q DATA INxB D SET Q D CLR Q D CLR Q 400MHz RCK PLL 800MHz FSEL BYP Figure 2: Functional Timing Diagram tRATETS TSET[0:9] tSETSU INA INSU INB INH tSETH OUT TSET (0000000000) tPDTG(MIN) OUT TSET (1111111111) tOPW tPDV(SPAN) tPDTG(SPAN) RCK Time Set Input (TSET) This is a 10-bit TTL bus that controls the delay value of the vernier. The 3 MSBs control the 800MHz shift register and the 7 LSBs control the fine delay element. The TSET data is clocked in by a pulse generated from the input data. The setup time of the TSET data is the same as the input signals (INA, INB). The TSET data must be stable by the time the input edge arrives at the input pin and data must then be held stable for at least 3.5ns after the input edge arrives at the pin. G52335-0, Rev. 4.0 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION High-Speed Octal Programmable Timing Generator Figure 3: Fine Vernier Calibration DAC Programming One Test/Calibration Cycle Shift Data Into Calibration Register SHIFT 1 DCLK 2 3 4 5 6 1 2 3 4 5 6 Hold Data In Calibration Register Data Sheet VSC6048 DIN 5 4 3 2 1 0 X X X X X 5 4 3 2 1 0 X X X X DAC_WR CAL_DAT (internal) ADR[2:0] Vernier 0 DAC Data Vernier 1 DAC Data Address for Vernier 0 Address for Vernier 1 DAC Calibration Each fine vernier must be calibrated to a 1240ps span, one step (10ps) shorter than the 800MHz period (1.25ns). This is accomplished by setting the fine vernier to maximum delay and adjusting the 6-bit calibration DAC until the desired range has been achieved. The calibration data is transferred into the device through a 3-bit serial interface. Refer to Figure 3 for the programming sequence. Typical DCLK frequencies are 1MHz to 10MHz. Once the calibration value has been transferred into the device, the data is written into the specified DAC by the rising edge of DCLK when DAC_WR is HIGH. The address lines must remain stable from the enable of SHIFT to one cycle after the disable of DAC_WR. DAC Application There are three DAC_REF pins on this device. Each pin supplies the reference for two or three calibration DACs. In order to reduce crosstalk between verniers through the DAC_REF supply, it is recommended that each DAC_REF pin be isolated from each other. This will reduce crosstalk between the the three channel groups, however, it will not effect crosstalk between verniers within each group. Table 3: DAC Reference Pin Identification DAC_REF Pin # 1 18 40 Vernier Channels 0, 1, 2 3, 4 5, 6, 7 Outputs Each channel has a differential ECL output. The output of the verniers is falling edge active. The shift register propagates a 2ns pulse. The fine vernier then stretches the pulse width based on the programmed delay. Page 4 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52335-0,Rev.4.0 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6048 DC Characteristics Table 4: Single Ended ECL Inputs and Outputs Parameter VOH VOL VIH VIL IIH IIL High-Speed Octal Programmable Timing Generator Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Min -1020 -2000 -1165 -2000 -50 Typ - Max -700 -1620 -700 -1475 200 - Units mV mV mV mV uA uA Conditions VIN = VIH (max) VIN = VIL (min) NOTE: VTT = -2.0V ± 5%, VCC = VCCA = GND, RLOAD = 50Ω to -2.0V. Table 5: Differential ECL Inputs and Outputs Parameter VDIFF VCM Description Input Voltage Differential Min 200 Typ - Max - Units mV Conditions Required for full output swing Common-mode range required for full output swing with VDIFF applied Common-Mode Voltage -1.5 - -0.5 V Figure 4: Differential ECL Input Voltages Pad PadN VDIFF/2 VDIFF/2 VCM G52335-0, Rev. 4.0 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION High-Speed Octal Programmable Timing Generator Table 6: TTL Inputs and Outputs Parameter VOH VOL VIH VIL IIH IIL IOZH IOZL IOZLB IOCZ Data Sheet VSC6048 Min 2.4 0 2.0 0 -500 -100 -600 - Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Tri-State Output OFF Current HIGH Tri-State Output OFF Current LOW Tri-State Output OFF Current Low for Bi-directs Open Collector Output Leakage Current Typ - Max 0.4 VTTL+1.0V 0.8 50 200 200 Units V V V V µA µA µA µA µA µA Conditions IOH = -2.4mA IOL = 16 mA VIN = 2.4V VIN = 0.4V VOUT = 2.4V VOUT = 0.4V VOUT = 0.4V VOUT = 2.4V NOTE: All specifications are over recommended commercial operating conditions, TTL/GND = GND. Table 7: Power Supply Requirements Parameter ITT IDACREF ITTL Description Power Supply Current from VTT Power Supply Current from VDACREF Power Supply Current from VTTL Min Typ Max 3.4 80 250 8 Units mA mA mA W Conditions PD Power Dissipation(1) NOTE: (1) Output power dissipation does not include load power. Page 6 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52335-0,Rev.4.0 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6048 Table 8: AC Characteristics Parameter tRATE IN tRATE TS tRATE TS tRES tSPAN High-Speed Octal Programmable Timing Generator Description INA and INB Reprogram Rate TSET Reprogram Rate, 200MHz Application TSET Reprogram Rate, 100MHz Application Nominal Resolution (tPDV(SPAN)/ 127) Propagation Delay, 200MHz Application Full TG Span (TSET = 0011111111) After Vernier Span DAC Calibration Propagation Delay, 100MHz Application Full TG Span (TSET = 1111111111) After Vernier Span DAC Calibration Propagation Delay Vernier Delay Element Span (TSET=0001111111) After Vernier Span DAC Calibration Propagation Delay TG Minimum Delay (TSET=000000000) Propagation Delay Vernier Delay Element Zero Delay Integral Non-Linearity Dynamic on-the-fly TSET Switching Differential Non-Linearity Dynamic on-the-fly TSET Switching Variation in Delay vs. Duty Cycle and Frequency Full TG Span (TSET=1111111111) Variation in Delay vs. Temperature Full TG Span (TSET=1111111111) Variation in Delay vs. Supply Voltage Full TG Span (TSET=1111111111) Random Output Signal Jitter Calibration DAC Resolution Width of the Output Pulse Output Rise/Fall Times (20% to 80%) IN0 - IN7 to REF_CLK Setup(1) IN0 - IN7 to REF_CLK Hold(1) TSET [0:9] Setup with Respect to IN TSET [0:9] Hold with Respect to IN IN0 - IN7 Pulse Width Min 5 5 10 Typ Max Units ns ns ns 10 4980 4990 ps ps tPDTG(SPAN) 9980 9990 ps tPDV(SPAN) tPDTG(MIN) tPDV(MIN) INL DNL DCV DTCO PSRR OSJ DACRES tOPW tR/tF INSU INH tSETSU tSETH INPW 1230 11.0 1300 -4 -4 -40 -6 -8 1240 14.0 1700 +4 +4 +40 +6 +8 10 25 ps ns ps LSBs LSBs ps ps/°C ps/100mV ps rms ps 2500 ps ps 1250 ps ps ps ps ns 800 300 250 1750 250 3500 2 NOTE: (1) The rising edge of the input (INA, INB) must fall in the setup region defined from 250ps to 1250ps before the rising edge of the reference clock (RCK, RCKN). G52335-0, Rev. 4.0 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION High-Speed Octal Programmable Timing Generator Data Sheet VSC6048 Absolute Maximum Ratings(1) Power Supply Voltage (VTT) ..........................................................................................................-2.5V to +0.5V Power Supply Voltage (VDACREF) .................................................................................................-0.5V to +4.3V Power Supply Voltage (VTTL) ........................................................................................................-0.5V to +4.3V ECL Input Voltage Applied, (VIN ECL) ................................................................................+0.5V to VTT + -0.5V TTL Input Voltage Applied, (VIN TTL)................................................................................. -0.5V to VTTL + 1.0V Output Current (IOUT) ................................................................................................................................... 50mA Case Temperature Under Bias (TC)............................................................................................. -55oC to + 125oC Storage Temperature (TSTG)........................................................................................................ -65oC to + 150oC Recommended Operating Conditions Power Supply Voltage (VTT) ..................................................................................................................-2.0V ± 5 % Power Supply Voltage (VDACREF) ........................................................................................................ +3.0V ± 5 % Power Supply Voltage (VTTL) ............................................................................................................... +3.3V ± 5 % Commercial Operating Temperature Range(2) (T) .............................................................................. 0oC to 70oC NOTES: (1) Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. (2) Lower limit of specification is ambient temperature and upper limit is case temperature. ESD Ratings Proper ESD procedures should be used when handling this product. The VSC6048 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V. Page 8 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52335-0,Rev.4.0 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6048 Package Pin Description Figure 5: Pin Diagram High-Speed Octal Programmable Timing Generator DAC_REF VCC TSET35 TSET36 TSET37 TSET38 TSET39 VTT IN0A IN0B IN1A IN1B IN2A IN2B IN3A IN3B VCC DAC_REF VPLL VGND RCK RCKN VCC VGND VPLL VTT IN4A IN4B IN5A IN5B IN6A IN6B IN7A IN7B VCC TSET40 TSET41 TSET42 VTT DAC_REF 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 TSET34 TSET33 TSET32 TSET31 TSET30 VTT TSET29 TSET28 TSET27 TSET26 TSET25 TSET24 TSET23 VCC TSET22 TSET21 TSET20 TSET19 TSET18 TSET17 VTT TSET16 TSET15 TSET14 TSET13 TSET12 TSET11 TSET10 VTTL TSET09 TSET08 TSET07 TSET06 TSET05 TSET04 TSET03 TSET02 TSET01 VCC VTT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VITESSE VSC6048 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 TSET00 VCC BYP FSEL ADR2 ADR1 ADR0 OUT0N OUT0 VCC OUT1N OUT1 VTT OUT2N OUT2 VCC OUT3N OUT3 NC OUT4N OUT4 VTT OUT5N OUT5 VTT OUT6N OUT6 VTT OUT7N OUT7 DCLK SHIFT VCC DAC_WR PLLRST DIN VCC TSET79 TSET78 TSET77 TSET43 TSET44 TSET45 TSET46 TSET47 TSET48 TSET49 TSET50 VCC TSET51 TSET52 TSET53 TSET54 TSET55 TSET56 TSET57 VTT TSET58 TSET59 TSET60 TSET61 TSET62 TSET63 VCC TSET64 TSET65 TSET66 TSET67 TSET68 TSET69 TSET70 VTTL TSET71 TSET72 TSET73 TSET74 TSET75 TEST76 VTT VCC 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 G52335-0, Rev. 4.0 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION High-Speed Octal Programmable Timing Generator Table 9: Pin Identifications Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Data Sheet VSC6048 Signal Name DAC_REF VCC TSET35 TSET36 TSET37 TSET38 TSET39 VTT IN0A IN0B IN1A IN1B IN2A IN2B IN3A IN3B VCC DAC_REF VPLL VGND RCK RCKN VCC VGND VPLL VTT IN4A IN4B IN5A IN5B IN6A IN6B IN7A IN7B VCC TSET40 TSET41 Signal Type — — TTL TTL TTL TTL TTL — ECL ECL ECL ECL ECL ECL ECL ECL — — — — ECL ECL — — — — ECL ECL ECL ECL ECL ECL ECL ECL — TTL TTL Levels +3.0V 0V I I I I I -2.0V I I I I I I I I 0V +3.0V -2.0V 0V I I 0V 0V -2.0V -2.0V I I I I I I I I 0V I I Ground Description DAC Reference Supply Timeset Data for Channel 3, Bit 5 Timeset Data for Channel 3, Bit 6 Timeset Data for Channel 3, Bit 7 Timeset Data for Channel 3, Bit 8 Timeset Data for Channel 3, Bit 9 Power Supply Channel 0, Input A Channel 0, Input B Channel 1, Input A Channel 1, Input B Channel 2, Input A Channel 2, Input B Channel 3, Input A Channel 3, Input B Ground DAC Reference Supply PLL Power Supply PLL Ground PLL Reference Clock PLL Reference Clock, Complementary Ground PLL Ground PLL Power Supply Power Supply Channel 4, Input A Channel 4, Input B Channel 5, Input A Channel 5, Input B Channel 6, Input A Channel 6, Input B Channel 7, Input A Channel 7, Input B Ground Timeset Data for Channel 4, Bit 0 Timeset Data for Channel 4, Bit 1 Page 10 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52335-0,Rev.4.0 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6048 Pin # 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 High-Speed Octal Programmable Timing Generator Signal Name TSET42 VTT DAC_REF TSET43 TSET44 TSET45 TSET46 TSET47 TSET48 TSET49 TSET50 VCC TSET51 TSET52 TSET53 TSET54 TSET55 TSET56 TSET57 VTT TSET58 TSET59 TSET60 TSET61 TSET62 TSET63 VCC TSET64 TSET65 TSET66 TSET67 TSET68 TSET69 TSET70 VTTL TSET71 TSET72 TSET73 Signal Type TTL — — TTL TTL TTL TTL TTL TTL TTL TTL — TTL TTL TTL TTL TTL TTL TTL — TTL TTL TTL TTL TTL TTL — TTL TTL TTL TTL TTL TTL TTL — TTL TTL TTL Levels I -2.0V +3.0V I I I I I I I I 0V I I I I I I I -2.0V I I I I I I 0V I I I I I I I +3.3V I I I Power Supply Description Timeset Data for Channel 4, Bit 2 DAC Reference Supply, +3.0V Timeset Data for Channel 4, Bit 3 Timeset Data for Channel 4, Bit 4 Timeset Data for Channel 4, Bit 5 Timeset Data for Channel 4, Bit 6 Timeset Data for Channel 4, Bit 7 Timeset Data for Channel 4, Bit 8 Timeset Data for Channel 4, Bit 9 Timeset Data for Channel 5, Bit 0 Ground Timeset Data for Channel 5, Bit 1 Timeset Data for Channel 5, Bit 2 Timeset Data for Channel 5, Bit 3 Timeset Data for Channel 5, Bit 4 Timeset Data for Channel 5, Bit 5 Timeset Data for Channel 5, Bit 6 Timeset Data for Channel 5, Bit 7 Power Supply Timeset Data for Channel 5, Bit 8 Timeset Data for Channel 5, Bit 9 Timeset Data for Channel 6, Bit 0 Timeset Data for Channel 6, Bit 1 Timeset Data for Channel 6, Bit 2 Timeset Data for Channel 6, Bit 3 Ground Timeset Data for Channel 6, Bit 4 Timeset Data for Channel 6, Bit 5 Timeset Data for Channel 6, Bit 6 Timeset Data for Channel 6, Bit 7 Timeset Data for Channel 6, Bit 8 Timeset Data for Channel 6, Bit 9 Timeset Data for Channel 7, Bit 0 TTL Power Supply Timeset Data for Channel 7, Bit 1 Timeset Data for Channel 7, Bit 2 Timeset Data for Channel 7, Bit 3 G52335-0, Rev. 4.0 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION High-Speed Octal Programmable Timing Generator Pin # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Data Sheet VSC6048 Levels I I I -2.0V 0V I I I 0V I I I 0V I I O O -2.0V O O 0V O O -2.0V O O — O O 0V O O -2.0V Signal Name TSET74 TSET75 TSET76 VTT VCC TSET77 TSET78 TSET79 VCC DIN PLLRST DAC_WR VCC SHIFT DCLK OUT7 OUT7N VTT OUT6 OUT6N VCC OUT5 OUT5N VTT OUT4 OUT4N NC OUT3 OUT3N VCC OUT2 OUT2N VTT Signal Type TTL TTL TTL — — TTL TTL TTL — TTL TTL TTL — TTL TTL ECL ECL — ECL ECL — ECL ECL — ECL ECL — ECL ECL — ECL ECL — Description Timeset Data for Channel 7, Bit 4 Timeset Data for Channel 7, Bit 5 Timeset Data for Channel 7, Bit 6 Power Supply Ground Timeset data for Channel 7, Bit 7 Timeset data for Channel 7, Bit 8 Timeset data for Channel 7, Bit 9 Ground Serial Calibration Data for Vernier Delay Setting Resets PLL Feedback Counter Write Pulse for DAC Register Ground Enables Shift of Data in the Calibration Register Clock for Serial Data Shift for Calibration Register Delayed Signal Output Channel 7 Delayed Signal Output Channel 7, Complementary Power Supply Delayed Signal Output Channel 6 Delayed Signal Output Channel 6, Complementary Ground Delayed Signal Output Channel 5 Delayed Signal Output Channel 5 Complementary Power Supply Delayed Signal Output Channel 4 Delayed Signal Output Channel 4, Complementary Not Connected Delayed Signal Output Channel 3 Delayed Signal Output Channel 3, Complementary Ground, 0V Delayed Signal Output Channel 2 Delayed Signal Output Channel 2, Complementary Power Supply Page 12 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52335-0,Rev.4.0 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6048 Pin # 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 High-Speed Octal Programmable Timing Generator Signal Name OUT1 OUT1N VCC OUT0 OUT0N ADR0 ADR1 ADR2 FSEL BYP VCC TSET00 VTT VCC TSET01 TSET02 TSET03 TSET04 TSET05 TSET06 TSET07 TSET08 TSET09 VTTL TSET10 TSET11 TSET12 TSET13 TSET14 TSET15 TSET16 VTT TSET17 TSET18 TSET19 TSET20 TSET21 TSET22 VCC Signal Type ECL ECL — ECL ECL TTL TTL TTL TTL TTL — TTL — — TTL TTL TTL TTL TTL TTL TTL TTL TTL — TTL TTL TTL TTL TTL TTL TTL — TTL TTL TTL TTL TTL TTL — Levels O O 0V O O I I I I I 0V I -2.0V 0V I I I I I I I I I +3.3V I I I I I I I -2.0V I I I I I I 0V Description Delayed Signal Output Channel 1 Delayed Signal Output Channel 1 Complementary Ground Delayed Signal Output Channel 0 Delayed Signal Output Channel 0, Complementary Address Bit 0 for Vernier Calibration Address Bit 1 for Vernier Calibration Address Bit 2 for Vernier Calibration Selects Reference Clock Frequency PLL Bypass Mode Ground Timeset Data for Channel 0, Bit 0 Power Supply Ground Timeset Data for Channel 0, Bit 1 Timeset Data for Channel 0, Bit 2 Timeset Data for Channel 0, Bit 3 Timeset Data for Channel 0, Bit 4 Timeset Data for Channel 0, Bit 5 Timeset Data for Channel 0, Bit 6 Timeset Data for Channel 0, Bit 7 Timeset Data for Channel 0, Bit 8 Timeset Data for Channel 0, Bit 9 TTL Power Supply Timeset Data for Channel 1, Bit 0 Timeset Data for Channel 1, Bit 1 Timeset Data for Channel 1, Bit 2 Timeset Data for Channel 1, Bit 3 Timeset Data for Channel 1, Bit 4 Timeset Data for Channel 1, Bit 5 Timeset Data for Channel 1, Bit 6 Power Supply Timeset Data for Channel 1, Bit 7 Timeset Data for Channel 1, Bit 8 Timeset Data for Channel 1, Bit 9 Timeset Data for Channel 2, Bit 0 Timeset Data for Channel 2, Bit 1 Timeset Data for Channel 2, Bit 2 Ground, G52335-0, Rev. 4.0 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION High-Speed Octal Programmable Timing Generator Pin # 148 149 150 151 152 153 154 155 156 157 158 159 160 2, 17, 23, 35, 49, 64 80, 84, 88, 96, 105, 111, 119, 122, 147 8, 26, 39, 57, 79, 93, 99, 108, 121, 140, 155 72, 132 19, 25 20, 24 1, 18, 40 Data Sheet VSC6048 Levels I I I I I I I -2.0V I I I I I Signal Name TSET23 TSET24 TSET25 TSET26 TSET27 TSET28 TSET29 VTT TSET30 TSET31 TSET32 TSET33 TSET34 Signal Type TTL TTL TTL TTL TTL TTL TTL — TTL TTL TTL TTL TTL Description Timeset Data for Channel 2, Bit 3 Timeset Data for Channel 2, Bit 4 Timeset Data for Channel 2, Bit 5 Timeset Data for Channel 2, Bit 6 Timeset Data for Channel 2, Bit 7 Timeset Data for Channel 2, Bit 8 Timeset Data for Channel 2, Bit 9 Power Supply Timeset Data for Channel 3, Bit 0 Timeset Data for Channel 3, Bit 1 Timeset Data for Channel 3, Bit 2 Timeset Data for Channel 3, Bit 3 Timeset Data for Channel 3, Bit 4 Ground and Power Supply Pins VCC VTT VTTL VPLL VGND DAC_REF Page 14 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52335-0,Rev.4.0 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6048 Package Information High-Speed Octal Programmable Timing Generator The VSC6048 is packaged in a thermally-enhanced 160-pin PQFP with an embedded heat sink. SYMBOL E D AMAX A1 A2 e b1 c1 Dimensions in Millimeters Min 27.9 27.9 Nom 28 28 0.35 3.35 0.65 0.3 0.15 0.8 1.6 0.8 31.2 31.2 15 15 0.2 0.2 Max 28.1 28.1 4 3.45 0.4 10 1 NOTES: E, D b1 c1 Excluding the tie bar cutting stub Lead width of basemetal. Lead thickness of basemetal. 3.25 0.2 0 0.6 θ L L1 L2 HE HD 30.8 30.8 31.6 31.6 θ2 θ3 R R1 G52335-0, Rev. 4.0 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION High-Speed Octal Programmable Timing Generator Data Sheet VSC6048 Package Thermal Characteristics The VSC6048 is packaged in an 160-pin, 28x28mm thermally-enhanced PQFP with an internal heat spreader. These packages use industry-standard EIAJ footprints, which have been enhanced to improve thermal dissipation. The construction of the packages are as shown in Figure 6. The VSC6048 is designed to operate with a case temperature up to 70oC. The user must guarantee that the temperature specification is not violated. Figure 6: Package Cross Section Exposed Heat Slug Insulator Plastic Molding Compound Lead Wire Bond Thermal Epoxy Die Table 10: Thermal Resistance Symbol θJC θCA-0 θCA-100 θCA-200 θCA-400 θCA-600 θCA-800 Description Thermal resistance from junction-to-case Thermal resistance from case-to-ambient, still air Thermal resistance from case-to-ambient, 100 LFPM air Thermal resistance from case-to-ambient, 200 LFPM air Thermal resistance from case-to-ambient, 400 LFPM air Thermal resistance from case-to-ambient, 600 LFPM air Thermal resistance from case-to-ambient, 800 LFPM air Value 1.3 16.5 14.1 12.3 10.7 9.3 7.9 Units oC/W oC/W oC/W oC/W oC/W oC/W oC/W Page 16 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52335-0,Rev.4.0 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6048 Ordering Information High-Speed Octal Programmable Timing Generator The order number for this product is formed by a combination of the device number, and package type. VSC6048 Device Type High-Speed Octal Programmable Timing Generator xx Package QV: 160-Pin PQFP, 28x28mm Body Notice This document contains information about a product during its fabrication or early sampling phase of development. The information contained in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to design or order placement. Warning Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. G52335-0, Rev. 4.0 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 17 VITESSE SEMICONDUCTOR CORPORATION High-Speed Octal Programmable Timing Generator Data Sheet VSC6048 Page 18 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52335-0,Rev.4.0 8/28/00