VSC7135QN

VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 Features • Gigabit Ethernet Transceiver @ 1.25Gb/s • Compliant to IEEE 802.3Z PMA • TTL Interface Compatible to PMA-TBI • Monolithic Clock Synthesis and Clock Recovery - No External Components • 125MHz TTL Reference Clock 1.25Gbits/sec Gigabit Ethernet Transceiver • Low Power Operation - 700 mW • Suitable for Both Coaxial or Optical Link Applications • 64 Pin, 14mm or 10mm Standard PQFP • Single +3.3V Supply General Description The VSC7135 is a 1.25Gb/s Ethernet Transceiver optimized for Gigabit Ethernet or 1000Base-X applications. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes it onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency. The VSC7135 also samples serial receive data on the RX PECL differential inputs, recovers the clock and data, deserializes it onto the 10-bit receive data bus, outputs two recovered clocks at one-twentieth of the incoming baud rate and detects “Comma” characters. The VSC7135 contains on-chip PLL circuitry for synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream. These circuits are fully monolithic and require no external components. VSC7135 Block Diagram EWRAP R0:9 10 QD Serial to Parallel ÷ 10 Retimed Data Recovered Clock QD Clock Recovery 2:1 RX+ RX- RCLK RCLKN Frame Logic ÷ 20 Comma Detect Resync COM_DET EN_CDET 10 T0:9 DQ Parallel to Serial Serial Data Synthesized Clock DQ TX+ TX- REFCLK PLL Clock Multiply G52146-0, Rev. 4.0 5/28/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION 1.25Gbits/sec Gigabit Ethernet Transceiver Data Sheet VSC7135 Functional Description Clock Synthesizer The VSC7135 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to achieve a baud rate clock at nominally 1.25GHz. The clock synthesizer contains a fully monolithic PLL which does not require any external components. Serializer The VSC7135 accepts TTL input data as a parallel 10 bit character on the T0:9 bus which is latched into the input latch on the rising edge of REFCLK. This data will be serialized and transmitted on the TX PECL differential outputs at a baud rate of ten times the frequency of the REFCLK input, with bit T0 transmitted first. User data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel specification, or an equivalent, edge rich, DC-balanced code. Transmission Character Interface An encoded byte is 10 bits and is referred to as a transmission character. The 10 bit interface on the VSC7135 corresponds to a transmission character. This mapping is illustrated in Figure 2. Figure 1: Transmission Order and Mapping of an 8B/10B Character Parallel Data Bits 8B/10B Bit Position Comma Character T9 j X T8 h X T7 g X T6 f 1 T5 i 1 T4 e 1 T3 d 1 T2 c 1 T1 b 0 T0 a 0 Last Data Bit Transmitted Clock Recovery First Data Bit Transmitted The VSC7135 accepts differential high speed serial inputs on the RX+/RX- pins, extracts the clock and retimes the data. The serial bit stream should be encoded so as to provide DC balance and limited run length by an 8B/10B transmitter or equivalent. The VSC7135 clock recovery circuitry is completely monolithic and requires no external components. For proper operation, the baud rate of the data stream to be recovered should be within 0.01% of ten times the REFCLK frequency. For example if the REFCLK used is 125MHz, then the incoming serial baud rate must be 1.25 gigabaud +0.01%. Deserializer The retimed serial bit stream is converted into a 10-bit parallel output character. The VSC7135 provides complementary TTL recovered clocks, RCLK and RCLKN, which are at one-twentieth of the serial baud rate. This architecture is designed to simplify demultiplexing of the 10-bit data characters into a 20-bit half-word in the downstream controller chip. The clocks are generated by dividing down the high-speed clock which is phase locked to the serial data. The serial data is retimed by the internal high-speed clock, and deserialized. The result- Page 2 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52146-0, Rev. 4.0 5/28/98 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 1.25Gbits/sec Gigabit Ethernet Transceiver ing parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and RCLKN. In order to maximize the setup and hold times available at this interface, the parallel data is loaded into the output register at a point nominally midway between the transition edges of RCLK and RCLKN. If serial input data is not present, or does not meet the required baud rate, the VSC7135 will continue to produce a recovered clock so that downstream logic may continue to function. The RCLK and RCLKN output frequency under these circumstances may differ from their expected frequency by no more than +1%. Word Alignment The VSC7135 provides 7-bit comma character recognition and data word alignment. Word synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7135 constantly examines the serial data for the presence of the “Comma” character. This pattern is “0011111XXX”, where the leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and K28.7, which are defined specifically for synchronization purposes. Improper alignment of the comma character is defined as any of the following conditions: 1) The comma is not aligned within a the 10-bit transmission character such that T0...T6 = “0011111” 2) The comma straddles the boundary between two 10-bit transmission characters. 3) The comma is properly aligned but occurs in the received character presented during the rising edge of RCLK rather than RCLKN. When EN_CDET is HIGH and an improperly aligned comma is encountered, the internal data is shifted in such a manner that the comma character is aligned properly in R0:9. This results in proper character and halfword alignment. When the parallel data alignment changes in response to a improperly aligned comma pattern, some data which would have been presented on the parallel output port may be lost. However, the synchronization character and subsequent data will be output correctly and properly aligned. When EN_CDET is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern. On encountering a comma character, COM_DET is driven HIGH to inform the user that realignment of the parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the comma character and has a duration equal to the data, or half of an RCLK period. The COM_DET signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of RCLKN. Functional waveforms for synchronization are given in Figure 3 and Figure 4. Figure 3 shows the case when a comma character is detected and no phase adjustment is necessary. It illustrates the position of the COM_DET pulse in relation to the comma character on R0:9. Figure 4 shows the case where the K28.5 is detected, but it is out of phase and a change in the output data alignment is required. Note that up to three characters prior to the comma character may be corrupted by the realignment process. G52146-0, Rev. 4.0 5/28/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION 1.25Gbits/sec Gigabit Ethernet Transceiver Figure 2: Detection of a Properly Aligned Comma Character Data Sheet VSC7135 RCLK RCLKN COM_DET R0:9 K28.5 TChar TChar TChar TChar: 10 bit Transmission Character Figure 3: Detection and Resynchronization of an Improperly Aligned Comma Receiving Two Consecutive K28.5+TChar Transmission Words RCLK RCLKN COM_DET R0:9 Potentially Corrupted K28.5 TChar TChar TChar K28.5 TChar Page 4 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52146-0, Rev. 4.0 5/28/98 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 AC Characteristics Figure 4: Transmit Timing Waveforms 1.25Gbits/sec Gigabit Ethernet Transceiver REFCLK T1 T2 T0:9 10 Bit Data Data Valid Data Valid Data Valid Table 1: Transmit AC Characteristics Parameters T1 T2 TSDR,TSDF TLAT Description T0:9 Setup time to the rising edge of REFCLK T0:9 hold time after the rising edge of REFCLK TX+/TX- rise and fall time Min 1.5 Max — Units ns. Conditions Measured between thevalid data level of T0:9 to the 1.4V point of REFCLK 1.0 — — 300 ns. ps. 20% to 80%, 75 Ohm load to Vss, Tested on a sample basis bc = Bit clocks ns = Nano second Latentcy from rising edge of 11bc - 1ns ns. REFCLK to T0 appearing on TX+/TXTransmitter Output Jitter Allocation Total data output jitter (p-p) Serial data output deterministic jitter (p-p) — — 192 80 ps. ps. TJ TDJ IEEE 802.3Z Clause 38.68, tested on a sample basis IEEE 802.3Z Clause 38.69, tested on a sample basis G52146-0, Rev. 4.0 5/28/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION 1.25Gbits/sec Gigabit Ethernet Transceiver Figure 5: Receive Timing Waveforms T4 T3 Data Sheet VSC7135 RCLK RCLKN T1 T2 Data Valid R0:9 Data Valid Data Valid Table 2: Receive AC Characteristics Parameters T1 Description Data or COM_DET Valid prior to RCLK/RCLKN rise Data or COM_DET Valid after RCLK or RCLKN rise Deviation of RCLK rising edge to RCLKN rising edge delay from nominal. f baud delay = ------------- ± T 3 10 Min. 3.0 Max. — Units ns. Conditions Measured between the 1.4V point of RCLK or RCLKN and a valid level of R0:9. All outputs driving 10pF load. T2 2.0 — ns. T3 -500 500 ps. Nominal delay is 10 bit times. Tested on sample basis T4 Deviation of RCLK, RCLKN frequency from nominal. f REFCLK f RCLK = ---------------------- ± T 4 2 -1.0 1.0 % Whether or not locked to serial data TR, TF Rlat TLOCK Tjtd Djtd R0:9, COM_DET, RCLK, RCLKN rise and fall time Latency from RX to R0:9 Data acquisition lock time @ 1.25 Gb/s Total receive data jitter tolerance (p-p) Total deterministic data jitter tolerance (p-p) — 15bc + 2ns — 2.4 34bc + 2ns 2.0 599 370 ns. µs. ps ps Between Vil(max) and Vih(min), into 10 pf. load. bc = Bit clock ns = Nano second 8B/10B IDLE pattern. Tested on a sample basis IEEE 802.3Z Clause 38.68, tested on a sample basis IEEE 802.3Z Clause 38.69, tested on a sample basis NOTE: Probability of Recovery for data acquisition is 95% per section 5.3 of the FC-PH rev. 4.3. Page 6 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52146-0, Rev. 4.0 5/28/98 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 Figure 6: REFCLK Timing Waveforms 1.25Gbits/sec Gigabit Ethernet Transceiver TL REFCLK TH Vih(min) Vil(max) Table 3: Reference Clock Requirements Parameters Description Min Max Units Conditions Range over which both transmit and receive reference clocks on any link may be centered Maximum frequency offset between transmit and receive reference clocks on one link Measured at 1.5V Between Vil(max) and Vih(min) dbc, RMS for 10-12 Bit Error Ratio with zero length external path. Tested on a sample basis FR Frequency Range 123 127 MHz FO DC TRCR,TRCF REFCLK Jitter Frequency Offset REFCLK duty cycle REFCLK rise and fall time REFCLK Jitter Power 5 MHz -200 200 ppm. 30 — 70 2.0 % ns. ∫ 100 Hz PhaseNoise — 40 ps. G52146-0, Rev. 4.0 5/28/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION 1.25Gbits/sec Gigabit Ethernet Transceiver Data Sheet VSC7135 DC Characteristics (Over recommended operating conditions). Parameters VOH VOL ∆VOUT751 ∆VOUT501 ∆VIN1 Description Output HIGH voltage (TTL) Output LOW voltage (TTL) TX Output differential peakto-peak voltage swing TX Output differential peakto-peak voltage swing Receiver differential peak-topeak Input Sensitivity RX Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Supply voltage Power dissipation Supply Current Min 2.4 — 1200 1200 400 2.0 0 — — 3.14 — — Typ — — — — — — — 50 — — 625 190 Max — 0.5 2200 2200 3200 5.5 0.8 500 -500 3.47 900 260 Units V V mVp-p mVp-p mVp-p V V µA µA V mW mA Conditions IOH = -1.0 mA IOL = +1.0 mA 75Ω to VDD – 2.0 V (TX+ - TX-) 50Ω to VDD – 2.0 V (TX+ - TX-) Internally biased to Vdd/2 (RX+ - RX-) — VIN =2.4V VIN =0.5V 3.3V±5% Outputs open, VDD = VDD max Outputs open, VDD = VDD max VIH VIL IIH IIL VDD PD IDD Note: (1) Refer to Application Note, AN-37, for differential measurement techniques. Absolute Maximum Ratings (1) Power Supply Voltage, (VDD)............................................................................................................ -0.5V to +4V DC Input Voltage (PECL inputs) ............................................................................................ -0.5V to VDD +0.5V DC Input Voltage (TTL inputs)......................................................................................................... -0.5V to 5.5V DC Output Voltage (TTL Outputs) ........................................................................................ -0.5V to VDD + 0.5V Output Current (TTL Outputs) ................................................................................................................ +/-50mA Output Current (PECL Outputs) ............................................................................................................... +/-50mA Case Temperature Under Bias......................................................................................................... -55o to +125oC Storage Temperature .................................................................................................................... -65oC to +150oC Maximum Input ESD (Human Body Model) .............................................................................................. 1500 V Recommended Operating Conditions Power Supply Voltage, (VDD)................................................................................................................ +3.3V+5% Operating Temperature Range ............................................................. 0oC Ambient to +95oC Case Temperature Notes: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 8 G52146-0, Rev. 4.0 5/28/98 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 1.25Gbits/sec Gigabit Ethernet Transceiver Figure 7: Parametric Measurement Information Serial Input Rise and Fall Time 80% 20% TTL Input and Output Rise and Fall Time Vih(min) Vil(max) Tr Tf Tr Tf Receiver Input Eye Diagram Jitter Tolerance Mask Bit Time Amplitude Eye Width% Parametric Test Load Circuit Serial Output Load TTL A.C. Output Load Z0 = 75Ω 75Ω 10 pF VDD – 2.0V G52146-0, Rev. 4.0 5/28/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION 1.25Gbits/sec Gigabit Ethernet Transceiver Data Sheet VSC7135 Figure 8: Input Structures Input Structures VDD +3.3 V INPUT Current Limit R R GND REFCLK and TTL Inputs A VDD +3.3 V INPUT INPUT All Resistors 3.3K GND High Speed Differential Input (RX+/RX-) B Page 10 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52146-0, Rev. 4.0 5/28/98 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 Package Pin Descriptions Figure 9: Pin Diagram TX+ TXVDDP VDDD VSSANA VDDANA VSSD VDDD RX+ VDDP RXVSSD VDDD N/C 1.25Gbits/sec Gigabit Ethernet Transceiver N/C VDDP 63 VSSD T0 T1 T2 VDDD T3 T4 T5 T6 VDDD T7 T8 T9 VSSD VSSD N/C 1 3 61 59 57 55 53 51 49 47 45 5 43 7 41 9 39 11 37 13 35 15 17 19 21 23 25 27 29 31 33 N/C COMDET VSST R0 R1 R2 VDDT R3 R4 R5 R6 VDDT R7 R8 R9 VSST (Top View) Table 4: Pin Identification Pin # 2-4, 6-9, 11-13 Name T0:9 INPUTS - TTL 10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of REFCLK. The data bit corresponding to T0 is transmitted first. INPUT - TTL This rising edge of this clock latches T0:9 into the input register. It also provides the reference clock, at one tenth the baud rate to the PLL. OUTPUTS - Differential PECL (AC Coupling recommended) These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH, TX+ is HIGH and TX- is LOW. OUTPUTS - TTL 10-bit received character. Parallel data on this bus is clocked out on the rising edges of RCLK and RCLKN. R0 is the first bit received on RX+/RX-. 22 REFCLK 62, 61 TX+, TX- 45-43, 4138, 36-34 R0:9 G52146-0, Rev. 4.0 5/28/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 N/C TEST1 EWRAP TEST2 VSSD REFCLK TEST3 EN_CDET VSSD TEST4 N/C VDDD VDDT RCLKN RCLK VSST Description Page 11 VITESSE SEMICONDUCTOR CORPORATION 1.25Gbits/sec Gigabit Ethernet Transceiver Pin # 19 Data Sheet VSC7135 Description Name EWRAP INPUT - TTL LOW for Normal Operation. When HIGH, an internal loopback path from the transmitter to the receiver is enabled and the TX outputs are held HIGH. INPUTS - Differential PECL (AC Coupling recommended) The serial receive data inputs selected when EWRAP is LOW. Internally biased tot VDD/2, with 3.3KΩ resistors from each input pin to VDD and GND. OUTPUT - Complementary TTL Recovered clocks derived from one twentieth of the RX+/- data stream. Each rising transition of RCLK or RCLKN corresponds to a new word on R0:9. INPUT - TTL Enables COMDET and word resynchronization when HIGH. When LOW, keeps current word alignment and disables COMDET. OUTPUT - TTL This output goes HIGH for half of an RCLK period to indicate that R0:9 contains a Comma Character (‘0011111XXX’). COMDET will go HIGH only during a cycle when RCLKN is rising. COMDET is enabled by EN_CDET being HIGH. INPUT These signals are used for factory test. For normal operation, tie to VDD. OUTPUT This signal is used for factory test. For normal operation, leave open. Analog Power Supply Analog Ground Digital Logic Power Supply 54, 52 RX+, RX- 31, 30 RCLK, RCLKN 24 EN_CDET 47 COMDET 18,20,23 TEST1 TEST2 TEST3 TEST4 VDDANA VSSANA VDDD 26 57 58 5, 10, 28, 50, 55, 59 1, 14, 15, 21, 25, 51, 56 29, 37, 42 32, 33, 46 53, 60, 63 16,17,27, 48,49,64 VSSD VDDT VSST VDDP N/C Digital Logic Ground TTL Output Power Supply TTL Output Ground PECL I/O Power Supply No Connection. These pins are not internally connected. Page 12 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52146-0, Rev. 4.0 5/28/98 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 Package Information 64 PQFP Package Dimensions 1.25Gbits/sec Gigabit Ethernet Transceiver D D1 64 49 48 1 Item A A2 D D1 E E1 E 10 mm 2.45 2.00 13.20 10.00 13.20 10.00 0.22 0.50 0.88 0° - 7° 14 mm 2.35 2.00 17.20 14.00 17.20 14.00 0.35 0.80 0.88 Tolerance MAX +.10/-.05 ±.25 ±.10 ±.25 ±.10 ±.05 BASIC ±.15/-.10 E1 b e 16 33 L θ 17 10o TYP 32 A A2 100 TYP e 0.30 RAD. TYP. A 0.20 RAD. TYP . STANDOFF 0.25 MAX. 0.17 MAX. 0.25 L θ b 0.102 MAX. LEAD COPLANARITY NOTES: All drawings not to scale All units in mm unless otherwise noted. 10 x 10 mm Package # 101-266-1 14 x 14 mm Package # 101-262-1 G52146-0, Rev. 4.0 5/28/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION 1.25Gbits/sec Gigabit Ethernet Transceiver Data Sheet VSC7135 Package Thermal Considerations The VSC7135 is packaged in a 14 mm conventional PQFP with an internal heat spreader. This package use an industry-standard EIAJ footprint, but have been enhanced to improve thermal dissipation. The construction of the packages are as shown in Figure 12. Figure 10: Package Cross Section - 14 mm package Plastic Molding Compound Copper Heat Spreader Lead Table 5: Thermal Resistance Symbol Bond Wire Die Description Thermal resistance from junction to case Thermal resistance from case to ambient in still air including conduction through the leads. Thermal resistance from case to ambient with 100 LFM airflow Thermal resistance from case to ambient with200 LFM airflow Thermal resistance from case to ambient with 400 LFM airflow Thermal resistance from case to ambient with 600 LFM airflow 10mm Value 10.0 50.8 41.2 36.9 31.8 27.8 14mm Value 9.5 29 26.1 23.8 20.5 17.9 Units oC/W oC/W oC/W oC/W oC/W oC/W θjc θca θca-100 θca-200 θca-400 θca-600 The VSC7135 is designed to operate with a junction temperature up to 105oC. The user must guarantee that the temperature specification is not violated. With the Thermal Resistances shown above, the 10x10 PQFP can operate in still air ambient temperatures of 55oC [55oC=110oC-0.9W*(10oC/W+50.8oC/W)] while the 14x14 PQFP can operate in still air ambient temperatures of 75oC [75oC=110oC-0.9W*(9.5oC/W+29oC/W)]. If the ambient air temperature exceeds these limits then some form of cooling through a heatsink or an increase in airflow must be provided. Moisture Sensitivity Level This device is rated with a moisture sensitivity level 3 rating. Refer to Application Note AN-20 for appropriate handling procedures. Page 14 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52146-0, Rev. 4.0 5/28/98 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 Ordering Information 1.25Gbits/sec Gigabit Ethernet Transceiver The part number for this product is formed by a combination of the device number and the package style: VSC7135xx Device Type: VSC7135: 1.25 Gbps Transceiver Package Style (64-pin) QN: 14x14mm PQFP QU: 10x10mm PQFP Marking Information The package is marked with three lines of text as shown below (QU Package): Pin Identifier VITESSE VSC7135QU #### AAAA# Package Suffix Part Number Date Code Lot Tracking Code Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products, specifications or other information at any time without prior notice. Therefore the reader is cautioned to confirmation that this datasheet is current prior to placing any orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. G52146-0, Rev. 4.0 5/28/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION 1.25Gbits/sec Gigabit Ethernet Transceiver Data Sheet VSC7135 Page 16 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52146-0, Rev. 4.0 5/28/98