VSC7146RH

VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7146 Features • Speed Selectable Full-Duplex Transceiver: - 1.06/2.12Gb/s for FibreChannel - 1.25/2.5Gb/s for Gigabit Ethernet • 20-Bit TTL Interface for Transmit and Receive Data at 125MHz • Monolithic Clock Synthesis and Clock Recovery - No External Components • 125MHz TTL Reference Clock 2.5Gb/s, 20-Bit Transceiver • Automatic Lock-to-Reference Function • Suitable for Both Coaxial and Optical Link Applications • Low Power Operation: 2.5 W max • 80-Pin, 14mm Thermally-Enhanced EDQUAD Package • Single +3.3V Supply General Description The VSC7146 is a 2.5Gb/s Transceiver optimized for ease-of-use and efficiency in high-performance data transmission systems. The VSC7146 accepts two 10-bit 8b/10b encoded transmit characters, latches them on the rising edge of Transmit Byte Clock (TBC) and serializes the data onto the TX+/- differential outputs at a baud rate, which is 20 times the TBC frequency. The VSC7146 also samples serial receive data on the RX+/differential inputs, recovers the clock and data, deserializes it onto two 10-bit receive characters, outputs a recovered clocks at one-twentieth of the incoming baud rate and detects Fibre Channel “comma” characters. The VSC7146 contains on-chip Phase-Lock Loop (PLL) circuitry for synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream. These circuits are fully monolithic and require no external components. Block Diagram EWRAP 20 R0:19 QD Serial to Parallel Retimed Data Recovered Clock QD Clock Recovery 2:1 RX+ RX- RBC RBCN 125 MHz ÷ 20 Comma Detect RXRATE COM_DET EN_CDET Frame Logic T0:19 TBC 20 DQ Parallel to Serial 2.5 Gb/s Serial Data 2.5 Gb/s DQ TX+ TX- 125 MHz REF TXRATE BCMN PLL Clock Multiply (x20) 2.5 GHz Synthesized Clock G52162-0, Rev. 2.7 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.5Gb/s, 20-Bit Transceiver VSC7146 Functional Description Clock Synthesizer The VSC7146 clock synthesizer multiplies the 125MHz reference frequency provided on the REF input by 20 to achieve a baud rate clock at 2.5GHz. The clock synthesizer contains a fully monolithic PLL which requires no external components. An additional 125MHz clock, TBC, should be provided to clock in the data bus. Since TBC is only used for the purpose of clocking data in, it is not required to have the same jitter constraints as REF. REF clock and TBC should preserve certain phase margins and be of the same frequency. Serializer The VSC7146 accepts TTL input data as two parallel 10-bit characters on the T[0:19] bus which is latched into the input latch on the rising edge of a 125MHz clock at TBC. This data will be serialized and transmitted on the TX differential outputs at a baud rate of 20 times the frequency of the TBC input, with bit T0 transmitted first. User data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel specification, or an equivalent, edge rich, DC-balanced code. If EWRAP is HIGH, the transmitter will be disabled with TX+ HIGH and TX- LOW. If EWRAP is LOW, the transmitter outputs serialized data. The phases of REF clock and TBC can be identical, but there is a phase relationship between the two input clocks which must be maintained. Transmission Character Interface In Fibre Channel, an encoded byte is 10 bits and is referred to as a transmission character. The 20-bit interface on the VSC7146 corresponds to two transmission characters. This mapping is shown in Figure 1. Figure 1: Transmission Order and Mapping to Fibre Channel Character Parallel Data Bits 8B/10B Bit Position Valid “Comma” Position 19 j 18 h 17 g 16 f 15 i 14 e 13 d 12 c 11 b 10 a 09 j 08 h 07 g 06 f 1 05 i 1 04 e 1 03 d 1 02 c 1 01 b 0 00 a 0 Last Data Bit Transmitted First Data Bit Transmitted Clock Recovery The VSC7146 accepts differential high-speed serial inputs on the RX+/RX- pins, (when EWRAP is LOW), extracts the clock and retimes the data. The serial bit stream should be encoded so as to provide DC balance and limited run length by a Fibre Channel-compatible 8B/10B transmitter or equivalent. The VSC7146 clock recovery circuitry is completely monolithic and requires no external components. For proper operation, the baud rate of the data stream to be recovered should be within 200ppm of twenty times the REF frequency. This allows oscillators on either end of the link to be 125MHz +/- 100ppm. Page 2 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52162-0 Rev. 2.7 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7146 2.5Gb/s, 20-Bit Transceiver Deserializer The retimed serial bit stream is converted into two 10-bit parallel output characters. The VSC7146 provides a TTL recovered clock, RBC, at one twentieth of the serial baud rate. The clock is generated by dividing down the high-speed clock which is phase-locked to the serial data. The serial data is retimed by the internal highspeed clock, and deserialized. The resulting parallel data will be captured by the adjoining protocol logic on the rising edge of RBC. If serial input data is not present, or does not meet the required baud rate, the VSC7146 will continue to produce a recovered clock and RBC will automatically lock to the REF reference clock. This eliminates the need for a Lock-to-Reference input pin and simplifies the support software for that function. Word Alignment The VSC7146 provides 7-bit Fibre Channel “comma” character recognition and data word alignment. Word synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7146 constantly examines the serial data for the presence of the Fibre Channel “comma” character. This pattern is “0011111XXX”, where the leading zero corresponds to the first bit received. The “comma” sequence is not contained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and K28.7, which are defined specifically for synchronization in Fibre Channel systems. Improper alignment of the “comma” character is defined as either of the following conditions: 1) The “comma” is not aligned within the 10-bit transmission character such that T0...T6 = “0011111.” 2) The “comma” straddles the boundary between two 10-bit transmission characters. When EN_CDET is HIGH and an improperly aligned “comma” is encountered, the internal data is shifted in such a manner that the “comma” character is aligned properly in R[0:6] as shown in Figure 1. This results in proper character and word alignment. When the parallel data alignment changes in response to a improperly aligned “comma” pattern, some data which would have been presented on the parallel output port may be lost. However, the synchronization character and subsequent data will be output correctly and properly aligned. When EN_CDET is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern. On encountering a “comma” character, COM_DET is driven HIGH to inform the user that realignment of the parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the “comma” character and has a duration equal to the data. The COM_DET signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of RBC. Functional waveforms for synchronization are shown in Figure 2 and Figure 3. Figure 2 shows the case when a “comma” character is detected and no phase adjustment is necessary. It illustrates the position of the COM_DET pulse in relation to the “comma” character on R[0:6]. Figure 3 shows the case where the K28.5 is detected, but it is out-of-phase and a change in the output data alignment is required. Note that up to three characters prior to the “comma” character may be corrupted by the realignment process. G52162-0, Rev. 2.7 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.5Gb/s, 20-Bit Transceiver Figure 2: Detection of a Properly Aligned “Comma” Character VSC7146 RBCN COM_DET R[0:9] R[10:19] K28.5 TChar TChar TChar TChar TChar TChar TChar TChar: 10 bit Transmission Character Figure 3: Detection and Resynchronization of an Improperly Aligned “Comma” Character Receiving Two Consecutive K28.5+TChar Transmission Words RBCN COM_DET R[0:9] R[10:19] Potentially Corrupted K28.5 TChar TChar TChar TChar TChar TChar TChar K28.5 TChar TChar TChar Page 4 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52162-0 Rev. 2.7 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7146 2.5Gb/s, 20-Bit Transceiver Dual Data Rate Operation The VSC7146 performs at two data rates, full-speed (2.5 Gb/s on the serial link, 125MHz on the parallel 20-bit data bus) and half-speed (1.25 Gb/s on the serial link, 62.5 Mb/s on the parallel 20-bit data bus). To accommodate for this, the user is provided with 3 signal pins for data rate control: TXRATE, RXRATE and BCMN. The usage of these signals is as follows: If BCMN = 0 (Backwards Compatibility Mode), TXRATE controls both the serializer and deserializer speeds. TXRATE should be HIGH for full-speed operation and LOW for half-speed operation. If BCMN = 1, TXRATE controls the serializer speed and RXRATE controls the deserializer speed. TXRATE and/or RXRATE must be HIGH for full-speed operation and/or LOW for half-speed operation. Table 1: Data Rate BCMN 0 0 1 1 1 1 TXRate 1 0 0 0 1 1 RXRate X X 0 1 0 1 Description Both serializer and deserializer run at full-speed. Both serializer and deserializer run at half-speed. Both serializer and deserializer run at half-speed. Serializer is run at half-speed and deserializer is run at full-speed. Serializer is run at full-speed and deserializer is run at half-speed. Both serializer and deserializer run at full-speed. For “comma” character (K28.5) detection, it is recommended not to use differing RXRATE inputs to actual RX rate data reception, as shown in the Table 2 (assumes EN_CDET = 1): Table 2: Comma Detect RXRate 0 Half-Speed 0 Half-Speed 1 Full-Speed 1 Full-Speed RX+/- Actual Data Rate 2.5Gb/s 1.25Gb/s 2.5Gb/s 1.25Gb/s Normal detection operation. Normal detection operation. “Comma” Detect Will only detect 00/00/11/11/11/11/11 pattern as “comma”. Do not use. Will detect false characters (e.g., those that include “0111”) as “comma”. Do not use. Similarly, it is recommended not to use differing TXRATE inputs to actual TX rate data reception. The T[19:0] data bus, TBC and REF clock inputs must be at 125Mb/s rates if TXRATE = 1 and 62.5Mb/s if TXRATE = 0. It is important to note that the PLL will not lock otherwise. Along with the 20-bit data input to the serializer, the user will also have to send the appropriate transmit byte clock signal (TBC)—that is, 125MHz when TXRATE = 1 and 62.5MHz when TXRATE = 0. REF and TBC should be frequency-locked in all cases and should maintain a certain phase relationship as shown in Figure 6. The output recovered clocks (RBC/RBCN), the output deserialized data (R[19:0]) and the internal VCO high-speed clock multiplier will be automatically adjusted by the TXRATE and RXRATE signals. The baud rate of the data stream to be recovered in the deserializer should be within 200ppm of the REF frequency. In other words: F REF – TX – F REF – RX ≤ 200 ppm © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52162-0, Rev. 2.7 Page 5 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.5Gb/s, 20-Bit Transceiver Figure 4: Transmit Timing Waveforms VSC7146 TBC T1 T2 T[0:19] 20-Bit Data Data Valid Data Valid Data Valid Table 3: Transmit AC Characteristics Parameters T1 T2 TSDR,TSDF TLAT Description T[0:19] setup time to the rising edge of TBC T[0:19] hold time after the rising edge of TBC TX+/TX- rise and fall time Latency from rising edge of TBC to T0 appearing on TX+ TXSerial data output random jitter (RMS) Serial data output deterministic jitter (p-p) Min 1.5 1.0 Typ Max — — Units ns ns Conditions Measured between the valid data level of T[0:19] to the 1.4V point of TBC. — 24 bc +1ns 160 45 bc +1ns ps Bit Clock 20% to 80% into 50Ω load to VSS. Tested on a sample basis. Bit clock periods (PLL locked) Transmitter Output Jitter Allocation TRJ TDJ — — 5 25 7.5 30 ps ps RMS, tested on a sample basis. Peak-to-peak, tested on a sample basis. Page 6 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52162-0 Rev. 2.7 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7146 Figure 5: Receive Timing Waveforms 2.5Gb/s, 20-Bit Transceiver RBCN RBC T 3 T3 T1 T2 Data Valid R[0:19] and COM_DET Data Valid Data Valid Table 4: Receive AC Characteristics Paramete rs T1 T2 T3 TR1, TF1 TR2, TF2 RLAT TRBC DC TLOCK Description Data or COM_DET valid prior to RBCN rise Data or COM_DET valid after RBCN rise Time difference between RBC and RBCN edges RBC/RBCN rise and fall time R[0:19], COM_DET rise and fall time Latency from RX to R[0:19] RBC period RBC duty cycle Data acquisition lock time @ 2.5Gb/s Min. 1.0 2.0 5.0 10.0 — 0.6 0.7 36bc+ 2ns 7.9 15.8 40% — Max. — — 1 2.0 2.4 56bc+ 2ns 8.1 16.2 60% 1250 Units ns ns ns ns ns Bit Clocks ns period Bit Clocks Conditions Measured between the 1.4V point of RBCN and a valid level of R[0:19] or COM_DET. All outputs driving 10pF load. The spec on top relects RXMODE=1 and the bottom one reflects RXMODE=0. Between VIL(max) and VIH(min), into 10pF load. Between VIL(max) and VIH(min), into 10pF load. When locked to valid data. The spec on top relects RXMODE=1 and the bottom one reflects RXMODE=0. Tested on a sample basis. 95% probability of lock. G52162-0, Rev. 2.7 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.5Gb/s, 20-Bit Transceiver Figure 6: TBC and REF Timing Waveforms TH VSC7146 TBC REF TL VIH(min) VIL(max) REF T1 T2 TBC REF and TBC must not have their opposing edges coincident within 2.0ns of each other. Table 5: TBC and REF Requirements Parameters T1 T2 FR Description Necessary lag time between TBC and REF Necessary lead time between TBC and REF Frequency Range 105 52.5 FO TL,TH Frequency Offset Pulse Width, Low / High 4.5 2.5 ns −100 127 63.5 +100 MHz Min — — Max 2.0 2.0 Units ns ns Conditions Measured from falling edge of REF to rising edge of TBC. Measured from falling edge of REF to rising edge of TBC. Range over which both transmit and receive reference clocks on any link may be centered. The figure on top relects TXMODE=1 and the bottom one reflects TXMODE=0. |TXTBC - RXTBC| Low is measured from VIL(max) to VIL(max), High is measured from VIH(min) to VIH(min). Min measurement refers to TXMODE=0 and Max measurement refers to TXMODE=1. Measured at 1.5V. Between VIL(max) and VIH(min). ppm DC TRCR,TRCF TBC and REF duty cycle TBC and REF rise and fall time 40 0.6 60 1.5 % ns Page 8 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52162-0 Rev. 2.7 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7146 2.5Gb/s, 20-Bit Transceiver Figure 7: Parametric Measurement Information Serial Input Rise and Fall Time 80% 20% TTL Input and Output Rise and Fall Time VIH(min) VIL(max) Tr Tf Tr Tf Receiver Input Eye Diagram Jitter Tolerance Mask Bit Time Amplitude Eye Width% Parametric Test Load Circuit Serial Output Load TTL AC Output Load Z0 = 50Ω 50Ω VDD-0.6V 10 pF G52162-0, Rev. 2.7 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.5Gb/s, 20-Bit Transceiver VSC7146 Absolute Maximum Ratings (1) Power Supply Voltage, (VDD) ........................................................................................................... −0.5V to +4V DC Input Voltage (Differential inputs) .................................................................................. −0.5V to VDD +0.5V DC Input Voltage (TTL inputs) .............................................................................................. −0.5V to VDD+0.5V DC Output Voltage (TTL Outputs)....................................................................................... −0.5V to VDD + 0.5V Output Current (TTL Outputs) ................................................................................................................... ±50mA Output Current (Differential Outputs) ............................................................................................±50mA Case Temperature Under Bias ..................................................................................................... −55oC to +125oC Storage Temperature .................................................................................................................... −65oC to +150oC Relative Humidity (Storage)...................................................................................... 0% - 95% (Non-condensing) Relative Humidity (Operating)................................................................................................................ 8% - 80% Maximum Input ESD (Human Body Model)............................................................................................1500V(2) NOTES: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied.Exposure to these values for extended periods may affect device reliability. (2) High-speed PECL receiver inputs only are rated at 700V. Recommended Operating Conditions Power Supply Voltage, (VDD) ................................................................................................................+3.3V+5% Power Supply Noise, (VDD) ........................................................................ 100mVp-p from 100Hz to TBD MHz Operating Temperature Range ............................................................. 0oC Ambient to +90oC Case Temperature Page 10 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52162-0 Rev. 2.7 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7146 DC Characteristics (Over recommended operating conditions) Parameters VOH VOL ∆VOUT50(1) 2.5Gb/s, 20-Bit Transceiver Description Output HIGH voltage (TTL) Output LOW voltage (TTL) Serial output absolute voltage differential peak-to-peak swing (TX+/TX-) Serial output absolute voltage differential peak-to-peak swing (TX+/TX-) Serial input absolute voltage differential peak-to-peak swing (RX+/RX-) Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Supply voltage Power dissipation Supply current Output resistance (TX) Input resistance (RX) Min 2.4 — 600 Typ — — 1100 Max — 0.5 2000 Units V V mV Conditions IOH = −1.0 mA IOL = +1.0 mA Driving a 50Ω transmission line (TX+ - TX-) Driving a 75Ω transmission line (TX+ - TX-) (RX+ - RX-) ∆VOUT75(1) 600 1100 2000 mV ∆VIN (1) VIH VIL IIH IIL VDD PD IDD ZO ZI 400 2.0 0 — — 3.14 — — — — — — — — — 1.8 550 50 50 2200 5.5 0.8 1000 -500 3.47 2.6 750 — — mV V V µA µA V W mA Ω Ω VIN = 2.4 V VIN = 0.5 V +3.3V± 5% Outputs open, VDD = VDD max Outputs open, VDD = VDD max Note: (1) Refer to Application Note, AN-37, for differential measurement techniques. G52162-0, Rev. 2.7 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.5Gb/s, 20-Bit Transceiver Figure 8: Input Structures VDD +3.3 V VSC7146 INPUT Current Limit R R GND TTL Inputs Figure 9: High-Speed I/O Termination Scheme Transmitter Output 50 50 50Ω Transmission Line Receiver Input 50 VBB 50 VSC7146 Off-Chip VSC7146 No external resistor terminations are necessary on the high-speed I/O Page 12 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52162-0 Rev. 2.7 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7146 Package Pin Descriptions Figure 10: Pin Diagram (Top View) TEST4 RXRATE VDD VSSP VDDP 2.5Gb/s, 20-Bit Transceiver TXTX+ VDDP VSSA VDDA VSS VDD RX+ RX- VDD 79 77 75 73 71 69 67 65 R0 R10 63 VDD T0 T10 T1 T11 T2 VSS T12 T3 T13 T4 T14 VDD T5 T15 T6 T16 T7 T17 T8 1 59 3 57 5 55 7 53 9 51 11 49 13 47 15 45 17 43 19 21 23 25 27 29 31 33 41 35 37 39 61 R1 R11 VSST VSST R2 R12 R3 R13 R4 R14 VDDT R5 R15 R6 R16 R7 R17 VDDT R8 R18 R9 R19 VSST NOTES: Heat Sink is not connected electrically. It should not be connected electrically by the user. Pin 80 has changed from SLOOP in previous versions of the spec to TEST4. Tie this pin to VSS. G52162-0, Rev. 2.7 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 TXRATE EWRAP COM_DET RBC RBCN VSST TBC BCMN VSS TEST1 TEST2 TEST3 EN_CDET VDD T18 T9 T19 VSS REF VSS Page 13 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.5Gb/s, 20-Bit Transceiver Table 6: Pin Identifications Pin # 2, 4, 6, 9, 11, 14, 16, 18, 20, 23, 3, 5, 8, 10, 12, 15, 17, 19, 22, 24 26 VSC7146 Description INPUTS - TTL: Transmit Data Bus, Bit 0 through Bit 19. 20-bit Transmit Character. Parallel data on this bus is clocked in on the rising edge of TBC. The data bit corresponding to T0 is transmitted first. INPUT - TTL: Reference Clock. REF goes to the PLL/CMU circuitry and is multiplied 20 times INPUT - TTL: Transmit Byte Clock. This rising edge of this clock latches T[0:19] into the input register and provides the reference clock at 1/20th of the baud rate to the PLL. OUTPUTS - Differential (AC-coupling recommended): Transmitter Serial Outputs. These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH, TX+ is HIGH and TX- is LOW. OUTPUTS - TTL: Receive Data Bus, Bits 0 thru 19. 20-bit received character. Parallel data on this bus can be sampled on the rising edge of RBC. R0 is the first bit received on RX+/RX-. INPUT - TTL: Transmitter Dual Rate Selector. LOW for half-speed operation (1.25Gb/s). HIGH for full-speed operation (2.5 Gbps). INPUT - TTL: Receiver Dual Rate Selector. LOW for half-speed operation (1.25Gb/s). HIGH for full-speed operation (2.5Gb/s). INPUT - TTL: Backwards Compatibility Mode Selector. LOW to allow operation in previous version compatibility (no separate rate controls for transmitter and receiver). HIGH to allow operation with separate rate controls for transmitter and receiver. INPUT - TTL: Enable Internal WRAP Mode. LOW for Normal Operation. When HIGH, an internal loopback path from the transmitter to the receiver is enabled, TX+ = HIGH and TXis LOW. INPUTS - Differential (AC-coupling recommended): Receive Serial Inputs. The receiver inputs when EWRAP is LOW. OUTPUT - TTL: Recovered Byte Clock. Recovered clock and complement derived from 1/20th of the RX+/- data rate. The rising edge of RBC corresponds to a new word on R[0:19]. Name T[0:19] REF 28 TBC 74,75 65, 63, 59, 57, 55, 52, 50, 48, 45, 43, 64, 62, 58, 56, 54, 51, 49, 47, 44, 42 35 TX+, TX- R[0:19] TXRATE 79 RXRATE 29 BCMN 36 EWRAP 68, 67 38, 39 RX+, RXRBC, RBCN 34 INPUT - TTL: ENable Comma DETect. Enables COM_DET and word resynchroniEN_CDET zation when HIGH. When LOW, keeps current word alignment and disables COM_DET. OUTPUT - TTL: COM_DET COMma DETect. This output goes HIGH to indicate that R[0:6] contains a “comma” character (‘0011111’). COM_DET can be sampled on the rising edge of RBC. 37 Page 14 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52162-0 Rev. 2.7 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7146 Pin # 31, 32, 33 2.5Gb/s, 20-Bit Transceiver Name TEST1, TEST2, TEST3 TEST4 VDD VDDT VDDA VDDP VSS VSST VSSA VSSP Description TEST Pins For internal Vitesse use only. Customers should tie TEST1, TEST2 and TEST3 to VDD. TEST Pins For internal Vitesse use only. Customers should tie TEST4 to V SS. Digital Power Supply, +3.3V. TTL Power Supply, +3.3V. Analog Power Supply, +3.3V. High-Speed Output Driver Power Supply, +3.3V Digital Ground, 0V. TTL Ground, 0V. Analog Ground, 0V. High-Speed Output Driver Ground, 0V. 80 1, 13,21, 66, 69,78 46, 53 71 73, 76 7, 25, 27, 30, 70 40, 41, 60, 61 72 77 G52162-0, Rev. 2.7 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.5Gb/s, 20-Bit Transceiver VSC7146 Package Information F G 80 61 60 1 Item A D E F G H I H I J K 14 mm 2.35 2.00 0.30 17.20 14.00 17.20 14.00 0.88 0.65 Tolerance MAX +0.10/-0.05 ±.05 ±.25 ±.10 ±.25 ±.10 +.15/-.10 BASIC 20 21 40 41 10° TYP EXPOSED HEATSINK 6.85 + .50 DIA HEATSINK INTRUSION .0127 MAX D A 10° TYP K 0.30 RAD. TYP. 0.20 RAD. TYP. A 0.25 STANDOFF 0.25 MAX. 0.102 MAX LEAD COPLANARITY 0.17 MAX. 0° - 8° J NOTES: Drawing not to scale. All units in mm unless otherwise noted. E Page 16 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52162-0 Rev. 2.7 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7146 Package Thermal Characteristics 2.5Gb/s, 20-Bit Transceiver The VSC7146 is packaged in an 80-pin, 14mm thermally-enhanced EDQUAD with an internal heat spreader. These packages use industry-standard EIAJ footprints, which have been enhanced to improve thermal dissipation. The construction of the packages are as shown in Figure 11. The VSC7146 is designed to operate with a case temperature up to 90oC. The user must guarantee that the temperature specification is not violated. Figure 11: Package Cross Section Exposed Heat Slug Insulator Plastic Molding Compound Lead Wire Bond Thermal Epoxy Die Table 7: Thermal Resistance Symbol θjc θca-0 θca-100 θca-200 θca-400 θca-600 Description Thermal resistance from junction-to-case Thermal resistance from case-to-ambient, still air Thermal resistance from case-to-ambient, 100 LFPM air Thermal resistance from case-to-ambient, 200 LFPM air Thermal resistance from case-to-ambient, 400 LFPM air Thermal resistance from case-to-ambient, 600 LFPM air Value 2.5 35 29 26 22 19 Units oC/W oC/W oC/W oC/W oC/W oC/W G52162-0, Rev. 2.7 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 17 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.5Gb/s, 20-Bit Transceiver VSC7146 Ordering Information The part number for this product is formed by a combination of the device number and the package style: VSC7146 Device Type 2.5 Gb/s, 20-Bit Transceiver xx Package RH: 80-Pin, 14x14mm EDQUAD Notice This document contains information about a new product during its fabrication or early sampling phase of development. The information contained in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore, the reader is cautioned to confirm that this data sheet is current prior to design or order placement. Warning Vitesse Semiconductor Corporation’s products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. Page 18 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52162-0 Rev. 2.7 8/28/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7146 Revision History: 1.0 Initial Release 2.5Gb/s, 20-Bit Transceiver 1.1 Fix Fig 5, Add Figure 10, New numbers for Power Supply, Dissipation, Zi/Zo/Ri/Ro & Termination. 1.2 Added Trj/Tdj, Power Supply Noise, Pinout Diagram, Different Thermals, Added Reliability 1.3 Filled in TBA’s, package pinout, pin description, dual-mode description. For internal CDR. 2.0 Post CDR. Rev.A target spec. 2.1 Pre-CDR. Rev. B target spec. 2.2 Post-CDR. Rev. B API. Removed reliability table. Changed BCLK name to TBC. 2.2.1 Removed 50 ohm termination wording in table on page 10. 2.3 Modified title and features section to reflect dual speed. 2.4 Added facility loop-back (SLOOP) and speed negotiation port (TXRATE, RXRATE, BCMN) features. Modified pinout list and diagram accordingly. Modified spec as per ICR results. Changed package type from QZ to RH. 2.5 Removed facility loop-back (SLOOP) feature. Changed pin# 80 from SLOOP to TEST4. Modified Figures 2 and 3 to better reflect RBCN relationship with output data R[0:19]. Modified RBCN vs. R bus timing as per characterization findings. 2.6 Revised max Idd to 750 ma, max power to 2.6 W; Modified ESD rating on p.10; removed “Vitesse Confidential” 2.7Added typ column to Table 3: TRJ:added typ 5 ps, changed max from 5ps to 7.5ps; TDJ: added typ 25ps. Corrected grammatical/typo errors and corrected inconsistencies. Updated format. Removed marking information. G52162-0, Rev. 2.7 8/28/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 19