VSC7182TW

® VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7182 Features • Four Complete Transmitter/ Receiver Functions in a Single Integrated Circuit • Full Fibre Channel (T11) and Gigabit Ethernet (IEEE 802.3z) Compliance • 1.05Gb/s to 1.36Gb/s Operation per Channel • Common or Per-Channel Transmit Byte Clocks • TTL or PECL Reference Clock Input • Receiver Squelch Circuit Quad Transceiver for Gigabit Ethernet and Fibre Channel • Common and Per-Channel, Serial and Parallel Loopback Controls • Common Comma Detect Enable Inputs • Per-Channel Comma Detect Outputs • Cable Equalization in Receivers • Replacement For Agilent’s HDMP-1682 • 3.3V Power Supply, 2.67 W Max Dissipation • 208-Pin, 23mm BGA Packaging General Description The VSC7182 is a full-speed quad Fibre Channel and Gigabit Ethernet transceiver IC. Each of the four transmitters has a 10-bit wide bus, running up to 136MHz, which accepts 8B/10B encoded transmit characters and serializes the data onto high-speed differential outputs at speeds up to 1.36Gb/s. The transmit data can be synchronous to the reference clock, a common transmit byte clock or a per-channel transmit byte clock. Each receiver samples serial receive data, recovers the clock and data, deserializes it into 10-bit receive characters, outputs a recovered clock and detects “Comma” characters. The VSC7182 contains on-chip Phase-Lock Loop (PLL) circuitry for synthesis of the baud-rate transmit clock and extraction of the clocks from the received serial streams. The VSC7182 also includes a receiver squelch circuit to control the parallel data bus in the absence of serial input. VSC7182 Block Diagram (1 of 4 Channels) 10 RXi[0:9] QD Serial to Q Parallel D ÷10 QD 0 1 Clock Recovery SI+ SI- RCM RCi1 RCi0 SYNi SYNC PLUP SLPN LPNi TXi[0:9] 4 SEL ÷10/ ÷20 Comma Detect Loopback Control 0 10 DQ 4 4 Parallel to Serial DQ 1 SO+ SO- TCi RFCT RFC+ RFCRFCM LTCN CAP0 CAP1 Clock Multiply Unit x10/x20 RFCO0 RFCO1 G52307-0, Rev 2.2 10/10/00 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 1 ® VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet and Fibre Channel Advance Product Information VSC7182 Functional Description Notation In this document, each of the four channels are identified as Channel A, B, C or D. When discussing a signal on any specific channel, the signal will have the Channel letter embedded in the name, for example, “TA[0:9]”. When referring to the common behavior of a signal which is used on each of the four channels, a lower case “x” is used in the signal name, i.e. TXi[0:9]. Differential signals, such as RA+ and RA-, may be referred to as a single signal, i.e. RA, by dropping reference to the “+” and “-”. “RFC” refers to either the TTL input RFCT, or the PECL differential inputs RFC+/RFC-, whichever is used. Clock Synthesizer The VSC7182 clock synthesizer multiplies the reference frequency provided on the RFC input by 10 or 20 to achieve a baud rate clock between 1.05GHz and 1.36GHz. The RFC input can be either TTL or PECL. If TTL, connect the TTL input clock to RFCT. If PECL, connect the PECL inputs to RFC+ and RFC-. The internal clock presented to the clock synthesizer is a logical XNOR of RFCT and RFC+/-. The reference clock will be active HIGH if the unused input is HIGH. The reference clock is active LOW if the unused input is LOW. RFCT has an internal pull-up resistor. Internal biasing resistors set the proper DC level on RFC+/- so AC-coupling may be used. The TTL outputs, RFCO0 and RFCO1, provide a clock that is frequency-locked to the RFC input. This clock is derived from the clock synthesizer and is always 1/10th the baud rate, regardless of the state of the RFCM input. The on-chip PLL uses a single external 0.1µF capacitor, connected between CAP0 and CAP1, to control the loop filter. This capacitor should be a multilayer ceramic dielectric, or better, with at least a 5V working voltage rating and a good temperature coefficient (NPO is preferred but X7R may be acceptable). These capacitors are used to minimize the impact of common-mode noise on the Clock Multiplier Unit (CMU), especially power supply noise. Higher value capacitors provide better robustness in systems. NPO is preferred because if an X7R capacitor is used, the power supply noise sensitivity will vary with temperature. For best noise immunity, the designer may use a three capacitor circuit with one differential capacitor between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to ground, C3. Larger values are better but 0.1µF is adequate. However, if the designer cannot use a three capacitor circuit, a single differential capacitor, C1, is adequate. These components should be isolated from noisy traces. Figure 1: Loop Filter Capacitors (Best Circuit) CAP0 C2 C1 C3 VSC7182 CAP1 C1=C2=C3= >0.1µF MultiLayer Ceramic Surface Mount NPO (Preferred) or X7R 5V Working Voltage Rating Page 2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52307-0, Rev 2.2 10/10/00 ® VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7182 Quad Transceiver for Gigabit Ethernet and Fibre Channel Serializer The VSC7182 accepts TTL input data as a parallel 10-bit character on the TXi[0:9] bus which is latched into the input register on the rising edge of either RFC or TCi. Three clocking modes are available and automatically detected by the VSC7182. If TCC is static and RFCM is HIGH, then all four TXi[0:9] busses are latched on the rising edges of RFC. If TCC is static and RFCM is LOW, then RFC is multiplied by 20 and the input busses are latched on the rising edges of RFC and at the midpoint between rising edges. If TCC is toggling but TCB is static, then all four TXi[0:9] busses are latched on the rising edges of TCC. If TCB and TCC are both toggling then the rising edge of each TCi latches the corresponding TXi[0:9] bus. The active TCC or TCi inputs must be frequency-locked to RFC. There is no specified phase relationship. Prior to normal data transmission, LTCN must be asserted LOW so the VSC7182 can lock to TCi, which may result in corrupted data being transmitted. Once LTCN has been raised HIGH, the transmitters remain locked to RFC and can tolerate +/-2 bit times of drift in TCi relative to RFC. The 10-bit parallel transmission character will be serialized and transmitted on the TXi PECL differential outputs at the baud rate with bit TXi0 (bit A) transmitted first. User data should be encoded using 8B/10B or an equivalent code. The mapping to 10B encoded bit nomenclature and transmission order is illustrated below, along with the recognized comma pattern. Table 1: Transmission Order and Mapping of a 10B Character Data Bit 10B Bit Position Comma Character TXi9 j x TXi8 h x TXi7 g x TXi6 f 1 TXi5 i 1 TXi4 e 1 TXi3 d 1 TXi2 c 1 TXi1 b 0 TXi0 a 0 Clock Recovery The VSC7182 accepts differential high-speed serial input from the selected source (either the PECL SI+/ SI- pins or the internal TXi+/- data), extracts the clock and retimes the data. Equalizers are included in the receiver to open the data eye and compensate for InterSymbol Interference (ISI) which may be present in the incoming data. The serial bit stream should be encoded so as to provide DC balance and limited run length by an 8B/10B encoding scheme. The digital Clock Recovery Unit (CRU) is completely monolithic and requires no external components. For proper operation, the baud rate of the data stream to be recovered should be within +200 ppm of ten times the RFC frequency. For example, Gigabit Ethernet systems would use 125MHz oscillators with a +100ppm accuracy resulting in +200 ppm between VSC7182 pairs. Deserializer The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7182 provides complementary TTL recovered clocks, RCi0 and RCi1, which are at 1/20 th o f the serial baud rate (if RCM=LOW) or 1/10th (if RCM=HIGH). The clocks are generated by dividing down the high-speed recovered clock which is phase-locked to the serial data. The serial data is retimed, deserialized and output on RXi[0:9]. If serial input data is not present, or does not meet the required baud rate, the VSC7182 will continue to produce a recovered clock so that downstream logic may continue to function. The RCi0/RCi1 output frequency under these circumstances will differ from its expected frequency by no more than +1%. A receiver squelch circuit forces the parallel data output bus to all ones if the serial receiver input level is less than 100mV differential peak-to-peak. © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52307-0, Rev 2.2 10/10/00 Page 3 ® VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet and Fibre Channel Advance Product Information VSC7182 Word Alignment The VSC7182 provides 7-bit comma character recognition and data word alignment. Word synchronization is enabled on all channels by asserting SYNC HIGH. When synchronization is enabled, the receiver examines the recovered serial data for the presence of the “Comma” pattern. This pattern is “0011111XXX”, where the leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and K28.7, which are defined for synchronization purposes. Improper comma alignment is defined as any of the following conditions: 1) The comma is not aligned within the 10-bit transmission character such that RXi(0...6) = “0011111.” 2) The comma straddles the boundary between two 10-bit transmission characters. 3) The comma is properly aligned but occurs in the received character presented during the rising edge of RCi0 rather than RCi1. When SYNC is HIGH and an improperly aligned comma is encountered, the recovered clock is stretched, never slivered, so that the comma character and recovered clocks are aligned properly to RXi[0:9]. This results in proper character and word alignment. When the parallel data alignment changes in response to a improperly aligned comma pattern, data which would have been presented on the parallel output port prior to the comma character, and possibly the comma character itself, may be lost. Possible loss of the comma character is data dependent, according to the relative change in alignment. Data subsequent to the comma character will always be output correctly and properly aligned. When SYNC is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern. On encountering a comma character, SYNi is driven HIGH. The SYNi pulse is presented simultaneously with the comma character and has a duration equal to the data. The SYNi signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of RCi1. Functional waveforms for synchronization are given in Figure 2. The first K28.5 shows the case where the comma is detected, but it is misaligned so a change in the output data alignment is required. Note that up to three characters prior to the comma character may be corrupted by the realignment process. The second K28.5 shows the case when a comma is detected and no phase adjustment is necessary. It illustrates the position of the SYNi pulse in relation to the comma character on RXi[0:9]. Figure 2: Misaligned and Aligned K28.5 Characters RCi0 (RCM LOW) RCi1 RCi0 ([RCM HIGH) RCi1 SYNi RXi[0:9] Data Corrupt Corrupt Corrupt Misaligned Comma: Stretched K28.5 Data1 Data2 Data3 K28.5 Aligned Comma Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52307-0, Rev 2.2 10/10/00 ® VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7182 Quad Transceiver for Gigabit Ethernet and Fibre Channel Loopback Operation Loopback operation is controlled by the PLUP (Parallel Loopback), SLPN (Serial Loopback) and LPNi inputs as shown in Table 2. LPNi enables PLUP/SLPN on a per-channel basis when LOW. If LPNi is HIGH, PLUP/SLPN have no impact on Channel x. When SLPN and PLUP are both HIGH the transmitter output is held HIGH. When RXx is looped back to TXx, the data goes through a clock recovery unit so much of the input jitter is removed. However, the TXx outputs may not meet jitter specifications listed in the “Transmitter AC Specifications” due to low frequency jitter transfer from RXx to TXx. Table 2: Loopback Selection LPNi LOW LOW LOW LOW HIGH PLUP LOW LOW HIGH HIGH X SLPN LOW HIGH LOW HIGH X Tranmitter Source Receiver Transmitter Transmitter HIGH Transmitter Receiver Source Receiver Receiver Transmitter Transmitter Receiver JTAG Access Port A JTAG Access Port is provided to assist in board-level testing. Through this port most pins can be accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this device is available in “VSC7182 JTAG Access Port Functionality.” G52307-0, Rev 2.2 10/10/00 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 5 ® VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet and Fibre Channel Advance Product Information VSC7182 AC Characteristics Figure 3: Transmit Timing Waveforms RFC TCi T1 T2 TXi[0:9] 10-Bit Data Data Valid Data Valid Data Valid +/-TXi TRLAT TTLAT TXi0 TXi1 TXi2 RFC TCi Table 3: Transmitter AC Characteristics Parameter T1 T2 TSDR,TSDF TRLAT TTLAT Description TXi[0:9] setup time to the rising edge of TCi or RFC TXi[0:9] hold time after the rising edge of TCi or RFC TXi+/TXi- rise and fall time Latency from rising edge of RFC to TXi0 appearing on TX+/TXLatency from rising edge of TCi to TXi0 appearing on TX+/TX- Min 1.5 Typ — Max — Units ns Conditions Measured between the valid data level of TXi[0:9] to the 1.4V point of TCi or RFC 1.0 — 7bc + 0.66ns 5bc + 0.66ns — — — — — 300 7bc + 1.46ns 11bc + 1.46ns ns ps 20% to 80%, 75Ω load to VDD/2, tested on a sample basis bc = bit clocks ns = nanoseconds ns bc = bit clocks ns = nanoseconds Transmitter Output Jitter RJ DJ Random jitter (rms) Serial data output deterministic jitter (pk-pk) — — 5 35 8 80 ps ps Measured at SO+/-, 1 sigma deviation of 50% crossing point IEEE 802.3Z Clause 38.68, tested on a sample basis Page 6 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52307-0, Rev 2.2 10/10/00 ® VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7182 Quad Transceiver for Gigabit Ethernet and Fibre Channel Figure 4: Receive Timing Waveforms RCi0 (RCM=LOW) RCi1 RCi0 (RCM=HIGH) RCi1 T1 T2 VALID VALID RXi[0:9] VALID SYNi +/-RXi RXi0 RXi1 RXi2 RLAT RCi1 Table 4: Receive Timing Waveforms Parameters T1 Description TTL outputs valid prior to RCi1/RCi0 rise Min 4.0 3.0 TBD 3.0 2.0 TBD 10 x TRX -500 1.98 x TRFC — 12bc + 2.77ns — Typ Max — — — — — — 10 x TRX +500 2.02 x TRFC 2.4 13bc + 7.28ns 1400 Units ns Conditions At 1.0625Gb/s At 1.25Gb/s At 1.36Gb/s At 1.0625Gb/s At 1.25Gb/s At 1.36Gb/s TRX is the bit period of the incoming data on RXi. Whether or not locked to serial data. Between VIL(MAX) and VIH(MIN), into 10 pf load. bc = bit clock ns = nanosecond T2 T3 T4 TR, TF RLAT TLOCK TTL outputs valid after RCi1 or RCi0 rise Delay between rising edge of RCi1 to rising edge of RCi0 Period of RCi1 and RCi0 TTL Output rise and fall time Latency from serial bit RXi0 to rising edge RCi1 Data acquisition lock time(1) ns ps ps ns bit times 8B/10B IDLE pattern. Tested on a sample basis. NOTE: (1) Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3. G52307-0, Rev 2.2 10/10/00 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 7 ® VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet and Fibre Channel Advance Product Information VSC7182 Figure 5: RFC and TCi Waveforms TL RFC TCi TH VIH(MIN) VIL(MAX) RFCO0 RFCO1 TP Table 5: Reference Clock Requirements Parameters FR Description Frequency range Min 105 Typ Max 136 Units MHz Conditions Range over which both transmit and receive reference clocks on any link may be centered. Maximum frequency offset between transmit and receive reference clocks on one link. FO TP DC TR, TF DC TRCR,TRCF Frequency offset Delay from RFC to RFCO0/1 RFC0/1 duty cycle RCF0/1 rise and fall time RFC/TCi duty cycle RFC/TCi rise and fall time -200 1.97 40 0.25 35 — 200 3.58 60 1.5 65 1.5 ppm ns % ns % ns Between VIL(MAX) and VIH(MIN) Measured at 1.4V Between VIL(MAX) and VIH(MIN) Page 8 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52307-0, Rev 2.2 10/10/00 ® VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7182 DC Characteristics Parameters TTL Outputs VOH VOL IOZ TTL Inputs VIH VIL IIH IIL TTL input HIGH voltage TTL input LOW voltage TTL input HIGH current TTL input LOW current 2.0 0 — — VDD 1.1 VDD 2.0 — - 50 400 — — 50 — TTL output HIGH voltage TTL output LOW voltage TTL output Leakage current 2.4 — — — — — Quad Transceiver for Gigabit Ethernet and Fibre Channel Description Min. Typ Max. — 0.5 50 Units V V µA Conditions IOH = -1.0mA IOL = +1.0mA When set to high-impedance state through JTAG. 5V tolerant inputs VIN = 2.4V VIN = 0.5V 5.5 0.8 500 -500 VDD 0.7 VDD 1.5 200 — — V V µA µA PECL Input (RFC+/RFC-) VIH VIL IIH IIL ∆VIN PECL input HIGH voltage PECL input LOW voltage PECL input HIGH current PECL input LOW current PECL input differential peak-topeak voltage swing — — — — — V V µA µA mV VIN = VIH(MAX) VIN = VIL(MIN) VIH(MIN) - VIL(MAX) High Speed Outputs ∆VOUT75(1) ∆VOUT50(1) TX output differential peakto-peak voltage swing TX output differential peakto-peak voltage swing PECL differential peak-to-peak input voltage swing Power supply voltage Power dissipation Supply current (all supplies) Supply current on VDDA 1200 1000 — — 2200 2200 mVpp mVpp 75Ω to VDD – 2.0 V (TX+) - (TX-) 50Ω to VDD – 2.0 V (TX+) - (TX-) High-Speed Inputs ∆VIN(1) Miscellaneous VDD PD IDD IDDA 3.14 — — — — 2.2 — 100 3.47 2.67 770 — V W mA mA 3.3V + 5% Maximum at 3.47V, outputs open, 25oC, 136MHz Clk, PRBS 27-1 parallel input pattern 200 — 2600 mV SI+ - SI- NOTE: (1) Refer to Application Note, AN-37, for differential measurement techniques. G52307-0, Rev 2.2 10/10/00 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 9 ® VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet and Fibre Channel Advance Product Information VSC7182 Absolute Maximum Ratings (1) Power Supply Voltage, (VDD)............................................................................................................-0.5V to +4V DC Input Voltage (PECL inputs) ........................................................................................... -0.5V to VDD +0.5V DC Input Voltage (TTL inputs)......................................................................................................... -0.5V to 5.5V DC Output Voltage (TTL outputs) ........................................................................................ -0.5V to VDD + 0.5V Output Current (TTL outputs) .................................................................................................................... +50mA Output Current (PECL outputs)................................................................................................................... +50mA Case Temperature Under Bias...................................................................................................... -55oC to +125oC Storage Temperature .................................................................................................................... -65oC to +150oC Maximum Input ESD (human body model)................................................................................................. 2000V NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Power Supply Voltage, (VDD)................................................................................................................+3.3V+5% Operating Temperature Range .......................................................... 0oC Ambient to +100oC Case Temperature Page 10 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52307-0, Rev 2.2 10/10/00 VSC7182 G52307-0, Rev 2.2 10/10/00 1 V S ST SY N C B RCB0 RB0 RB4 RB6 VDDT VD D V SS T RC1 VDDT RC8 V SST VDDT V SST 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Table 6: Pin Table A R A9 V SS T RCB1 RB1 VDDT RB7 V SS SY N C C RC0 RC2 RC5 RC9 SYNCD RCD0 RCD1 V SST VDD ® B R A6 VDDT VDDT RB2 V SST RB8 SLPN RCC0 VDD T RC3 RC6 VDD VDDT V SST R D0 R A7 R A8 C VDDT V SS T LPND RB3 RB5 RB9 TMS RCC1 V SS T RC4 RC7 R D1 RD2 R D3 R D4 R A4 R A5 D R A2 R A3 VDDT V SST R D5 R A0 R A1 Advance Product Information E VDDT V SS T R D7 RD8 R C A0 R C A1 R D6 F V SS VDD TC2 TCB SY N C A R D9 V SS G TB6 TB7 TC6 TB8 T B9 TC1 TC0 VDDT H TB2 TB3 TB4 T B5 TC5 TC4 TC3 J V SS LPN C TB0 T B1 NOT POPULATED VDD TC9 TC8 TC7 K V SS VDD TCA TDO V SS V SS VDD TCC L T A6 TA7 T A8 T A9 TD3 TD2 TD1 TD0 VITESSE SEMICONDUCTOR CORPORATION M T A2 TA3 T A4 T A5 TD7 TD6 TD5 TD4 N R FC LPN B T AV SS TBV SS C A P0 T A0 T A1 PL U P VDD TD9 TD8 P LPNA VDD TA+ V SS TB+ V SSA LTCN RFCM VS S TC+ V SS TD+ R FC O 1 T DI R FC O 0 TCD © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com C A P1 VS S TCV SS T DVDD TRSTN VDDT R SY N C VDD VDD VDDP A V SS VDDP B V SS VDDA VS S V D D PC V SS VDDP D VDD V SS V SST R TCK R ARA+ VDD RBRB+ V SS V SS RCRC+ V SS R DR D+ V SS V SS V SS R RFCT R FC + T RCM V SS Quad Transceiver for Gigabit Ethernet and Fibre Channel U VS S V SS Page 11 ® VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet and Fibre Channel Table 7: Pin Descriptions Pin N1, N2, N3 N4, M1, M2, M3, M4, L1 L2 J1, J2, J3 J4, H1, H2 H3, H4, G1 G2 G16, G15, G14 H17, H16, H15 H14, J17, J16 J15 L17, L16, L15 L14, M17, M16 M15, M14, N17 N16 Advance Product Information VSC7182 Description Name TA0, TA1, TA2 TA3, TA4, TA5 TA6, TA7, TA8 TA9 TB0, TB1, TB2 TB3, TB4, TB5 TB6, TB7, TB8 TB9 TC0, TC1, TC2 TC3, TC4, TC5 TC6, TC7, TC8 TC9 TD0, TD1, TD2 TD3, TD4, TD5 TD6, TD7, TD8 TD9 INPUT - TTL: 10-Bit Transmit Bus for Channel A. Parallel data on this bus is latched on the rising edge of RFC, TCC or TCA. TA0 is transmitted first. INPUT - TTL: 10-Bit Transmit Bus for Channel B. Parallel data on this bus is latched on the rising edge of RFC, TCC or TCB. TB0 is transmitted first. INPUT - TTL: 10-Bit Transmit Bus for Channel C. Parallel data on this bus is latched on the rising edge of RFC or TCC. TC0 is transmitted first. INPUT - TTL: 10-Bit Transmit Bus for Channel D. Parallel data on this bus is latched on the rising edge of RFC, TCC or TCD. TD0 is transmitted first. INPUT - Differential PECL or TTL: This rising edge of RFC+/- provides the reference clock, at 1/10th or 1/20th of the baud rate (depending on RFCM) to the Clock Multiplying PLL. If RFC+/- is used, either leave RFCT open or set RFCT HIGH. Internally biased to VDD/2. If all TCi inputs are HIGH, the rising edge of RFC will latch TXi[0:9] on all four channels. INPUT - TTL: TTL Reference Clock. This rising edge of RFCT provides the reference clock, at 1/10th or 1/20th of the baud rate (depending on RFCM) to the Clock Multiplying PLL. If RFCT is used, set RFC+ HIGH and leave RFC- open. If all TCi inputs are HIGH, the rising edge of RFCT will latch TXi[0:9] on all four channels INPUT - TTL: Reference Clock Mode Select. When LOW, RFC is at 1/20th of the transmit baud rate (i.e., 62.5MHz for 1.25Gb/s). When HIGH, RFC is at 1/10th the baud rate (i.e., 125MHz for 1.25Gb/s). OUTPUT - TTL: These are identical copies of the transmit baud rate clock divided by 10. INPUT - TTL: Per Channel Transmit Byte Clock for Channel x. All four channels’ parallel TXi[0:9] inputs may be timed to RFC, TCC, or independently to TCi. Refer to the Serializer description. INPUT - TTL: Latch Transmit Byte Clocks. When LOW, internal PLLs align clocks with each of the transmit byte clocks, if present. Data may be corrupted when LOW. When HIGH, alignment will remain static regardless of actual TCi location. R2 P3 RFC+ RFC- R1 RFCT P2 P16 P14 K1, F1 K17, P17 RFCM RFCO0 RFCO1 TCA, TCB TCC, TCD P1 LTCN Page 12 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52307-0, Rev 2.2 10/10/00 ® VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7182 Pin R5, P5 R7, P7 P11, R11 P13, R13 D1, D2, E3 E4, C1, C2 C3, B1, B2 B3 A6, B6, C6 D6, A7, D7 A8, B8, C8 D8 B11, A12, B12 C12, D12, B13 C13, D13, A14 B14 C17, D14, D15 D16, D17, E16 E17, F14, F15 F16 T1 E1 E2 A5 B5 C10 D10 B16 B17 U4, U3 U7, U6 U11, U10 U14, U13 Quad Transceiver for Gigabit Ethernet and Fibre Channel Description Name TA+, TATB+, TBTC+, TCTD+, TDRA0, RA1, RA2 RA3, RA4, RA5 RA6, RA7, RA8 RA9 RB0, RB1, RB2 RB3, RB4, RB5 RB6, RB7, RB8 RB9 RC0, RC1, RC2 RC3, RC4, RC5 RC6, RC7, RC8 RC9 RD0, RD1, RD2 RD3, RD4, RD5 RD6, RD7, RD8 RD9 RCM RCA0 RCA1 RCB0 RCB1 RCC0 RCC1 RCD0 RCD1 RA+, RARB+, RBRC+, RCRD+, RD- OUTPUT - Differential PECL (AC-coupling recommended): These pins output the serialized transmit data for Channel x when PLUP is LOW. When PLUP is HIGH, TXi+ is HIGH and TXi- is LOW. OUTPUT - TTL: 10-Bit Receive Bus for Channel A. Parallel data on this bus is synchronous to RCA0 and RCA1. RA0 is the first bit received. OUTPUT - TTL: 10-Bit Receive Bus for Channel B. Parallel data on this bus is synchronous to RCB0 and RCB1. RB0 is the first bit received. OUTPUT - TTL: 10-Bit Receive Bus for Channel C. Parallel data on this bus is synchronous to RCC0 and RCC1. RC0 is the first bit received. OUTPUT - TTL: 10-Bit Receive Bus for Channel D. Parallel data on this bus is synchronous to RCD0 and RCD1. RD0 is the first bit received. INPUT - TTL: Recovered Clock MODE Control. When LOW, RCi0/RCi1 is 1/20th of the incoming baud rate. When HIGH, RCi0/RCi1 is 1/10th the incoming baud rate. OUTPUT - Complementary TTL: Recovered Complementary Clocks for Channel A at 1/10th the Incoming Baud Rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the RA(0:9) and SYNCA bus. OUTPUT - Complementary TTL: Recovered Complementary Clocks for Channel B at 1/10th the Incoming Baud Rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the RB(0:9) and SYNCB bus. OUTPUT - Complementary TTL: Recovered Complementary Clocks for Channel C at 1/10th the Incoming Baud Rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the RC(0:9) and SYNCC bus. OUTPUT - Complementary TTL: Recovered Complementary Clocks for Channel D at 1/10th the Incoming Baud Rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the RD(0:9) and SYNCD bus. INPUT - Differential PECL (AC-coupling recommended): Serial Receive Data Inputs for Channel x. These are selected when PLUP is LOW (internally biased to VDD/2). G52307-0, Rev 2.2 10/10/00 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 13 ® VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet and Fibre Channel Pin N14 Advance Product Information VSC7182 Description Name PLUP INPUT - TTL: Parallel Loopback Enable Input. RXi is input to the CRU for Channel x (normal operation) when PLUP is LOW. When HIGH, internal loopback paths from TXi to RXi are enabled. Refer to Table 2. INPUT - TTL: Serial Loopback Enable Input. Normal operation when HIGH. When LOW, SI+/- is looped back to TXi+/- internally for diagnostic purposes. Refer to Table 2 and related description. INPUT - TTL: Loopback Enable Pins. When LPNi is LOW, PLUP/SLPN impact Channel x. When HIGH, PLUP/SLPN have no effect on Channel x. INPUT - TTL: Enables SYNi and Word Alignment when HIGH. When LOW, keeps current word alignment and disables SYNi (always LOW). OUTPUT - TTL: Comma Detect for Channel x. This output goes HIGH for half of an RCi1 period to indicate that RXi[0:9] contains a “comma” character (‘0011111XXX’). SYNi will go HIGH only during a cycle when RCi0 is rising. SYNi is enabled when SYNC is HIGH. ANALOG: Loop Filter capacitor for the Clock Multiply Unit. Typically 0.1µF connected between CAP0 and CAP1. Amplitude is less than 3.3V. INPUT - TTL: JTAG Test Clock INPUT - TTL: JTAG Test Mode Select INPUT - TTL: JTAG Test Reset, Active LOW INPUT - TTL: JTAG Test Data Input OUTPUT - TTL: JTAG Test Data Output Analog Power Supply Analog Ground. Tie to common ground plane with VSS. C9 R3 P4 K4 D5 R17 F2 A4 B10 B15 P9 R9 T17 D9 R15 P15 K2 T9 R8 A2,A10,C14 G4,J14,K16 L4,N15,R4 R14,T3 T4,T14,U5 C4, D3,F3 A9, B7, C5 A13, A16, C11 C15, E14, G17 T5 T7 T11 T13 SLPN LPNA LPNB LPNC LPND SYNC SYNCA SYNCB SYNCC SYNCD CAP0 CAP1 TCK TMS TRSTN TDI TDO VDDA VSSA VDD Digital Logic Power Supply VDDT TTL Output Power Supply VDDPA VDDPB VDDPC VDDPD PECL I/O Power Supply for Channel x. Page 14 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52307-0, Rev 2.2 10/10/00 ® VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7182 Pin R16 T16 A1,A3,A11,A15 A17,B4,C7 C16,D4,D11 E15,F4 B9,F17,G3,K3, K14,K15,L3,P6, P8,P10,P12 R6,R10,R12,T2 T6,T8,T10,T12 T15,U1,U2,U8, U9,U12,U15 U16, U17 Quad Transceiver for Gigabit Ethernet and Fibre Channel Description Name VDDTR VSSTR TTL Output Power Supply for RFCO0 and RFCO1. TTL Ground for RFCO0 and RFCO1. VSST Ground for TTL Outputs VSS Ground G52307-0, Rev 2.2 10/10/00 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 15 ® VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet and Fibre Channel Advance Product Information VSC7182 Package Thermal Characteristics The VSC7182 is packaged in a 23mm BGA package with 1.27mm eutectic ball spacing. The construction of the package is shown in Figure 6. Figure 6: Package Cross Section Copper Heat Spreader Die Attach Epoxy Adhesive Die Wirebond Polyimide Dielectric Encapsulant Eutectic Solder Balls The VSC7182 is designed to operate with a case temperature up to 100oC. In order to comply with this target, the user must guarantee that the case temperature specification of 100oC is not violated. With the thermal resistances shown in Table 8, the VSC7182 can operate in still air ambient temperatures of 40oC [40 oC = 100oC - 2.5W * 24oC/W]. If the ambient air temperature exceeds these limits, some form of cooling through a heatsink or an increase in airflow must be provided. Table 8: Thermal Resistance Symbol θjc θca θca-100 θca-200 θca-400 θca-600 Description Thermal resistance from junction-to-case Thermal resistance from case-to-ambient in still air including conduction through the leads. Thermal resistance from case-to-ambient with 100 LFM airflow Thermal resistance from case-to-ambient with200 LFM airflow Thermal resistance from case-to-ambient with 400 LFM airflow Thermal resistance from case-to-ambient with 600 LFM airflow Value 4.3 24 21 18.5 17 15 Units oC/W o o C/W C/W oC/W oC/W oC/W Moisture Sensitivity Level This device is rated at with a Moisture Sensitivity Level 3 rating. Refer to Application Note AN-20 for appropriate handling procedures. Page 16 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52307-0, Rev 2.2 10/10/00 ® VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7182 Package Information Quad Transceiver for Gigabit Ethernet and Fibre Channel Pin A1 Indicator 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U 23.0 1.27 Typ BOTTOM VIEW 23.0 TOP VIEW 1.55 Typ G52307-0, Rev 2.2 10/10/00 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 17 ® VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet and Fibre Channel Advance Product Information VSC7182 Ordering Information The order number for this product is formed by a combination of the device type and package type. VSC7182 Device Type Quad Gigabit Transceiver TW Package TW: 208-Pin, 23mm BGA Notice This document contains information about a new product during its fabrication or early sampling phase of development. The information in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this data sheet is current prior to design or order placement. Warning Vitesse Semiconductor Corporation’s products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. Page 18 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52307-0, Rev 2.2 10/10/00