VSC7186TW

VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7186 Features • Four Complete Transceiver Functions in One IC • Full Gigabit Ethernet (IEEE 802.3z) Compliance • Pin-Compatible With Agilent HDMP-1686A • 5-Volt Tolerant TTL Inputs • Uses Reference Clock to Latch Tx Data • 1/10th or 1/20th Baud Rate Recovered Clocks • Common Local Loopback Control Quad Transceiver for Gigabit Ethernet • Single Comma Detect Enable • Cable Equalization in Receivers • Automatic Lock-to-Reference • JTAG Access Port • 2kV ESD Protection on All Pins • 3.3V Power Supply, 2.67 W Max Dissipation • 208 pin, 23 mm BGA Packaging General Description The VSC7186 is a Quad Gigabit Ethernet Transceiver IC. Each of the four transmitters has a 10-bit wide bus, running at 125 MHz, which accepts 8b/10b encoded transmit characters and serializes the data onto high speed differential outputs at rates between 1.05 and 1.36 Gb/s. The transmit data must be synchronous to the reference clock. Each receiver samples serial receive data, recovers the clock and data, deserializes it into 10-bit receive characters, outputs a recovered clock and detects “Comma” characters. The VSC7186 contains on-chip PLL circuitry for synthesis of the baud-rate transmit clock and extraction of the clocks from the received serial streams. VSC7186 Block Diagram (1 of 4 Channels) RXi(0:9) 10 QD Serial to Q Parallel D QD 0 Clock Recovery ÷10 Unit 1 SI+ SI- RCM RCi1 RCi0 SYNi SYNC LOOP Comma Detect SEL ÷10/ ÷20 TXi(0:9) 10 DQ Parallel to Serial DQ SO+ SO- RFC1 CAP0 CAP1 Clock Multiply Unit x10 G52306-0, Rev. 2.0 3/27/00  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet Advance Product Information VSC7186 Functional Description Notation In this document, each of the four channels are identified as Channel 0, 1, 2 or 3. When discussing a signal on any specific channel, the signal will have the Channel number embedded in the name, i.e. “T3(0:9)”. When referring to the common behavior of a signal which is used on each of the four channels, the notation “i” is used. Differential signals, i.e. SOi+ and SOi-, may be referred to as a single signal, i.e. SOi, by dropping reference to the “+” and “-”. Clock Synthesizer The VSC7186 Clock Multiplier Unit (CMU) multiplies the reference frequency provided on the RFC1 input by 10 to achieve a baud rate clock between 1.05 and 1.36 GHz. The RFC1 input is TTL. The on-chip PLL uses a single external 0.1uF capacitor, connected between CAP0 and CAP1, to control the Loop Filter. This capacitor should be a multilayer ceramic dielectric, or better, with at least a 5V working voltage rating and a good temperature coefficient, i.e., NPO is preferred but X7R may be acceptable. These capacitors are used to minimize the impact of common mode noise on the Clock Multiplier Unit, especially power supply noise. Higher value capacitors provide better robustness in systems. NPO is preferred because if an X7R capacitor is used, the power supply noise sensitivity will vary with temperature. For best noise immunity, the designer may use a three capacitor circuit with one differential capacitor between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to ground, C3. Larger values are better but 0.1uF is adequate. However, if the designer cannot use a three capacitor circuit, a single differential capacitor, C1, is adequate. These components should be isolated from noisy traces. Figure 1: Loop Filter Capacitors (Best Circuit) CAP0 C2 C1 C3 VSC7186 CAP1 C1=C2=C3= >0.1uF MultiLayer Ceramic Surface Mount NPO (Prefered) or X7R 5V Working Voltage Rating Serializer The VSC7186 accepts TTL input data as four parallel 10 bit characters on the Ti(0:9) buses which are latched into the input registers on the rising edge of RFC1. The 10-bit parallel transmission character will be serialized and transmitted on the SOi+/- PECL differential outputs at the baud rate with bit Ti0 (bit a) transmitted first. User data should be encoded using 8b/10b or an equivalent code. The mapping to 10b encoded bit nomenclature and transmission order is illustrated below, along with the recognized comma pattern. Page 2  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52306-0, Rev. 2.0 3/27/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7186 Table 1: Transmission Order and Mapping of a 10b Character Quad Transceiver for Gigabit Ethernet Data Bit 10B Bit Position Comma Character T9 j x T8 h x T7 g x T6 f 1 T5 i 1 T4 e 1 T3 d 1 T2 c 1 T1 b 0 T0 a 0 Clock Recovery The VSC7186 accepts differential high speed serial input from the selected source (either the PECL SIi+/pins or the internal SOi+/- data), extracts the clock and retimes the data. Equalizers are included in the receiver to open the data eye and compensate for Intersymbol Interference (ISI) which may be present in the incoming data. The serial bit stream should be encoded so as to provide DC balance and limited run length by an 8b/10b encoding scheme. The digital Clock Recovery Unit (CRU) is completely monolithic and requires no external components. For proper operation, the baud rate of the data stream to be recovered should be within +200 ppm of ten times the REF frequency. For example, Gigabit Ethernet systems use 125 MHz oscillators with a +/100ppm accuracy resulting in +/-200 ppm between VSC7186 pairs. Deserializer The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7186 provides complementary TTL recovered clocks, RCi0 and RCi1, at one-twentieth of the serial baud rate if RCM=LOW, or a single clock at one-tenth the serial baud rate, on RCi1 only, if RCM=HIGH. The clocks are generated by dividing down the high-speed recovered clock which is phase locked to the serial data. The serial data is retimed, deserialized and output on Ri(0:9). If serial input data is not present, or does not meet the required baud rate, the VSC7186 will continue to produce a recovered clock so that downstream logic may continue to function. The RCi0/RCi1 output frequency under these circumstances will differ from its expected frequency by no more than +1%. Word Alignment The VSC7186 provides 7-bit comma character recognition and data word alignment. Word synchronization is enabled on all channels by asserting SYNC HIGH. When synchronization is enabled, the receiver examines the recovered serial data for the presence of the “Comma” pattern. This pattern is “0011111XXX”, where the leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8b/10b coded data character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and K28.7, which are defined for synchronization purposes. Improper comma alignment is defined as any of the following conditions: 1) The comma is not aligned within the 10-bit transmission character such that Ri(0..6) = “0011111”. 2) The comma straddles the boundary between two 10-bit transmission characters. 3) The comma is properly aligned but occurs in the received character presented during the rising edge of RCi0 rather than RCi1. When an improperly aligned comma is encountered, the recovered clock is stretched, never slivered, so that the comma character and recovered clocks are aligned properly to Ri(0:9). This results in proper character and word alignment. When the parallel data alignment changes in response to a improperly aligned comma pattern, G52306-0, Rev. 2.0 3/27/00  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet Advance Product Information VSC7186 data which would have been presented on the parallel output port prior to the comma character, and possibly the comma character itself, may be lost. Possible loss of the comma character is data dependent, according to the relative change in alignment. Data subsequent to the comma character will always be output correctly and properly aligned. On encountering a comma character, SYNi is driven HIGH. The SYNi pulse is presented simultaneously with the comma character and has a duration equal to the data. The SYNi signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of RCi1. Functional waveforms for synchronization are given in Figure 1. The first K28.5 shows the case where the comma is detected, but it is misaligned so a change in the output data alignment is required. Note that up to three characters prior to the comma character may be corrupted by the realignment process. The second K28.5 shows the case when a comma is detected and no phase adjustment is necessary. It illustrates the position of the SYNi pulse in relation to the comma character on Ri(0:9). Figure 2: Misaligned and Aligned K28.5 Characters RCi0 (RCM LOW) RCi1 RCi0 (RCM HIGH) RCi1 SYNi RXi(0:9) Data Corrupt Corrupt Corrupt K28.5 Data1 Data2 Data3 K28.5 Misaligned Comma: Stretched Aligned Comma Loopback Operation Loopback operation is controlled by the LOOP line. When this line is HIGH, the outgoing high-speed serial data on each of the four channels is internally looped back into that channel’s high-speed serial receiver section. This provides for in-circuit testing capability independent of the transmission medium. JTAG Access Port A JTAG access port is provided to assist in board-level testing. Through this port most pins can be accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this device is available in “VSC7186 JTAG Access Port Functionality”. Circuits designed exclusively for the HDMP-1686A will automatically disable the JTAG port. The pinout table in this data sheet shows the proper connections for either HDMP-1686A emulation or for JTAG functionality (in parentheses).  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 4 G52306-0, Rev. 2.0 3/27/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7186 AC Characteristics Figure 3: Transmit Timing Waveforms Quad Transceiver for Gigabit Ethernet RFC1 T1 T2 TXi(0:9) 10 Bit Data Data Valid Data Valid Data Valid +/-SOi TLAT S0 S1 S2 RFC1 Table 2: Transmitter AC Characteristics Parameter T1 T2 TSDR,TSDF TLAT Description Ti(0:9) Setup time to the rising edge of RFC1 Ti(0:9) hold time after the rising edge of RFC1 Ti+/Ti- rise and fall time Latency from rising edge of RFC1 to Ti0 appearing on SO bit 0i Min 1.5 1.0 — 7bc + 0.66ns Typ — — — — Max — — 300 7bc + 1.46ns Units ns. ns. ps. Note: Conditions Measured between the valid data level of Ti(0:9) to the 1.4V point of RFC1 20% to 80%, 75 Ohm load to Vdd/ 2, Tested on a sample basis bc = bit clocks ns = nanoseconds Transmitter Output Jitter RJ DJ Random jitter (RMS) Serial data output deterministic jitter (pk-pk) — — 5 35 8 80 ps. ps. Measured at SO+/-, 1 sigma deviation of 50% crossing pt IEEE 802.3Z Clause 38.68, Tested on a sample basis G52306-0, Rev. 2.0 3/27/00  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet Advance Product Information VSC7186 Figure 4: Receive Timing Waveforms RCi0 RCM=LOW RCi1 RCi0 RCM=HIGH RCi1 T1 T2 VALID VALID RXi(0:9) SYNi VALID +/-SIi S0 S1 S2 RLAT RCi1 Table 3: Receive AC Characteristics— Parameters T1 T2 T3 T4 TR, TF TLOCK Description TTL Outputs Valid prior to RCi1/RCi0 rise TTL Outputs Valid after RCi1 or RCi0 rise Delay between rising edge of RCi1 to rising edge of RCi0 Period of RCi1 and RCi0 TTL Output rise and fall time Data acquisition lock time* Latency from bit 0 of RXi0 appearing on SI to rising edge of RCi1 Min. 3.0 2.0 10 x TRi -500 1.98 x TREF — — 12bc + 2.77ns Max. — — 10 x TRi +500 2.02 x TREF 2.4 1400 13bc + 7.28 Units ns. ns. ps. ps. ns. bit times Note: Conditions @ 1.25Gb/s @ 1.25Gb/s TRi is the bit period of the incoming data on Ri. Whether or not locked to serial data. Between VIL(max) and VIH(min), into 10 pf. load. 8b/10b IDLE pattern. Tested on a sample basis bc = bit clocks ns = nanoseconds. RLAT * Note: Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3 Page 6  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52306-0, Rev. 2.0 3/27/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7186 Figure 5: RFC1 Waveform Quad Transceiver for Gigabit Ethernet TL RFC1 TH VIH(MIN) VIL(MAX) Table 4: Reference Clock Requirements Parameters Description Min Max Units Conditions Range over which both transmit and receive reference clocks on any link may be centered Maximum frequency offset between transmit and receive reference clocks on one link Measured at 1.4V Between VIL(max) and VIH(min) FR Frequency Range 105 136 MHz FO DC TRCR,TRCF Frequency Offset RFC1 duty cycle RFC1 rise and fall time -200 200 ppm. 35 — 65 1.5 % ns. G52306-0, Rev. 2.0 3/27/00  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet Advance Product Information VSC7186 DC Characteristics Parameters TTL Outputs VOH VOL IOZ TTL Inputs VIH VIL IIH IIL ∆VOUT75(1) ∆VOUT50(1) TTL input HIGH voltage TTL input LOW voltage TTL input HIGH current TTL input LOW current 2.0 0 — — — — 50 — 5.5 0.8 500 -500 V V µA µA mVpp mVpp VIN =2.4V VIN =0.5V 5V Tolerant Inputs TTL output HIGH voltage TTL output LOW voltage TTL output Leakage current 2.4 — — — — — — 0.5 50 V V µA IOH = -1.0mA IOL = +1.0mA When set to high-impedance state through JTAG. Description Min. Typ Max. Units Conditions High Speed Outputs TX Output differential peakto-peak voltage swing Ti Output differential peakto-peak voltage swing PECL differential peak-to-peak input voltage swing Power supply voltage Power dissipation Supply current (All Supplies) Supply current on VDDA 1200 1000 — — 2200 2200 75Ω to VDD – 2.0 V (Ti+) - (Ti-) 50Ω to VDD – 2.0 V (Ti+) - (Ti-) High Speed Inputs ∆VIN(1) Miscellaneous VDD PD IDD IDDA 3.14 — — — — 2.2 — 100 3.47 2.67 770 — V W mA mA 3.3V + 5% Maximum at 3.47V, Outputs Open, 25oC, 136MHz Ck, PRBS 27-1 parallel input pattern 200 — 2600 mV Ri+ - Ri- Note: (1) Refer to Application Note, AN-37, for differential measurement techniques. Page 8  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52306-0, Rev. 2.0 3/27/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7186 Absolute Maximum Ratings (1) Quad Transceiver for Gigabit Ethernet Power Supply Voltage, (VDD) ............................................................................................................-0.5V to +4V DC Input Voltage (PECL inputs)............................................................................................ -0.5V to VDD +0.5V DC Input Voltage (TTL inputs) ......................................................................................................... -0.5V to 5.5V DC Output Voltage (TTL Outputs)........................................................................................ -0.5V to VDD + 0.5V Output Current (TTL Outputs) ................................................................................................................. +/-50mA Output Current (PECL Outputs)................................................................................................................+/-50mA Case Temperature Under Bias .........................................................................................................-55o to +125oC Storage Temperature..................................................................................................................... -65oC to +150oC Maximum Input ESD (Human Body Model).............................................................................................. 2000 V Recommended Operating Conditions Power Supply Voltage, (VDD) ................................................................................................................+3.3V+5% Operating Temperature Range ........................................................... 0oC Ambient to +100oC Case Temperature Notes: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. G52306-0, Rev. 2.0 3/27/00  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 9 Quad Transceiver for Gigabit Ethernet Page 10 1 GNDT SYN1 RC10 RX10 RX14 RX16 VCCT VCC GNDT RX21 VCCT RX28 GNDT VCCT GNDT 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Table 5: Pin Table A RX09 GNDT RC11 RX11 VCCT RX17 GND SYN2 RX20 RX22 RX25 RX29 SYN3 RC30 RC31 GNDT VCC B RX06 VCCT VCCT RX12 GNDT RX18 NC RC20 VCCT RX23 RX26 VCC VCCT GNDT RX30 RX07 RX08 C VCCT GNDT GND RX13 RX15 RX19 NC (TMS) RC21 GNDT RX24 RX27 RX31 RX32 RX33 RX34 RX04 RX05 D RX02 RX03 VCCT GNDT RX35 RX00 RX01 E VCCT GNDT RX37 RX38 RC00 RC01 RX36 F GND VCC TX22 NC SYN0 RX39 GND G TX16 TX17 TX26 TX18 TX19 TX21 TX20 VCCT H TX12 TX13 TX14 TX15 TX25 TX24 TX23 J GND GND TX10 TX11 NOT POPULATED VCC TX29 TX28 TX27 K GND VCC NC NC (TDO) GND GND VCC NC L TX06 TX07 TX08 TX09 TX33 TX32 TX31 TX30 VITESSE SEMICONDUCTOR CORPORATION M TX02 TX03 TX04 TX05 TX37 TX36 TX35 TX34 N NC SO0GND SO1GND GND CAP0 TX00 TX01 LOOP VCC TX39 TX38 P GND SO0+ GND SO1+ GNDA VCC NC NC GND SO2+ GND SO3+ GND NC (TDI) NC NC  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 CAP1 GND SO2GND SO3VCC GND (TRSTN) VCCTR SYNC VCC VCC VCCP0 GND VCCP1 GND VCCA GND VCCP2 GND VCCP3 VCC GND GNDTR NC (TCK) SI0SI0+ VCC SI1SI1+ GND GND SI2SI2+ GND SI3SI3+ GND GND GND R RFC1 NC T RCM0 GND Advance Product Information VSC7186 G52306-0, Rev. 2.0 3/27/00 U GND GND VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7186 Table 6: Pin Description Pin N1, N2, N3 N4, M1, M2, M3, M4, L1 L2 J1, J2, J3 J4, H1, H2 H3, H4, G1 G2 G16, G15, G14 H17, H16, H15 H14, J17, J16 J15 L17, L16, L15 L14, M17, M16 M15, M14, N17 N16 Quad Transceiver for Gigabit Ethernet Name TX0-0, TX0-1, TX0-2 TX0-3, TX0-4, TX0-5, TX0-6, TX0-7, TX0-8 TX0-9 TX1-0, TX1-1, TX1-2 TX1-3, TX1-4, TX1-5, TX1-6, TX1-7, TX1-8, TX1-9 TX2-0, TX2-1, TX2-2 TX2-3, TX2-4, TX2-5, TX2-6, TX2-7, TX2-8, TX2-9 TX3-0, TX3-1, TX3-2, TX3-3, TX3-4, TX3-5, TX3-6, TX3-7, TX3-8, TX3-9 RFC1 SO0+, SO0SO1+, SO1SO2+, SO2SO3+, SO3RX0-0, RX0-1, RX0-2, RX0-3, RX0-4, RX0-5, RX0-6, RX0-7, RX0-8, RX0-9 RX1-0, RX1-1, RX1-2, RX1-3, RX1-4, RX1-5, RX1-6, RX1-7, RX1-8, RX1-9 RX2-0, RX2-1, RX2-2, RX2-3, RX2-4, RX2-5, RX2-6, RX2-7, RX2-8, RX2-9 Description INPUT - TTL: 10-bit Transmit bus for Channel 0. Parallel data on this bus is latched on the rising edge of REF. TX0-0 is transmitted first. INPUT - TTL: 10-bit Transmit bus for Channel 1. Parallel data on this bus is latched on the rising edge of REF. TX1-0 is transmitted first. INPUT - TTL: 10-bit Transmit bus for Channel 2. Parallel data on this bus is latched on the rising edge of REF. TX2-0 is transmitted first. INPUT - TTL: 10-bit Transmit bus for Channel 3. Parallel data on this bus is latched on the rising edge of REF. TX3-0 is transmitted first. INPUT - TTL: TTL Reference clock. This rising edge of RFC1 provides the reference clock, at 1/10th of the baud rate to the Clock Multiplying PLL. The rising edge of RFC1 will latch TXi(0:9) on all four channels OUTPUT - Differential PECL (AC Coupling recommended) These pins output the serialized transmit data for Channels 0-3 when LOOP is LOW. When LOOP is HIGH, SOi+ is HIGH and SOi- is LOW. R1 R5, P5 R7, P7 P11, R11 P13, R13 D1, D2, E3 E4, C1, C2 C3, B1, B2 B3 A6, B6, C6 D6, A7, D7 A8, B8, C8 D8 B11, A12, B12 C12, D12, B13 C13, D13, A14 B14 OUTPUT - TTL: 10-bit Receive bus for Channel 0. Parallel data on this bus is synchronous to RC0-0 and RC0-1. RX0-0 is the first bit received. OUTPUT - TTL: 10-bit Receive bus for Channel 1. Parallel data on this bus is synchronous to RC1-0 and RC1-1. RX1-0 is the first bit received. OUTPUT - TTL: 10-bit Receive bus for Channel 2. Parallel data on this bus is synchronous to RC2-0 and RC2-1. RX2-0 is the first bit received. G52306-0, Rev. 2.0 3/27/00  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet Pin C17, D14, D15 D16, D17, E16 E17, F14, F15 F16 Advance Product Information VSC7186 Name Description RX3-0, RX3-1, RX3-2, RX3-3, RX3-4, RX3-5, RX3-6, RX3-7, RX3-8, RX3-9 RCM0 OUTPUT - TTL: 10-bit Receive bus for Channel 3. Parallel data on this bus is synchronous to RC3-0 and RC3-1. RX3-0 is the first bit received. INPUT - TTL: Recovered clock MODE control. When LOW, RCi0/RCi1 is 1/20th of the incoming baud rate. When HIGH, RCi0/RCi1 is 1/10th the incoming baud rate. OUTPUT - Complementary TTL: Recovered complementary clocks for Channel 0 at 1/10th the incoming baud rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the RX0(0:9) bus and SYN0. OUTPUT - Complementary TTL: Recovered complementary clocks for Channel 1 at 1/10th the incoming baud rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the RX1(0:9) bus and SYN1. OUTPUT - Complementary TTL: Recovered complementary clocks for Channel 2 at 1/10th the incoming baud rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the RX20:9) bus and SYN2. OUTPUT - Complementary TTL: Recovered complementary clocks for Channel 3 at 1/10th the incoming baud rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the RX3(0:9) bus and SYN3. INPUT - Differential PECL (AC Coupling recommended): Serial receive data inputs for Channels 0-3 which are selected when LOOP is LOW. [Internally biased to VDD/2] INPUT - TTL: Parallel Loopback Enable input. SIi is input to the CRU for Channel i (normal operation) when LOOP is LOW. When HIGH, internal loopback paths from SOi to SIi are enabled. INPUT - TTL: Enables SYNi and word alignment when HIGH. When LOW, keeps current word alignment and disables SYNi (always LOW). OUTPUT - TTL: Comma Detect for Channel i. This output goes HIGH for half of an RCi1 period to indicate that RXi(0:9) contains a Comma Character (‘0011111XXX’). SYNi will go HIGH only during a cycle when RCi0 is rising. SYNi is enabled when SYNC is HIGH. ANALOG: Loop Filter capacitor for the Clock Multiply Unit. Typically 0.1 uF connected between CAP0 and CAP1. Amplitude is less than 3.3V. (INPUT - TTL: JTAG Test Clock) (INPUT - TTL: JTAG Test Mode Select) (INPUT - TTL: JTAG Test Reset, Active Low) (INPUT - TTL: JTAG Test Data Input) T1 E1 E2 A5 B5 C10 D10 B16 B17 U4, U3 U7, U6 U11, U10 U14, U13 N14 RC00 RC01 RC10 RC11 RC20 RC21 RC30 RC31 SI0+, SI0SI1+, SI1SI2+, SI2SI3+, SI3LOOP R17 F2 A4 B10 B15 P9 R9 T17 D9 R15 P15 SYNC SYN0 SYN1 SYN2 SYN3 CAP0 CAP1 NC (TCK) NC (TMS) GND (TRSTN) NC (TDI) Page 12  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52306-0, Rev. 2.0 3/27/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7186 Pin K2 T9 R8 A2,A10,C14 G4,J14,K16 L4,N15,R4 R14,R16,T3 T4,T14,U5 C4, D3,F3 A9, B7, C5 A13, A16, C11 C15, E14, G17 T5 T7 T11 T13 A1,A3,A11,A15 A17,B4,C7 C16,D4,D11 E15,F4 B9,F17,G3,K3, K14,K15,L3,P6, P8,P10,P12,P14 R6,R10,R12,T2 T6,T8,T10,T12 T15,T16,U1,U2, U8,U9,U12,U15 U16, U17 Quad Transceiver for Gigabit Ethernet Description Name NC (TDO) VCCA GNDA (OUTPUT - TTL: JTAG Test Data Output) Analog Power Supply Analog Ground. Tie to common ground plane with GND. VCC Digital Logic Power Supply VCCT TTL Output Power Supply. VCCP0 VCCP1 VCCP2 VCCP3 PECL I/O Power Supply for Channel i. GNDT Ground for TTL Outputs GND Ground G52306-0, Rev. 2.0 3/27/00  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet Advance Product Information VSC7186 Package Thermal Characteristics The VSC7186 is packaged in a 23 mm BGA package with 1.27mm eutectic ball spacing. The construction of the package is shown below. Figure 6: Package Cross Section Adhesive Copper Heat Spreader Die Attach Epoxy Die Wirebond Polyimide Dielectric Encapsulant Eutectic Solder Balls The VSC7186 is designed to operate with a case temperature up to 100oC. In order to comply with this target, the user must guarantee that the case temperature specification of 100oC is not violated. With the Thermal Resistances shown below, the VSC7186 can operate in still air ambient temperatures of 40oC [ 40oC = 100oC - 2.5W * 24oC/W ]. If the ambient air temperature exceeds these limits then some form of cooling through a heatsink or an increase in airflow must be provided. Table 7: Thermal Resistance Symbol Description Thermal resistance from junction to case Thermal resistance from case to ambient in still air including conduction through the leads. Thermal resistance from case to ambient with 100 LFM airflow Thermal resistance from case to ambient with200 LFM airflow Thermal resistance from case to ambient with 400 LFM airflow Thermal resistance from case to ambient with 600 LFM airflow Value 4.3 24 21 18.5 17 15 Units o o o o o o θjc θca θca-100 θca-200 θca-400 θca-600 C/W C/W C/W C/W C/W C/W Moisture Sensitivity Level This device is rated at with a Moisture Sensitivity Level 3 rating. Refer to Application Note AN-20 for appropriate handling procedures. Page 14  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52306-0, Rev. 2.0 3/27/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7186 Package Information Quad Transceiver for Gigabit Ethernet Pin A1 Indicator 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U 23.0 1.27 Typ BOTTOM VIEW 23.0 TOP VIEW 1.55 Typ G52306-0, Rev. 2.0 3/27/00  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION Quad Transceiver for Gigabit Ethernet Advance Product Information VSC7186 Ordering Information The part number for this product is formed by a combination of the device number and the package style: VSC7186TW Device Type: VSC7186: Quad Gigabit Transceiver Package Style TW: 208 pin, 23 mm BGA Marking Information The package is marked with three lines of text as shown below. Figure 7: Package Marking Information Pin A1 Identifier VITESSE Part Number DateCode VSC7186TW ####AAAA Package Suffix Lot Tracking Code Notice This document contains information about a product during its fabrication or early sampling phase of development. The information contained in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this data sheet is current prior to design or order placement. Warning Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. Page 16  VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52306-0, Rev. 2.0 3/27/00