VSC8062QH

VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8061/VSC8062 Features • Serial Data Rate up to 2.5Gb/s • 16-Bit Wide ECL 100K Compatible Parallel Data Interface • Differential High-Speed Data Outputs 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset • Power Dissipation: VSC8061:2.0W(max), VSC8062: 1.7W(max) • Standard ECL Power Supplies: VEE = -5.2V, VTT = -2.0V o o o • Differential or Single-Ended High-Speed Data and • Commercial (0 C to +70 C) or Industrial (-40 C o to +85 C) Temperature Range Clock Inputs • On-Chip Phase Detector (VSC8061 Multiplexer) • Available in 52-Pin Ceramic Leaded Chip Carrier or 52-Pin Plastic Quad Flat Pack Packages Functional Description The VSC8061 and VSC8062 are high-speed interface devices capable of data rates up to 2.5Gb/s. The devices are fabricated in gallium arsenide using the Vitesse H-GaAs E/D MESFET process to achieve highspeed and low power dissipation. For ease of system design using these products, both devices use industrystandard -5.2V and -2V power supplies, and have ECL-compatible I/O for parallel data interfaces. Typical applications include telecommunication transmission and instrumentation. VSC8061 Multiplexer The VSC8061 consists of a 16:1 multiplexer circuit, a phase detector, and a timing circuit which generates a divide-by-16 clock from the high-speed clock input. The 16:1 multiplexer accepts 16 parallel single-ended ECL compatible inputs (D0...D15) at data rates up to 156Mb/s and bitwise serializes them into a 2.5Gb/s serial output (DO/DON). The internal timing of the VSC8061 is referenced to the negative going edge of the highspeed clock true input (CLK). This clock is divided by 16 and is provided as an output (CLK16/CLK16N). The setup and hold time of the parallel inputs (D[0:15]) are specified with respect to the falling edge of CLK16, so that CLK16/CLK16N can be used to clock the data source of D[0:15]. The on-chip phase detector monitors the phase relationship between the internally generated divide-by-16 clock and an externally supplied low-speed reference clock input (DCLK/DCLKN). Phase difference between these two clock signals generates an up or down output (U, D) for phase lock applications. The phase detector can be used as part of an external Phase Locked Loop (PLL) to implement a clock multiplication function. In applications where a 2.5GHz system clock is provided, and the phase detector function is not required, it is recommended to connect one side of the DCLK/DCLKN input to VTT through a 50Ω resistor. The U and D output can be left open and unused. VSC8062 Demultiplexer The VSC8062 consists of a 1:16 demultiplexer and timing circuitry which generates a divide-by-16 clock from the high-speed clock input. The demultiplexer accepts a serial data stream input (DI/DIN) at up to 2.5Gb/s and deserializes it into 16 parallel single-ended ECL compatible outputs (D[0:15]) at data rates up to 156 Mb/s. The internal timing of the VSC8062 is referenced to the negative going edge of the high-speed clock true input (CLK). This clock is divided by 16 and provided as an output (CLK16/ CLK16N). The timing parameters of the parallel data outputs (D[0:15]) are specified with respect to the falling edge of CLK16, so that CLK16/CLK16N can be used to clock the destination of D[0:15]. G52069-0, Rev 4.3 05/11/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Figure 1: VSC8061 Block Diagram D0 16:1 D1 Parallel Data Receivers D15 Input Registers Timing Generator Multiplexer Output Register Data Sheet VSC8061/VSC8062 DO DON CLK16 CLK16N CLK CLKN DCLK DCLKN Bit Rate Clock Phase Detector U D Figure 2: VSC8062 Block Diagram D0 DI DIN Input Register DeMultiplexer 1:16 D1 Parallel Data Outputs D15 Output Registers CLK CLKN Timing Generator CLK16 CLK16N Page 2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52069-0, Rev 4.3 05/11/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8061/VSC8062 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset VSC8061 Multiplexer AC Characteristics (Over recommended operating range) Figure 3: VSC8061 Multiplexer Waveforms tCLK High-speed differential clock input tD CLK (CLKN) CLK16 (CLK16N) Parallel data clock output tDSU tDH D[0:15] Parallel data inputs VALID DATA (1) VALID DATA (2) DCLK (DCLKN) Parallel data clock input tD DO (DON) High-speed differential serial data output D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Serialized Data NOTE: =Don’t care tD Table 1: VSC8061 AC Characteristics Parameter tCLK tD tDSU tDH tDC tR, tF tR, tF tR, tF tR, tF Clock period(1) Description CLK16, DCLK period (tCLK x 16) Parallel data set-up time with respect to CLK16 falling edge Data hold time with respect to CLK16 falling edge CLK16 duty cycle DCLK (DCLKN) rise and fall times D[0:15] rise and fall times CLK16 (CLK16N) rise and fall times DO (DON) rise and fall times Min 400 6.4 2.0 0.5 40 Typ Max 15.6 Units ps ns ns ns Conditions 60 1.5 2.0 0.5 150 1.0 165 % ns ns ns ps 10% to 90% 10% to 90% 10% to 90% 20% to 80% NOTE: (1) Devices are guaranteed to operate to a maximum frequency of 2.5GHz. G52069-0, Rev 4.3 05/11/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Data Sheet VSC8061/VSC8062 VSC8061 Phase Detector Logic Diagram The internal phase detector of the VSC8061 compares the phase difference between the internally generated divide-by-16 clock and the DCLK input. If both inputs (CLK16 and DCLK) to the phase detector are in phase, the U and D outputs will both be low. If the rising edge of CLK16 precedes DCLK, a series of pulses with pulse widths proportional to the phase difference will be present at the U output. Conversely, if DCLK precedes CLK16, then a series of pulses with widths proportional to the phase difference will be present at the D output. The other output will remain low. The Phase Detector ignores phase differences for falling edges. This circuitry is useful for implementing a Clock Multiplier Unit (CMU) function with the VSC8061. For example, the DLCK can be the system reference clock at the parallel data rate. An external Voltage Controlled Oscillator (VCO) at 16x the frequency of the reference clock can be used as the CLK input for the VSC8061. The phase detector outputs (U and D) can then be used by an external integrator to generate an output that controls the VCO. The generated 16x clock from the VCO will be phase-locked to the reference clock. Figure 4: VSC8061 Phase Detector Logic Diagram CLK16 RQ S S RQ DCLK U D Figure 5: Phase Detector Input and Output Waveforms CLK16 DCLK U D Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com ~~ ~~ ~~ ~~ G52069-0, Rev 4.3 05/11/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8061/VSC8062 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset VSC8062 Demultiplexer AC Characteristics (Over recommended operating range) Figure 6: VSC8062 Timing Diagram CLK (CLKN) High-speed differential clock input tCLK DI (DIN) High-speed serial data input CLK16 Parallel data clock output tD tBD tD Demultiplexed Parallel Data Outputs D0 D1 D15 Table 2: VSC8062 AC Characteristics Parameter tCLK tD tDSU Clock period(1) BYTE CLK16 period (tCLK x 16) CLK16 falling edge output to valid data t SU + t H Phase Margin =  1 – ------------------  × 360 °  t CLK  Serial data phase timing margin with respect to high-speed clock(2) Description Min 400 6.4 1.0 Typ Max Units ps ns Conditions 3.0 ns tDH 180(3) degrees NOTES: (1) If tCLK changes, all remaining parameters change as indicated by the equations. (2) tSU and tH are setup and hold times of the serial data input register. (3) At tCLK = 400ps. G52069-0, Rev 4.3 05/11/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 5 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Data Sheet VSC8061/VSC8062 DC Characteristics Table 3: ECL Inputs and Outputs (Over recommended operating conditions with internal V REF, VCC = GND, output load = 50Ω to -2.0V). Parameter VOH VOL VIH VIL ∆VECLOUT ∆VECLIN Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Output voltage swing Input voltage swing Min -1100 VTT -1040 VTT 0.850 0.600 Typ Max -700 -1750 -600 -1600 Units mV mV mV mV V Conditions VIN = VIH (max) or VIL (min) VIN = VIH (max) or VIL (min) Guaranteed HIGH signal for all inputs Guaranteed LOW signal for all inputs Output load 50Ω to VTT AC-coupled 0.800 1.2 V Note: Differential ECL output pins must be terminated identically. Table 4: Power Dissipation (Over recommended operating conditions, V CC= GND, outputs open circuit) Parameter IEE ITT PD Description Power supply current from VEE Power supply current from VTT Power dissipation VSC8061 VSC8062 VSC8061 VSC8062 VSC8061 VSC8062 Min Typ Max 260 220 260 230 2.0 1.7 Units mV mV mV mV W W Conditions Table 5: High-Speed Input and Output Specifications (Over recommended operating conditions, V CC = GND, output load = 50Ω to -2.0V) Parameter ∆VHSOUT ∆VHSIN tR, tF Description Output voltage swing Input voltage swing Input voltage rise and fall time (high-speed) Min 0.7 Typ 0.9 Max Units V Conditions Output load, 50Ω to -2.0V AC-coupled Same for all data rates; no worse than sine wave at max speed See Table 6 0.2 1.5 ns NOTES: (1) Built-in references generator, the high-speed inputs are designed for AC-coupling. (2) If a high-speed input is driven single-ended, a capacitor should be connected between the unused high-speed or complement input and VTT (see Figures 7 and 8). Page 6 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52069-0, Rev 4.3 05/11/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8061/VSC8062 Absolute Maximum Ratings(1) 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Power Supply Voltage (VTT) ............................................................................................................ -3.0V to 0.5V Power Supply Voltage (VEE) ................................................................................................. VTT + 0.7V to -7.0V Input Voltage Applied (2) (VECLIN) .................................................................................................. -2.5V to 0.5V High-Speed Input Voltage Applied (2) (VHSIN) ............................................................... VEE-0.7V to VCC +0.7V Output Current, IOUT (DC, output HI) ........................................................................................................ -50mA Case Temperature Under Bias (TC)................................................................................................ -55oC to 125oC Storage Temperature (TSTG) .......................................................................................................... -65oC to 150oC NOTES: (1) Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. (2) VTT must be applied before the magnitude of any input signal voltage (|VIN|, |VHSIN|) can be greater than |VTT - 0.5V|. Recommended Operating Conditions Power Supply Voltage (VTT) .................................................................................................................-2.0V ± 5 % Power Supply Voltage (VEE) .................................................................................................................-5.2V ± 5 % Operating Temperature Range(1) (T)............................(Commercial) 0oC to +70oC, (Industrial) -40oC to +85oC NOTE: (1) Lower limit of specification is ambient temperature and upper limit is case temperature. ESD Ratings For performance considerations, minimum ESD protection is provided for the high-speed input pins. Therefore, proper procedures should be used when handling these products. The VSC8061/8062 are rated to the following ESD voltages based on the human body model: 1. All high-speed input pins are rated at or above 500V. 2. All other pins are rated at or above 2000V. The above ratings apply to both “F” and “QH” packages. G52069-0, Rev 4.3 05/11/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 7 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Data Sheet VSC8061/VSC8062 Coupling for Inputs Figure 7: AC-Coupling for DCLK, DCLKN Inputs Chip Boundary VCC = GND ZO CIN DCLK -1.32V -1.32V RT = ZO R| | = 1kΩ VTT CSE VTT CIN typ = 0.1 µF CSE typ = 0.1µF for single-ended applications (Capacitor values are selected for DCLK = 155Mb/s.) DCLKN VTT = -2V DCLK, DCLKN Inputs Internal biasing will position the reference voltage of approximately -1.32V on both the true and complement inputs. This input can either be DC-coupled or AC-coupled; it can also be driven single-ended or differentially. Figure 7 shows the configuration for a single-ended, AC-coupling operation. In the case of direct coupling and single-ended input, it is recommended that a stable VREF for ECL levels be used for the complementary input. High-Speed Clock and Serial Data Inputs It is recommended that all high-speed clock and serial data inputs (CLK/CLKN for the VSC8061; DI/DIN and CLK/CLKN for the VSC8062) be AC-coupled. Figure 8 shows the configuration for a single-ended ACcoupling operation. In most situations, these inputs will have high transition density and little DC offset. However, in cases where this does not hold, direct DC connection is possible. The following is to assist in this application. All serial data and clock inputs have the same circuit topology, as shown in Figure 8. The reference voltage is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DC-coupling operations, it is recommended the user provide an external reference voltage which has better temperature and power supply noise rejection than the on-chip resistor divider. The external reference should have a nominal value as indicated in the table and can be connected to either side of the differential gate. Page 8 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52069-0, Rev 4.3 05/11/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8061/VSC8062 Table 6: High-Speed Clock and Serial Data Inputs Product VSC8061 VSC8061 VSC8062 VSC8062 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Input DCLK, DCLKN CLK, CLKN DI, DIN CLK, CLKN Reference -1.32V -3.5V -3.5V -3.5V Min (p-p) 600mV 600mV 250mV 250mV Max (p-p) 1.2V 1.2V 1.2V 1.2V Figure 8: High-Speed Clock and Serial Data Inputs Chip Boundary VCC = GND ZO CIN CLK, DI -3.5V -3.5V RT = ZO R| | = 1.3kΩ VTT CSE VTT CLKN, DIN VEE = -5.2V CIN typ = 100pF CSE typ = 100pF for single-ended applications (Capacitor values are selected for DI = 2.5Gb/s.) G52069-0, Rev 4.3 05/11/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 9 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Data Sheet VSC8061/VSC8062 Package Pin Descriptions Figure 9: VSC8061/8062 F (52-Pin LDCC) Pin Diagrams DCLK TEST TEST V CC VEE NC D2 D3 D4 VCC D5 D6 VTT D7 D8 VCC D9 D10 NC 39 38 37 36 35 34 33 32 31 3029 2827 26 40 25 41 24 42 23 43 22 44 VSC8061 21 45 20 46 Heat Sink Side 19 47 48 18 49 17 50 16 51 15 52 14 1 2 3 4 5 6 7 8 9 10 11 1213 D11 VT T D1 2 D1 3 D1 4 D1 5 CLK16N CLK16 V CC V CC NC CLKN CLK NC D1 D0 D U Heat Sink Up Top View V CC DCLKN NC NC NC VEE* NC NC NC DO VCC DON NC NC NC T EST T EST V CC D1 2 V CC VEE D1 1 D1 3 D1 4 D1 5 NC NC D10 D9 D8 VCC D7 D6 VTT D5 D4 VCC D3 D2 NC 39 38 37 36 35 343332 31 30 29 28 27 26 40 25 41 24 42 23 43 22 44 21 45 VSC8062 46 20 Heat Sink Side 47 19 48 18 49 17 50 16 51 15 52 14 1 2 3 4 5 6 7 8 9 1011 12 13 NC NC V CC CLK16N NC V CC NC NC VTT CLK16 NC D1 D0 NC NC NC NC VEE* NC CLK CLKN DIN VCC DI NC NC NC *Heat sink is electrically connected to pin 23 and should be biased to VEE. Page 10 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52069-0, Rev 4.3 05/11/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8061/VSC8062 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Figure 10: VSC8061/8062 QH (52-Pin PQFP) Pin Diagrams Heat Spreader Up Top View VEE* V CC NC VEE NC NC VEE DO DO N VEE VEE NC NC VCC VTT TEST TEST VTT NC U D DCLK DCLKN D0 VCC VTT 52 1 VITESSE VSC8061QH VCC CLK CLKN VEE VTT CLK16 CLK16N D15 D14 D13 D12 D11 VCC VCC VTT NC TEST VTT NC TEST D15 D14 D13 D12 VCC VTT 11 52 VEE* V CC NC VEE CL K CLKN VEE DIN DI VEE VEE NC NC VTT D1 D2 D3 D4 D5 D6 VTT D7 D8 D9 D1 0 VTT VITESSE VSC8062QH VCC NC NC VEE VTT NC NC NC CLK16 CLK16N D0 D1 VCC *Heat spreader is electrically connected to pin 52 and should be biased to VEE. VTT D11 D10 D9 D8 D7 D6 VTT D5 D4 D3 D2 VTT G52069-0, Rev 4.3 05/11/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 11 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Table 7: VSC8061 Pin Identifications Pin Number QH Package 38 37 9 10 34 33 11, 15-20, 2225, 28-32 45 44 7 8 1, 12, 27, 39, 51 2, 5, 13, 14, 21, 26, 35 36, 42, 43, 46, 49 6, 40, 41, 47, 48, 50 3, 4 52 Data Sheet VSC8061/VSC8062 Pin number F Package 13 12 34 35 9 8 1-3, 5, 6, 8-42, 44, 45, 47, 48, 50, 51 19 17 31 32 4, 10, 18, 30, 36, 43, 49 7,46 33 11, 14-16, 20-22, 24-26, 29, 37, 52 27, 28 23 Signal Name CLK CLKN DCLK DCLKN CLK16 CLK16N D[0:15] DO DON U D VCC VTT VEE NC Test VEE I/O I I I I O O I O O O O Pwr Pwr Pwr Level HS HS ECL ECL ECL ECL ECL HS HS ECL ECL Description High-speed clock true(1) High-speed clock, complement (1) Data clock true(1) Data Clock complement(1) Clock divide-by-16, true Clock divide-by-16, complement Parallel data inputs Serial data output, true Serial data output, complement Phase detector output - up frequency Phase detector output - down frequency Most positive power supply DCFL negative power supply SCFL negative power supply Do not connect, leave open Test inputs. Used in factory for testing, connect to VTT through a resistor Pwr Heat sink bias, connect to VEE NOTE: (1) Can be used single-ended. Page 12 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52069-0, Rev 4.3 05/11/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8061/VSC8062 Table 8: VSC8062 Pin Identifications Pin Number QH Package 48 47 44 45 31 30 8-11, 15-20, 22-25, 28, 29 1, 12, 27, 39, 51 2, 5, 13, 14, 21, 26, 35 36, 42, 43, 46, 49 3, 6, 32-34, 37, 38, 40, 41, 50 4, 7 52 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Pin Number F Package 21 20 17 19 8 6 3, 5, 31, 32, 34, 35, 39-42, 44, 45, 47, 48, 50, 51 4, 10, 18, 30, 36, 43, 49 7, 46 33 1, 2, 9, 11-16, 22, 24-27, 37, 38, 52 28, 29 23 Signal Name CLK CLKN DI DIN CLK16 CLK16N I/O I I I I O O Level HS HS HS HS ECL ECL Description High-speed clock, true(1) High-speed clock, complement(1) Serial data input, true(1) Serial data input, complement(1) Parallel data clock (high-speed clock divide-by16), true Parallel data clock (high-speed clock divide-by16), complement Parallel data outputs D[0:15] O ECL VCC VTT VEE NC Test VEE* Pwr Pwr Pwr Most positive power supply DCFL negative power supply SCFL negative power supply Do not connect, leave open Pwr Pwr Test inputs. Used in factory for testing, connect to VTT through a resistor Heat sink bias, connect to VEE NOTE: (1) Can be used single-ended. G52069-0, Rev 4.3 05/11/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 13 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Data Sheet VSC8061/VSC8062 Package Information 52-Pin Ceramic LDCC (F) Package B A HEAT SINK SIDE PACKAGE IS CAVITY DOWN 52 I J K L C M NOTES: Drawing not to scale. All units in mm unless otherwise noted. D E 45o 1 N O Packages: Ceramic (alumnia) Heat Sinks: Copper tungsten Leads: Alloy 42 with gold plating Item A B C(1) D(1) E mm (Min/Max) 18.54/19.56 1.02/1.52 15.49/16.51 15.24 TYP 1.27 TYP in (Min/Max) 0.730/0.770 0.040/0.060 0.610/0.650 0.600 TYP 0.050 TYP Item I J K(1) L M N O mm (Min/Max) 0.41/0.61 2.03/2.79 0.09/0.24 4.57/5.34 27.69/30.22 0.36/0.56 1.75/1.90 in (Min/Max) 0.016/0.024 0.080/0.110 0.003/0.009 0.180/0.210 1.090/1.190 0.014/0.022 0.069/0.075 NOTE: (1) At package body. Page 14 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52069-0, Rev 4.3 05/11/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8061/VSC8062 52 Pin PQFP (QH) Package 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset F G 52 40 Item A D 39 mm 2.35 2.00 0.35 17.20 14.00 17.20 14.00 0.88 0.80 1.00 5.84 Tol. MAX +.10 / -.05 ±.05 ±.25 ±.10 ±.25 ±.10 +.15 / -.10 +.15 / -.10 BASIC ±.50 DIA. 1 E F G L I H H I J J1 K L 13 27 14 10o TYP 26 A D 100 TYP 0.30 RAD. TYP. K A 0.20 RAD. TYP. STANDOFF 0.25 MAX. 0.17 MAX. 0.25 NOTES: Drawing not to scale. Heat spreader up. All units in mm unless otherwise noted. 0o- 8o J1 E J 0.102 MAX. LEAD COPLANARITY G52069-0, Rev 4.3 05/11/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 15 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Data Sheet VSC8061/VSC8062 Thermal Considerations The VSC8061 and VSC8062 are available in ceramic LDCC and thermally enhanced plastic quad flatpacks. These packages have been enhanced to improve thermal dissipation through low thermal resistance paths from the die to the exposed surface of the heat spreader. The thermal resistance of the two packages is shown in the following table Table 9: Thermal Resistance Symbol θJC θCA Description Thermal resistance from junction-to -case. Thermal resistance from case-to-ambient still air including conduction through the leads. F Pack 1.3 18.5 QH Pack 2.1 30.0 Units °C/W °C/W Thermal Resistance with Airflow Shown in Table 10 is the thermal resistance with airflow. This thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. The temperature difference between the ambient airflow temperature and the case temperature should be the worst case power of the device multiplied by the thermal resistance. Table 10: Thermal Resistance with Airflow Airflow 100 lfpm 200 lfpm 300 lfpm 500 lfpm θCA for F Package 15.9 14.9 14.2 13.3 θCA for QH Package 24 21 19 15 Units oC/W oC/W oC/W oC/W Thermal Resistance with Heat Sink The determination of appropriate heat sink to use is as shown below, using the VSC8061 in QH package as an example. Figure 11: VSC8061 in QH Package TA θSA θCS Page 16 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52069-0, Rev 4.3 05/11/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8061/VSC8062 ∆ T = P ( MAX ) ( θSA + θ CS ) where: θSA θCS ΤA(MAX) ΤC(MAX) ∆T P(MAX) = = = = = = Theta sink-to-ambient Theta case-to-sink Air temperature, user supplied (typically +55o C) Case temperature (+85oC for Industrial range) TC - TA Power (2.0 W for VSC8061) 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset The worst-case temperature rise from case to ambient is given by the equation: TC – TA ∆T ∴P = ------ = -------------------------Σθ θ SA + θ CS ∆T θ SA = ------ – θ CS P Ιf TA = 55o C and θCS (user supplied) is typically 0.6o C/W, ( 85 – 55 )° C θ SA = ----------------------------- – 0.6 ° C ⁄ W 2W θ SA = 14.4 ° C ⁄ W Therefore, to maintain the proper case and junction temperature, a heat sink with a θSA of 14.4oC/W or less must be selected at the appropriate air flow. NOTE: The heat spreader is tied to VEE in both the VSC8061 and VSC8062. G52069-0, Rev 4.3 05/11/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 17 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Data Sheet VSC8061/VSC8062 Figure 12: Data Eye From Serial Output of VSC8061 in QH Package (D0/D0N) Amplitude: 200 mV/div Time Scale: 50 ps/div Data Rate: 2.5 Gb/s Figure 13: Measurement Setup 16 Channels at 155Mb/s Bit Error Rate Tester D0 D1 VSC8061 D0N D15 D0 2.5Gb/s 231 - 1 PRB Data D0 D1 1:16 De-serializer D15 TEK CSA803 Signal Analyzer Page 18 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52069-0, Rev 4.3 05/11/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8061/VSC8062 Ordering Information 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset The order number for this product is formed by a combination of the device number, package type, and the operating temperature range. VSC80XX Device Type VSC8061: 2.5Gb/s 16-bit Multiplexer VSC8062: 2.5Gb/s 16-bit Demultiplexer FC Package and Temperature FC: 52 Pin Ceramic Leaded Chip Carrier (LDCC), 0°C ambient to +70°C case FI: 52 Pin Ceramic Leaded Chip Carrier (LDCC), -40°C ambient to +85°C case QH: 52-Pin Plastic Flat Quad Pack (PFQP), 0°C ambient to +85°C case Notice Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. G52069-0, Rev 4.3 05/11/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 19 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset Data Sheet VSC8061/VSC8062 Page 20 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52069-0, Rev 4.3 05/11/01