VSC8114QB2

VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8114 Features • Operates at STS-12/STM-4 (622.08Mb/s) Data Rate ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery • Loss of Signal (LOS) Input & LOS Detection • +3.3V/5V Programmable PECL Serial Interface • Provides Equipment, Facilities and Split Loopback Modes as well as Loop Timing Mode • Provide PECL Reference Clock Inputs • Meets Bellcore, ITU and ANSI Specifications for Jitter Performance • Low Power - 0.9Watts Typical • 100 PQFP Package • Compatible with Industry ATM UNI Devices • On Chip Clock Generation of the 622.08MHz High Speed Clock (Mux) • On Chip Clock Recovery of the 622.08MHz High Speed Clock (Demux) • 8-Bit Parallel TTL Interface with Parity Error Detection and Generation • SONET/SDH Frame Recovery General Description The VSC8114 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication Unit (PLL) for high speed clock generation as well as a Clock and data Recovery Unit (CRU) with 8-bit serialto-parallel and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direction (Mux). The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equipment loopback modes and a loop time mode. The part is packaged in a 100PQFP with an integrated heat spreader for optimum thermal performance and reduced cost. The VSC8114 provides an integrated solution for ATM physical layers and SONET/SDH systems applications. Functional Description The VSC8114 is designed to provide a SONET/SDH compliant interface between the high speed optical networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8114 converts 8 bit parallel data at 77.76Mb/s to a serial bit stream at 622.08Mb/s. The device also provides a Facility Loopback function which loops the received high speed data and clock (optionally recovered on-chip) directly to the high speed transmit outputs. A Clock Multiplier Unit (CMU) is integrated into the transmit circuit to generate the high speed clock for the serial output data stream from input reference frequencies of 19.44 or 77.76 MHz. The CMU can be bypassed with the received/recovered clock in loop timing mode, thus synchronizing the entire part to a single clock. The block diagram on page 2 shows the major functional blocks associated with the VSC8114. The receive section provides the serial-to-parallel conversion, converting 622Mb/s bit stream to an 8 bit parallel output at 77.76MHz. A Clock Recovery Unit (CRU) is integrated into the receive circuit to recover the high speed clock from the received serial data stream. The receive section provides an Equipment Loopback function which will loop the low speed transmit data and clock back through the receive section to the 8 bit parallel outputs. The VSC8114 also provides the option of selecting between either its internal CRU’s clock and data signals, or optics containing a CRU clock and data signals. The receive section also contains a SONET/SDH frame G52185-0, Rev 4.0 11/1/99 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Data Sheet VSC8114 detector circuit which is used to provide frame pluses during the A1, A2 boundary in the serial to parallel converter. This only occurs when OOF is high. Both internal and external LOS functions are supported. The VSC8114 provides the parity error detection and generation for the 8 bit data bus. On the receive side, the parity of the 8 bit data outputs is generated. On the transmit side, the parity of the 8 bit data input is calculated and compared with the received parity input. VSC8114 Block Diagram EQULOOP RESET DQ 0 1 0 1 Divide-by-8 Parity Chk TXDATAOUT+/QD 1 0 1 0 FACLOOP Divide-by-8 8:1 MUX REG 8 TXIN[7:0] TXLSCKIN TXLSCKOUT RXLSCKOUT TXPERR TXINP 1:8 DEMUX Parity/ REG 8 RXOUT[7:0] RXOUTP FRAMER OOF FP 1 0 LOOPTIM0 0 1 RXDATAIN+/CRUEQLP 0 CRU REC-CLK RXCLKIN+/DSBLCRU losdet 0 1 REC-DATA 1 0 1 CMU REFCLKP+/REFSEL LOSPECL LOSTTL LOSDETEN_ 0 1 CRUREFCLK CRUREFSEL Transmit Section Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKIN. See Figure 1. The data is then serialized (MSB leading) and presented to the TXDATAOUT+/- pins. The serial output stream is synchronized to the CMU generated clock which is a phase locked and frequency scaled ver- Page 2 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52185-0, Rev 4.0 11/1/99 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8114 ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery sion of the input reference clock. External control input REFSEL selects the multiply ratio of the CMU (see table 11). A divide-by-8 version of the CMU clock (TXLSCKOUT) should be used to synchronize the transmit interface of the UNI device to the transmit input registers on the VSC8114 (see Application Notes, p. 20). Figure 1: Data and Clock Transmit Block Diagram VSC8114 PM5355 TXDATAOUT+ TXDATAOUT- QD QD TXIN[7:0] QD TXLSCKIN REFCLK CMU Divide-by-8 TXLSCKOUT Receive Section High speed Non-Return to Zero (NRZ) serial data at 622Mb/s are received by the RXDATAIN inputs. The CRU recovers the high speed clock from the serial data input. The serial data is converted to byte-wide parallel data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock (RXLSCKOUT) should be used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the UNI device. The on-chip CRU is by-passed by setting the DSBLCRU input high. In this mode, the serial input data and corresponding clock are received by the RXDATAIN and RXCLKIN inputs respectively. RXDATAIN is clocked in on the rising edge of RXCLKIN+. See Figure 2. The receive section also includes frame detection and recovery circuitry which detects the SONET/SDH frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8114 will continually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been detected. Frame detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has been detected. The parallel output data on RXOUT[7:0] will be byte aligned starting on the third A2 byte. When a frame is detected, a single byte clock period long pulse is generated on FP which is synchronized with the byte-aligned third A2 byte on RXOUT[7:0]. The frame detector sends an FP pulse only if OOF is high. Loss of Signal The VSC8114 features Loss of Signal (LOS) detection. Loss of Signal is detected if the incoming serial data stream has no transition continuously for more than 128 bits. During an LOS condition, the VSC8114 forces the receive data low which is an indication for any downstream equipment that an optical interface failure has occurred. The receive section continues to be clocked by the CRU as it is now locked to the CRUREFCLK unless DSBLCRU is active, in which case it will be clocked by the CMU. This LOS condition will be removed when the part detects more than 16 transitions in a 128 bit time window. This LOS detection feature can be disabled by applying a high level to the LOSDETEN_ input. The VSC8114 also has a TTL input LOSTTL and a G52185-0, Rev 4.0 11/1/99 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Data Sheet VSC8114 PECL input LOSPECL to force the part into a Loss of Signal state. Most optics have a PECL output usually called “SD” or “FLAG” indicating the presence or lack of optical power. Depending on the optics manufacturer this signal is either active high or active low. The LOSTTL and LOSPECL inputs are XNOR’d to generate an internal LOS control signal. See Figure 2. The optics “SD” output should be connected to LOSPECL. The LOSTTL input should be tied to low if the optics “SD” is active high. If it’s active low tie LOSTTL to a high. The inverse is true if the optics use “FLAG” for loss of signal Figure 2: Data and Clock Receive Block Diagram VSC8114 LOSPECL LOSTTL LOSDETEN_ DSBLCRU RXDATAIN+/Losdet PM5355 DQ DQ RXOUT[7:0] DQ 1 0 CRU 0 Divide-by-8 0 1 CMU DQ FP DQ RXLSCKOUT RXCLKIN+/- 1 Facility Loopback The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set high, the Facility Loopback mode is activated and the high speed serial receive data (RXDATAIN) is presented to the high speed transmit output (TXDATAOUT). See Figure 3. In Facility Loopback mode the high speed receive data (RXDATAIN) is also converted to parallel data and presented to the low speed receive data output pins (RXOUT[7:0]). The receive clock (RXCLKIN) is also divided down and presented to the low speed clock output (RXLSCKOUT). Figure 3: Facility Loopback Data Path RXDATAIN CRU Recovered Clock D Q 1:8 Serial to Parallel D Q RXOUT[7:0] 0 1 Q D RXCLKIN TXDATAOUT 1 0 8:1 Parallel to Serial Q D TXIN[7:0] 1 0 PLL FACLOOP Page 4 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52185-0, Rev 4.0 11/1/99 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8114 ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Equipment Loopback The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the parallel to serial conversion of the low speed data (TXIN[7:0]) is selected and converted back to parallel data in the receiver section and presented to the low speed parallel outputs (RXOUT[7:0]). See Figure 4. The internally generated 622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In Equipment Loopback mode the transmit data (TXIN[7:0]) is serialized and presented to the high speed output (TXDATAOUT) using the clock generated by the on-chip clock multiplier unit. CRU Equipment Loopback Exactly the same as equipment loopback, the point where the transmit data is looped back is moved all the way back to the high speed I/O. When the CRUEQLP signal is set high, transmit data is looped back to the CRU, replacing RXDATAIN± Figure 4: Equipment Loopback Data Path DQ D Q RXDATAIN EQULOOP 0 1 1:8 Serial to Parallel RXOUT[7:0] ÷8 Q D 8:1 Parallel to Serial Q D RXLSCKOUT TXIN[7:0] TXLSCKIN ÷8 TXLSCKOUT TXDATAOUT PLL Split Loopback Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data received (RXDATAIN) is mux’d through to the high-speed serial outputs (TXDATAOUT). The low-speed transmit byte-wide bus (TXIN[7:0]) and (TXLSCKIN) is mux’d into the low-speed byte-wide receive output bus (RXOUT[7:0]) and (RXLSCKOUT). See Figure 5. Figure 5: Split Loopback Datapath RXDATAIN Recovered Clock CRU D Q 1:8 Serial to Parallel D Q RXOUT[7:0] 0 1 Q D 8:1 Parallel to Serial Q D RXLSCKOUT TXIN[[7:0] RXCLKIN DSBLCRU TXDATAOUT TXLSCKIN G52185-0, Rev 4.0 11/1/99 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Data Sheet VSC8114 Loop Timing LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single external source. Parity An even parity input (TXINP) is provided for the byte-wide transmit data. This input, along with byte-wide data, is clocked into the VSC8114 on the rising edge of TXLSCKIN. Parity is calculated on the clocked in bytewide data and compared to the clocked in parity input. A parity error is reported on the next TXLSCKIN rising edge on TXPERR. For no parity errors to result, TXINP must be logic 1 when on an odd number of bits in the TXIN[7:0] are logic 1; otherwise, it must be logic 0. Even parity is calculated and clocked out along with byte-wide receive data (RXOUT[7:0]) on RXOUTP. RXOUTP is a logic 1 when an odd number of bits on RXOUT[7:0] are logic 1; ohterwise, it is logic 0. Clock Synthesis The VSC8114 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector (PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feedback system. The PFD compares the selected divided down version of the 622MHz VCO (select pin REFSEL selects divide-by ratios of 8 and 32, see Table 11) and the reference clock. The integrator provides a transfer function between input phase error and output voltage control. The VCO portion of the PLL is a voltage controlled ring-oscillator with a center frequency of 622MHz. The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable reference frequencies. Good analog design practices should be applied to the board design for these external components. Tightly controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedicated PLL power (VDDANA) and ground (VSSANA) pins should have quiet supply planes to minimize jitter generation within the clock synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke (π filter) on the (VDDANA) power pins. Note: Vitesse recommends a (π filter) C-L-C choke over using a ferrite bead. All ground planes should be tied together using multiple vias. Reference Clocks Note that the CMU uses a differential PECL reference clock input to achieve optimum jitter performance. The CRU has the option of either using the CMU’s reference clock or its own independent reference clock CRUREFCLK. This is accomplished with the control signal CRUREFSEL. The CRUREFCLK should be used if the system is being operated in either a regeneration or loop timing mode. In either of these modes the quality of the CRUREFCLK is not a concern, thus it can be driven by a simple 77.76MHz crystal, the key is its independence from the CMU’s reference clock. Page 6 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52185-0, Rev 4.0 11/1/99 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8114 ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Figure 6: External Integrator Capacitor CP = 0.1 µF CP1 CP2 + - CN1 CN2 CN = 0.1 µF Table 1: Recommended External Capacitor Values Reference Frequency [MHz] 19.44 77.76 Divide Ratio 32 8 CP 0.1 0.1 CN 0.1 0.1 Type X7R X7R Size 0603/0803 0603/0803 Tol. +/-10% +/-10% Clock Recovery The fully monolithic Clock Recovery Unit (CRU) consists of a Phase Detector, a Frequency Detector, a Loop Filter and a Voltage Controlled Oscillator (VCO). The phase detector compares the phase information of the incoming data with the recovered clock. The frequency detector compares the frequency component of the data input with the recovered clock to provide the pull in energy during lock acquisition. The Loop Filter integrates the phase information from the phase and frequency detectors and provides the control voltage to the VCO. Jitter Tolerance Jitter Tolerance is the ability of the Clock Recovery Unit to track timing variations in the received data stream. The Bellcore and ITU specifications allow the received optical data to contain jitter. The amount that must be tolerated is a function of the frequency of the jitter. The CRU is designed to tolerate jitter with margin over the specification limits, see Figure 7. The CRU obtains and maintains lock based on the data transition information. When there is no transition on the data stream, the recovered clock frequency can drift. The VSC8114 can maintain lock over 100 bits of no switching on the data stream. G52185-0, Rev 4.0 11/1/99 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Figure 7: Jitter Tolerance Data Sheet VSC8114 JITTER(UI P-P) 150 Bellcore Requirement 60 VSC8114 Guaranteed Jitter Tolerance 15 6 1.5 0.6 0.15 10 30 300 25K 250K 2.5M JITTER FREQ(HZ) Data Latency The VSC8114 contains several operating modes, each of which exercise different logic paths through the part. Table 2 bounds the data latency through each path with an associated clock signal. Table 2: Data Latency Circuit Mode Receive Facilities Loopback Description MSB at RXDATAIN to data on RXOUT [7:0] MSB at RXDATAIN to MSB at TXDATAOUT Clock Reference RXCLKIN RXCLKIN Range of Clock cycles 25-35 2-4 Page 8 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52185-0, Rev 4.0 11/1/99 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8114 AC Timing Characteristics ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Figure 8: Receive High Speed Data Input Timing Diagram TRXCLK RXCLKIN+ RXCLKINTRXSU RXDATAIN+ RXDATAINTRXH Table 3: Receive High Speed Data Input Timing Table Parameter TRXCLK TRXSU TRXH Receive clock period Serial data setup time with respect to RXCLKIN Serial data hold time with respect to RXCLKIN Description Min 250 250 Typ 1.608 - Max - Units ns ps ps Figure 9: Receive Data Output Timing Diagram TRXCLKIN RXCLKIN+ RXCLKINTRXLSCK RXLSCKOUT RXOUT [7:0] RXOUTP A1 A2 A2 A2 A2 TRXVALID FP Table 4: Receive Data Output Timing Table Parameter TRXCLKIN TRXLSCK TRXVALID TPW Receive clock period Receive data output byte clock period Time data on RXOUT [7:0], FP, and RXOUTP is valid before and after the rising edge of RXLSCKOUT Pulse width of frame detection pulse FP Description Min 4.0 - Typ 1.608 12.86 12.86 Max - Units ns ns ns ns G52185-0, Rev 4.0 11/1/99 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Figure 10: Transmit High Speed Data Timing Diagram TTXDAT TXDATAOUT+ TXDATAOUT- Data Sheet VSC8114 Table 5: Transmit High Speed Data Timing Table Parameter TTXDAT Transmit data width Description Min - Typ 1.608 Max - Units ns Figure 11: Transmit Data Timing Diagram TPROP TXLSCKOUT TCLKIN TXLSCKIN TINSU TXIN [7:0] TXINP TERR TINH TXPERR Table 6: Transmit Data Input Timing Table Parameter TCLKIN TINSU TINH TPROP TERR Description Transmit data input byte clock period Transmit data and parity setup time with respect to TXLSCKIN Transmit data and parity hold time with respect to TXLSCKIN Maximum allowable propagation delay for connecting TXLSCKOUT to TXLSCKIN Propagation delay from TXLSCKIN to TXPERR Min 1.0 1.0 3.2 Typ 12.86 - Max 3.5 9.0 Units ns ns ns ns ns Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case Page 10 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52185-0, Rev 4.0 11/1/99 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8114 AC Characteristics Table 7: PECL and TTL Outputs Parameter TR,TTL TF,TTL TR,PECL TF,PECL Description TTL Output Rise Time TTL Output Fall Time PECL Output Rise Time PECL Output Fall Time ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Min — — — — Typ 2 1.5 350 350 Max — — — — Units ns ns ps ps Conditions 10-90% 10-90% 20-80% 20-80% DC Characteristics Table 8: PECL and TTL Inputs and Outputs Parameter VOH VOL VOCM ∆VOUT75 ∆VOUT50 Description Output HIGH voltage (PECL) Output LOW voltage (PECL) O/P Common Mode Range (PECL) Differential Output Voltage (PECL) Differential Output Voltage (PECL) Input HIGH voltage (PECL) Input LOW voltage (PECL) Differential Input Voltage (PECL) I/P Common Mode Range (PECL) Output HIGH voltage (TTL) Output LOW voltage (TTL) Input HIGH voltage (TTL) Min — 0.7 Typ — — Max VDDP – 0.9V — Units V V Conditions — — — 75Ω to VDDP – 2.0V 50Ω to VDDP – 2.0V For single ended For single ended — — IOH = -1.0 mA IOL = +1.0 mA — 1.1 — VDDP – 1.3V V 600 600 VDDP – 0.9V 0 400 1.5 – ∆VIN/2 2.4 — 2.0 — — — — — — — — — 1300 1300 VDDP – 0.3V VDDP – 1.72V 1600 mV mV V V mV V V V V VIH VIL ∆VIN VICM VOH VOL VIH VDDP – 1.0 – ∆VIN/2 — 0.5 5.5 G52185-0, Rev 4.0 11/1/99 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Parameter VIL IIH IIL Description Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Min 0 — — Data Sheet VSC8114 Max 0.8 500 -500 Typ — 50 — Units V µA µA Conditions — 2.0V< VIN < 5.5V, Typical@2.4V -0.5V< VIN