VSC8116QP2

VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8116 Features • Operates at Either STS-3/STM-1 (155.52 Mb/s) or STS-12/STM-4 (622.08 Mb/s) Data Rates • Compatible with Industry ATM UNI Devices • On Chip Clock Generation of the 155.52 Mhz or 622.08 Mhz High Speed Clock • Dual 8 Bit Parallel TTL Interface • SONET/SDH Frame Detection and Recovery ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation • Loss of Signal (LOS) Control • Provides Equipment, Facilities and Split Loopback Modes as well as Loop Timing Mode • Meets Bellcore, ITU and ANSI Specifications for Jitter Performance • Single 3.3V Supply Voltage • Low Power - 1.2 Watts Maximum • 64 PQFP Package General Description The VSC8116 is an ATM/SONET/SDH compatible transceiver integrating an on-chip clock multiplication unit (PLL) for the high speed clock and 8 bit serial-to-parallel and parallel-to-serial data conversion. The high speed clock generated by the on-chip PLL is selectable for 155.52 or 622.08 MHz operation. The demultiplexer contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equipment loopback modes and loop timing modes. The part is packaged in a 64 PQFP with an integrated heat spreader for optimum thermal performance and reduced cost. The VSC8116 provides an integrated solution for ATM physical layers and SONET/SDH systems applications. VSC8116 Block Diagram EQULOOP LOSTTL RXDATAIN+/LOS DQ 0 1 RXCLKIN+/0 1 0 1 Divide-by-8 RXLSCKOUT FRAMER OOF FP 8 1:8 DEMUX DQ RXOUT[7:0] 1 TXDATAOUT+/QD 0 1 0 FACLOOP Divide-by-8 TXLSCKOUT 8:1 MUX QD 8 TXIN[7:0] 1 0 LOOPTIM0 CMU REFCLK G52220-0, Rev 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Data Sheet VSC8116 Functional Description The VSC8116 is designed to provide a SONET/SDH compliant interface between the high speed optical networks and the lower speed User Network Interface (UNI) devices such as the PM5355 S/UNI-622 (or PM5312 STTX). The VSC8116 transmit section converts 8 bit parallel data at 77.76 Mb/s or 19.44 Mb/s to a serial bit stream at 622.08 Mb/s or 155.52 Mb/s, respectively. It also provides a Facility Loopback function which loops the received high speed data and clock directly to the transmit outputs. A Clock Multiplier Unit (CMU) is integrated into the transmit circuit to generate the high speed clock for the serial output data stream from input references frequency of 19.44 or 77.76 MHz. The CMU can be bypassed by using the receive clock in loop timing mode thus synchronizing the entire part to a single clock (RXCLKIN). The receive section provides the serial-to-parallel conversion, converting 155 Mb/s or 622 Mb/s to an 8 bit parallel output at 19.44 Mb/s or 77.76 Mb/s, respectively. The receive section provides an Equipment Loopback function which will loop the low speed transmit data and clock back through the receive section to the 8 bit parallel data bus and clock outputs. The receive section also contains a SONET/SDH frame detector circuit which is used to provide frame recovery in the serial to parallel converter. The block diagram on page 1 shows the major functional blocks associated with the VSC8116. Transmit Section Byte-wide data is presented to TXIN [7:0] and is clocked into the part on the rising edge of TXLSCKOUT (refer to Figure 1). The data is then serialized (MSB leading) and presented at the TXDATAOUT+/- pins. The serial output stream is synchronized to the CMU generated clock which is a phase locked and frequency scaled version of the input reference clock. External control inputs CMUFREQSEL and STS12 select the multiply ratio of the CMU and either STS-3 (155 Mb/s) or STS-12 (622 Mb/s) transmission (See Table 2). Figure 1: Data and Clock Transmit Block Diagram VSC8116 PM5355 TXDATAOUT+ TXDATAOUT- QD QD TXIN[7:0] QD REFCLK CMU Divide-by-8 TXLSCKOUT Page 2 © VITESSE SEMICONDUCTOR CORPORATION G52220-0, Rev 4.1 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8116 ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Receive Section High speed Non-Return to Zero (NRZ) serial data at 155Mb/s or 622Mb/s are received by the RXDATAIN inputs. The corresponding clock is received by the RXCLKIN inputs. RXDATAIN is clocked in on the rising edge of RXCLKIN+. See Figure 2. The serial data is converted to byte-wide parallel data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock (RXLSCKOUT) should be used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the UNI device. The receive section also includes frame detection and recovery circuitry which detects the SONET/SDH frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8116 will continually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been detected. Frame detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has been detected. The parallel output data on RXOUT[7:0] will be byte aligned starting on the third A2 byte. When a frame is detected, a single byte clock period long pulse is generated on FP which is synchronized with the byte-aligned third A2 byte on RXOUT[7:0]. The frame detector sends an FP pulse only if OOF is high or if a frame was detected while OOF was being pulled low. Figure 2: Data and Clock Receive Block Diagram VSC8116 DQ RXOUT[7:0] PM5355 DQ 1:8 Serial LOSTTL RXDATAIN+ RXDATAINRXCLKIN+ RXCLKIN0 1 CMU Divide-by-8 DQ to Parallel DQ FP DQ RXLSCKOUT Loss of Signal During a LOS condition, the VSC8116 forces the receive data low which is an indication for any downstream equipment that an optical interface failure has occurred. The receive section is clocked by the transmit section’s G52220-0, Rev 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Data Sheet VSC8116 PLL clock multiplier. Optics have either a PECL or TTL output, usually called “SD” (Signal Detect) or “FLAG” indicating either a lack of or presence of optical power. Depending on the optics manufacture this signal is either active high or active low polarity. If the optics Signal Detect or FLAG output is a “TTL” signal, it should be connected to LOSTTL. If it’s a “PECL” signal it should be connected through a “PECL” to “TTL” translator (such as the Motorola “MC100ELT21”) which then drives LOSTTL. The follow on part to VSC8116 is the VSC8117, in this device the signal LOSTTL has been changed to LOSPECL, a PECL input. Facility Loopback The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set high, the Facility Loopback mode is activated and the high speed serial receive data (RXDATAIN) is presented at the high speed transmit output (TXDATAOUT). See Figure 3. In Facility Loopback mode the high speed receive data (RXDATAIN) is also converted to parallel data and presented at the low speed receive data output pins (RXOUT [7:0]). The receive clock (RXCLKIN) is also divided down and presented at the low speed clock output (RXLSCKOUT). Figure 3: Facility Loopback Data Path RXDATAIN D Q 1:8 Serial to Parallel D Q RXOUT[7:0] RXCLKIN 1 ÷8 Q D Q D RXLSCKOUT TXIN[7:0] TXDATAOUT 0 8:1 Parallel to Serial 1 0 PLL FACLOOP Equipment Loopback The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the parallel to serial conversion of the low speed data (TXIN [7:0]) is selected and converted back to parallel data in the receiver section and presented at the low speed parallel outputs (RXOUT [7:0]). See Figure 4. The internally generated 155MHz/622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In Equipment Loopback mode the transmit data (TXIN [7:0]) is serialized and presented at the high speed output (TXDATAOUT). Page 4 © VITESSE SEMICONDUCTOR CORPORATION G52220-0, Rev 4.1 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8116 ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Figure 4: Equipment Loopback Data Path RXDATAIN DQ 0 1 1:8 Serial to Parallel D Q RXOUT[7:0] RXCLKIN TXDATAOUT Q D 0 1 ÷8 8:1 Parallel to Serial Q D RXLSCKOUT TXIN[7:0] EQULOOP PLL ÷8 TXLSCKOUT Split Loopback Equipment and facility loopback modes can be enabled simultaneously. See descriptions for equipment and facility loop modes above. The only change is, since they are both active, RXDATAIN will not be deserialized and presented to RXOUT[0:7], and TXIN[0:7] will not be serialized and present to TXDATAOUT. Figure 5: Split Loopback Datapath 1:8 Serial to Parallel D Q RXDATAIN D Q 0 1 RXOUT[7:0] RXCLKIN 1 0 1 Q D ÷8 8:1 Parallel to Serial Q D RXLSCKOUT TXIN[7:0] TXDATAOUT 0 1 0 PLL EQULOOP FACLOOP Loop Timing LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single external source. G52220-0, Rev 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Data Sheet VSC8116 Clock Multiplier Unit The VSC8116 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector (PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feedback system. The PFD compares the selected divided down version of the 622MHz VCO (CMUFREQSEL selects divide-by ratios of 8 or 32, see Table 2) and the reference clock. The integrator provides a transfer function between input phase error and output voltage control. The VCO portion of the PLL is a voltage controlled ring-oscillator with a center frequency of 622MHz. The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable reference frequencies. Good analog design practices should be applied to the board design for these external components. Tightly controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedicated PLL power (VDDA) and ground (VSSA) pins should have quiet supply planes to minimize jitter generation within the clock synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke (π filter) on the (VDDA) power pins. Note: Vitesse recommends a (π filter) C-L-C choke over using a ferrite bead. All ground planes should be tied together using multiple vias. Table 1: Recommended External Capacitor Values Reference Frequency [MHz] 19.44 77.76 Divide Ratio 32 8 CP 0.1 0.1 CN 0.1 0.1 Type X7R X7R Size 0603/0805 0603/0805 Tol. +/-10% +/-10% Page 6 © VITESSE SEMICONDUCTOR CORPORATION G52220-0, Rev 4.1 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8116 ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Figure 6: External Integrator Capacitor CP = 0.1µF CP1 CP2 + - CN1 CN2 CN = 0.1µF Clock Multiplier Unit Table 2: Reference Frequency Selection and Output Frequency Control Reference Frequency [MHz] 19.44 77.76 19.44 77.76 STS12 1 1 0 0 CMUFREQSEL 1 0 1 0 Output Frequency [MHz] 622.08 622.08 155.52 155.52 G52220-0, Rev 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Table 3: Clock Multiplier Unit Performance Name RCd RCj RCj RCf OCj OCj OCfrange OCd (1) (2) (3) Data Sheet VSC8116 Min 40 Description Reference clock duty cycle Reference clock jitter (RMS) @ 77.76 MHz ref (1) Reference clock jitter (RMS) @ 19.44 MHz ref (1) Reference clock frequency tolerance (2) Output clock jitter (RMS) @ 77.76 MHz ref (3) Output clock jitter (RMS) @ 19.44 MHz ref Output frequency Output clock duty cycle (3) Typ Max 60 13 5 Units % ps ps ppm ps ps MHz % -20 +20 8 15 620 40 624 60 These Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirements (< 10 mUIrms) Needed to meet SONET output frequency stability requirements Measured Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter. AC Timing Characteristics Figure 7: Receive High Speed Data Input Timing Diagram TRXCLK RXCLKIN+ RXCLKINTRXSU RXDATAIN+ RXDATAINTRXH Table 4: Receive High Speed Data Input Timing Table (STS-12 Operation) Parameter TRXCLK TRXSU TRXH Receive clock period Serial data setup time with respect to RXCLKIN Serial data hold time with respect to RXCLKIN Description Min 250 250 Typ 1.608 - Max - Units ns ps ps Page 8 © VITESSE SEMICONDUCTOR CORPORATION G52220-0, Rev 4.1 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8116 Parameter TRXCLK TRXSU TRXH Receive clock period ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Table 5: Receive High Speed Data Input Timing Table (STS-3 Operation) Description Serial data setup time with respect to RXCLKIN Serial data hold time with respect to RXCLKIN Min 1.5 1.5 Typ 6.43 - Max - Units ns ns ns Figure 8: Transmit Data Input Timing Diagram TCLKOUT TXLSCKOUT TINSU TINH TXIN [7:0] Table 6: Transmit Data Input Timing Table (STS-12 Operation) Parameter TINSU TINH Description Transmit data setup time with respect to TXLSCKOUT Transmit data hold time with respect to TXLSCKOUT Min 1.0 1.0 Typ - Max - Units ns ns Table 7: Transmit Data Input Timing Table (STS-3 Operation) Parameter TINSU TINH Description Transmit data setup time with respect to TXLSCKOUT Transmit data hold time with respect to TXLSCKOUT Min 1.0 1.0 Typ - Max - Units ns ns Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case G52220-0, Rev 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Figure 9: Receive Data Output Timing Diagram Data Sheet VSC8116 TRXCLKIN RXCLKIN+ RXCLKINTRXLSCK RXLSCKOUT RXOUT [7:0] A1 A2 A2 A2 A2 TRXVALID FP Table 8: Receive Data Output Timing Table (STS-12 Operation) Parameter TRXCLKIN TRXLSCK TRXVALID TPW Receive clock period Receive data output byte clock period Time data on RXOUT [7:0] and FP is valid before and after the rising edge of RXLSCKOUT Pulse width of frame detection pulse FP Description Min 4.0 - Typ 1.608 12.86 12.86 Max - Units ns ns ns ns Table 9: Receive Data Output Timing Table (STS-3 Operation) Parameter TRXCLKIN TRXLSCKT TRXVALID TPW Receive clock period Receive data output byte clock period Time data on RXOUT [7:0] and FP is valid before and after the rising edge of RXLSCKOUT Pulse width of frame detection pulse FP Description Min 22 - Typ 6.43 51.44 51.44 Max - Units ns ns ns ns Page 10 © VITESSE SEMICONDUCTOR CORPORATION G52220-0, Rev 4.1 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8116 AC Characteristics Table 10: PECL and TTL Outputs Parameters TR,TTL TF,TTL TR,PECL TF,PECL Description TTL Output Rise Time TTL Output Fall Time PECL Output Rise Time PECL Output Fall Time ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Min — — — — Typ 2 1.5 350 350 Max — — — — Units ns ns ps ps Conditions 10-90% 10-90% 20-80% 20-80% DC Characteristics Table 11: PECL and TTL Inputs and Outputs Parameters VOH VOL VOCM Description Output HIGH voltage (PECL) Output LOW voltage (PECL) O/P Common Mode Range (PECL) Differential Output Voltage (PECL) Differential Output Voltage (PECL) Input HIGH voltage (PECL) Input LOW voltage (PECL) Differential Input Voltage (PECL) I/P Common Mode Range (PECL) Output HIGH voltage (TTL) Output LOW voltage (TTL) Min — 0.7 Typ — — Max VDDP – 0.9V — Units V V Conditions — — — 1.1 — VDDP – 1.3V V ∆VOUT75 600 — 1300 mV 75Ω to VDDP – 2.0 V ∆VOUT50 600 — 1300 mV 50Ω to VDDP – 2.0 V For single ended For single ended — — IOH = -1.0 mA IOL = +1.0 mA VIH VIL ∆VIN VDDP – 0.9V 0 400 1.5 – ∆VIN/2 — — — VDDP – 0.3V VDDP – 1.72V 1600 V V mV VICM VOH VOL — VDDP – 1.0 – ∆VIN/2 — 0.5 V 2.4 — — — V V G52220-0, Rev 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Table 11: PECL and TTL Inputs and Outputs Parameters VIH VIL IIH IIL Description Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Min 2.0 0 — — Data Sheet VSC8116 Max 5.5 0.8 500 -500 Typ — — 50 — Units V V µA µA Conditions — — 2.0V< VIN < 5.5V, Typical@2.4V -0.5V < VIN < 0.8V Power Dissipation Table 12: Power Supply Currents (Outputs Open) Parameter IDD PD Power dissipation Description Power supply current from VDD Typ 231 0.8 (Max) 346 1.2 Units mA W Absolute Maximum Ratings(1) Power Supply Voltage (VDD) Potential to GND .................................................................................-0.5V to +4V DC Input Voltage (PECL inputs)............................................................................................ -0.5V to VDD +0.5V DC Input Voltage (TTL inputs) ......................................................................................................... -0.5V to 5.5V DC Output Voltage (TTL Outputs)........................................................................................ -0.5V to VDD + 0.5V Output Current (TTL Outputs) ................................................................................................................. +/-50mA Output Current (PECL Outputs)................................................................................................................+/-50mA Case Temperature Under Bias .........................................................................................................-55o to +125oC Storage Temperature..................................................................................................................... -65oC to +150oC Maximum Input ESD (Human Body Model).............................................................................................. 1500 V Note: Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Power Supply Voltage (VDD) ................................................................................................................. +3.3V ± 5 % Commercial Operating Temperature Range* (T).................................................................................. 0o to 70oC Extended Operating Temperature Range* (T) .................................................................................... 0o to 115oC Industrial Operating Temperature Range* (T) ................................................................................... -40o to 85oC * Lower limit of specification is ambient temperature and upper limit is case temperature. Page 12 © VITESSE SEMICONDUCTOR CORPORATION G52220-0, Rev 4.1 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8116 Package Pin Description Signal RESET LOOPTIM0 CMUFREQSEL VDD TXDATAOUT+ TXDATAOUTN/C RXCLKIN+ RXCLKINVDD OOF N/C RXDATAIN+ RXDATAINVDD N/C N/C VDD RXOUT0 RXOUT1 VSS RXOUT2 RXOUT3 RXOUT4 RXOUT5 RXOUT6 RXOUT7 VSS RXLSCKOUT FP VDD N/C LOSTTL VDD VSS REFCLK VSSA ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 I/O I I I P O O I I P I I I P P O O P O O O O O O P O O P I P P I P Level TTL TTL TTL +3.3V PECL PECL PECL PECL +3.3V TTL PECL PECL +3.3V +3.3V TTL TTL GND TTL TTL TTL TTL TTL TTL GND TTL TTL +3.3V TTL +3.3V GND TTL GND Pin Description Resets frame detection, dividers, controls; active high Enable loop timing operation; active HIGH Reference clock frequency select, refer to table 2 +3.3V Power Supply Transmit output, high speed differential data + Transmit output, high speed differential data No connection Receive high speed differential clock input+ Receive high speed differential clock input+3.3V Power Supply Out Of Frame; Frame detection initiated with high level No connection Receive high speed differential data input+ Receive high speed differential data input+3.3V Power Supply No connection No connection +3.3V Power Supply Receive output data bit0 Receive output data bit1 Ground Receive output data bit2 Receive output data bit3 Receive output data bit4 Receive output data bit5 Receive output data bit6 Receive output data bit7 Ground Receive byte clock output Frame detection pulse +3.3V Power Supply No connection Loss of Signal Control - TTL input; active low +3.3V Power Supply Ground Reference clock input, refer to table 2 Analog Ground (CMU) G52220-0, Rev 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Signal N/C C1P C1N C2N C2P VDDA VSSA VSS VSS VDD VDD TXLSCKOUT TXIN7 TXIN6 VSS TXIN5 TXIN4 TXIN3 TXIN2 TXIN1 TXIN0 STS12 N/C VDD EQULOOP FACLOOP N/C Data Sheet VSC8116 Pin Description No connection CMU external capacitor (see Figure 6, and Table 1) CMU external capacitor (see Figure 6, and Table 1) CMU external capacitor (see Figure 6, and Table 1) CMU external capacitor (see Figure 6, and Table 1) Analog Power Supply (CRU) Analog Ground (CRU) Ground Ground +3.3V Power Supply +3.3V Power Supply Transmit byte clock out Transmit input data bit7 Transmit input data bit6 Ground Transmit input data bit5 Transmit input data bit4 Transmit input data bit3 Transmit input data bit2 Transmit input data bit1 Transmit input data bit0 155Mb/s or 622Mb/s mode select, refer to table 2 No connection +3.3V Power Supply Equipment loopback, loops low speed byte wide transmit input data to receive output bus Facility loopback, loops high speed receive data and clock directly to transmit outputs. No connection Pin 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I/O O I I O P P P P P P O I I P I I I I I I I P I I - Level ANALOG ANALOG ANALOG ANALOG +3.3V GND GND GND +3.3V +3.3V TTL TTL TTL GND TTL TTL TTL TTL TTL TTL TTL +3.3V TTL TTL - Page 14 © VITESSE SEMICONDUCTOR CORPORATION G52220-0, Rev 4.1 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8116 Package Information 64 Pin PQFP Package Drawings D ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Item D1 mm 2.45 2.00 13.20 10.00 13.20 10.00 0.88 0.50 0.22 0° - 7° .30 .20 Tol. MAX +.10/-.05 ±.25 ±.10 ±.25 ±.10 ±.15/-.10 BASIC ±.05 A 64 49 48 1 A2 D D1 E E1 E1 E L e b 16 33 θ R TYP TYP 17 10o TYP 32 R1 A A2 100 TYP e R A R1 STANDOFF 0.25 MAX. 0.17 MAX. 0.25 L θ b 0.102 MAX. LEAD COPLANARITY NOTES: All drawings not to scale All units in mm unless otherwise noted. 10 x 10 mm Package # 101-266-1 14 x 14 mm Package # 101-262-1 G52220-0, Rev 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Data Sheet VSC8116 Package Thermal Characteristics The VSC8116 is packaged into a thermally-enhanced plastic quad flatpack (PQFP). This package adheres to the industry-standard EIAJ footprint for a 10x10mm body but has been enhanced to improve thermal dissipation with the inclusion of an exposed Copper Heat Spreader. The package construction is as shown in Figure 10. Figure 10: Package Cross Section Copper Heat Spreader Insulator Lead Wire Bond Die Plastic Molding Compound The thermal resistance for the VSC8116 package is improved through low thermal resistance paths from the die to the exposed surface of the heat spreader and from the die to the lead frame through the heat spreader overlap of the lead frame. Table 13: 64-Pin PQFP Thermal Resistance Symbol θjc θca θca-100 θca-200 θca-400 θca-600 Description Thermal resistance from junction to case Thermal resistance from case to ambient in still air including conduction through the leads for a non-thermally saturated board. Thermal resistance from case to ambient in 100 LPFM air Thermal resistance from case to ambient in 200 LPFM air Thermal resistance from case to ambient in 400 LPFM air Thermal resistance from case to ambient in 600 LPFM air Value 2.5 37 31 28 24 22 Units oC/W oC/W oC/W oC/W oC/W oC/W The VSC8116QB1 is designed to operate at a maximum case temperature of up to 115 oC. The user must guarantee that the maximum case temperature specification is not violated. Given the thermal resistance of the package in still air, the user can operate the VSC8116 in still air if the ambient temperature does not exceed 71oC (71oC = 115oC - 1.2W * 37oC/W). If operation above this ambient temperature is required, then an appropriate heatsink must be used with the part or adequate airflow must be provided. Page 16 © VITESSE SEMICONDUCTOR CORPORATION G52220-0, Rev 4.1 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8116 Ordering Information The order number for this product are: Part Number VSC8116QP: ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Device Type 155Mb/s-622Mb/s Mux/Dmux with CMU in 64 Pin PQFP Commercial Temperature, 0°C ambient to 70°C case 155Mb/s-622Mb/s Mux/Dmux with CMU in 64 Pin PQFP Extended Temperature, 0°C ambient to 115°C case 155Mb/s-622Mb/s Mux/Dmux with CMU in 64 Pin PQFP Industrial Temperature, -40°C ambient to 85°C case VSC8116QP1 VSC8116QP2 Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time without prior notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to placing orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. G52220-0, Rev 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 17 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Data Sheet VSC8116 Application Notes AC Coupling and Terminating High-speed PECL I/Os The high speed signals on the VSC8116 (RXDATAIN, RXCLKIN, TXDATAOUT, TXCLKOUT) use 3.3V PECL levels which are essentially ECL levels shifted positive by 3.3 volts. The PECL I/Os are referenced to the VDD supply (VDD) and are terminated to ground. Since most optics modules use either ECL or 5.0V PECL levels, the high speed ports need to be either AC-coupled to overcome the difference in dc levels, or DC translated (DC level shift). The PECL receiver inputs of the VSC8116 are internally biased at VDD/2. Therefore, AC-coupling to the VSC8116 inputs is accomplished by providing the pull-down resistor for the open-source PECL output and an AC-coupling capacitor used to eliminate the DC component of the output signal. This capacitor allows the PECL receivers of the VSC8116 to self-bias via its internal resistor divider network (see Figure 12). The PECL output drivers are capable of sourcing current but not sinking it. To establish a LOW output level, a pull-down resistor, traditionally connected to VDD-2.0V, is needed when the output FET is turned off. Since VDD-2.0V is usually not present in the system, the resistor should be terminated to ground for convenience. The VSC8116 output drivers should be either AC-coupled to the 5.0V PECL inputs of the optics module, or translated (DC level shift). Appropriate biasing techniques for setting the DC-level of these inputs should be employed. The DC biasing and 50 ohm termination requirements can easily be integrated together using a thevenin equivalent circuit as shown in Figure 11. The figure shows the appropriate termination values when interfacing 3.3V PECL to 5.0V PECL. This network provides the equivalent 50 ohm termination for the high speed I/Os and also provides the required dc biasing for the receivers of the optics module. Table 15 contains recommended values for each of the components. Figure 11: AC Coupled High Speed I/O +3.3V DRIVER (Optics Module) PC Board Trace R1 GND GND Note: Only one side of a differential signal is shown. C1 PC Board Trace R2 GND C2 VSC8111 PECL I/O +5.0V R3 RECEIVER (Optics Module) R4 GND Page 18 © VITESSE SEMICONDUCTOR CORPORATION G52220-0, Rev 4.1 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8116 Table 14: AC Coupling Component Values Component R1 R2 R3 R4 C1, C2, C3, C4 ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Value 270 ohms 75 ohms 68 ohms 190 ohms .01uf High Frequency Tolerance 5% 5% 1% 1% 10% TTL Input Structure The TTL inputs of the VSC8116 are 3.3V TTL which can accept 5.0V TTL levels within a given set of tolerances (see Table 11). The input structure, shown in Figure 12, uses a current limiter to avoid overdriving the input FETs. Layout of the High Speed Signals The routing of the High Speed signals should be done using good high speed design practices. This would include using controlled impedance lines (50 ohms) and keeping the distance between components to an absolute minimum. In addition, stubs should be kept at a minimum as well as any routing discontinuities. This will help minimize reflections and ringing on the high speed lines and insure the maximum eye opening. In addition the output pull down resistor R2 should be placed as close to the VSC8116 pin as possible while the AC-coupling capacitor C2 and the biasing resistors R3, R4 should be placed as close as possible to the optics input pin. The same is true on the receive circuit side. Using small outline components and minimum pad sizes also helps in reducing discontinuities. Ground Planes The ground plane for the components used in the High Speed interface should be continuous and not sectioned in an attempt to provide isolation to various components. Sectioning of the ground planes tends to interfere with the ground return currents on the signal lines. In addition, the smaller the ground planes the less effective they are in reducing ground bounce noise and the more difficult to decouple. Sectioning of the positive supplies can provide some isolation benefits. Analog Power Supplies Good analog design practices should be applied to the board design for the analog ground and power planes. The dedicated PLL power (VDDA) and ground (VSSA) pins need to have quiet supply planes to minimize jitter generation within the clock synthesis unit. This is accomplished by either using a ferrit bead or a CL-C choke (π filter). G52220-0, Rev 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 19 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation Figure 12: Input Structures VDD +3.3 V VDD +3.3 V Data Sheet VSC8116 INPUT INPUT Current Limit R INPUT R GND GND All Resistors 3.3K REFCLK and TTL Inputs High Speed Differential Input (RXDATAIN+/RXDATAIN-) (RXCLKIN+/RXCLKIN-) Page 20 © VITESSE SEMICONDUCTOR CORPORATION G52220-0, Rev 4.1 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 1/8/00