VSC8117QP1

VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 Features ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery • Operates at Either STS-3/STM-1 (155.52Mb/s) or STS-12/STM-4 (622.08Mb/s) Data Rates • Compatible with Industry ATM UNI Devices • On Chip Clock Generation of the 155.52MHz or 622.08MHz High Speed Clock (Mux) • On Chip Clock Recovery of the 155.52MHz or 622.08MHz High Speed Clock (Demux) • 8 Bit Parallel TTL Interface • SONET/SDH Frame Recovery • Loss of Signal (LOS) Input & LOS Detection • +3.3V/5V programmable PECL Serial Interface • Provides Equipment, Facilities and Split Loopback Modes as well as Loop Timing Mode • Provides TTL and PECL reference clock inputs • Meets Bellcore, ITU and ANSI Specifications for Jitter Performance • Low Power - 1.0 Watts Typical • 64 PQFP Package General Description The VSC8117 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication Unit (PLL) for the high speed clock as well as a clock and data recovery unit (CRU) with 8 bit serial-to-parallel and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direction (Mux). The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer contains SONET/SDH frame detection and recovery. The device provides facility loopback, equipment loopback, and loop timing modes. The part is packaged in a 64-pin PQFP with integrated heat spreader for optimum thermal performance and reduced cost. The VSC8117 provides an integrated solution for ATM physical layers and SONET/SDH systems applications. Functional Description The VSC8117 is designed to provide a SONET/SDH compliant interface between the high speed optical networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8117 converts 8 bit parallel data at 77.76Mb/s or 19.44Mb/s to a serial bit stream at 622.08Mb/s or 155.52Mb/s respectively. The device also provides a Facility Loopback function which loops the received high speed data and clock (optionally recovered on-chip) directly to the high speed transmit outputs. A Clock Multiplier Unit (CMU) is integrated into the transmit circuit to generate the high speed clock for the serial output data stream from input reference frequencies of 19.44 or 77.76 MHz. The CMU can be bypassed with the recovered clock in loop timing mode thus synchronizing the entire part to a single clock. The block diagram on page 2 shows the major functional blocks associated with the VSC8117. The receive section provides the serial-to-parallel conversion, converting the 155.52Mb/s or 622.08Mb/s bit stream to an 8 bit parallel output at 19.44Mb/s or 77.76Mb/s respectively. A Clock Recovery Unit (CRU) is integrated into the receive circuit to recover the high speed clock from the received serial data stream. The receive section provides an Equipment Loopback function which will loop the low speed transmit data and clock back through the receive section to the 8 bit parallel data bus and clock outputs. The VSC8117 also provides the option of selecting between either its internal CRU’s recovered clock and data signals or optics containing a G52221-0, Rev. 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Data Sheet VSC8117 CRU clock and data signals. (In this mode the VSC8117 operates just like the VSC8111 and VSC8116). The receive section also contains a SONET/SDH frame detector circuit which is used to provide frame pluses during the A1, A2 boundary in the serial to parallel converter. This only occurs when OOF is high. Both internal and external LOS functions are supported. The high speed serial signals can be made PECL compatible or LVPECL compatible by setting the proper voltage on the VDDP supply pins VSC8117 Block Diagram EQULOOP DSBLCRU DQ 1 RXDATAIN+/CRUEQLP RXCLKIN+/0 CRU REC-CLK REC-DATA FRAMER OOF FP 8 0 1 0 1 0 0 1 0 1 1:8 DEMUX DQ RXOUT[7:0] 1 Divide-by-8 RXLSCKOUT LOSPECL LOSDETEN_ losdet 0 CRUREFCLK 1 1 CRUREFSEL 0 CMU STS12 REFCLKP+/REFCLK CMUFREQSEL LOOPTIM0 TXDATAOUT+/- QD 1 0 1 0 Divide-by-8 TXLSCKOUT 8:1 MUX QD 8 TXIN[7:0] FACLOOP Page 2 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52221-0, Rev 4.1 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Transmit Section Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKOUT. TXLSCKOUT also latches TXIN[7:0] into the part as shown in Figure 1. The data is then serialized (MSB leading) and presented at the TXDATAOUT+/- pins. The serial output stream is synchronized to the CMU generated clock which is a phase locked and frequency scaled version of the input reference clock. External control inputs CMUFREQSEL and STS-12 select the multiply ratio of the CMU for either STS-3 (155MbS) or STS-12 (622Mb/s) transmission (see Table 10). A divide-by-8 version of the CMU clock (TXLSCKOUT) should be used to synchronize the transmit interface of the UNI device to the transmit input registers on the VSC8117. Figure 1: Data and Clock Transmit Block Diagram VSC8117 PM5355 TXDATAOUT+ TXDATAOUT- QD QD TXIN[7:0] QD TXLSCKIN REFCLK CMU Divide-by-8 TXLSCKOUT Receive Section High speed Non-Return to Zero (NRZ) serial data at 155Mb/s or 622Mb/s are received by the RXDATAIN inputs. The CRU recovers the high speed clock from the serial data input. The serial data is converted to bytewide parallel data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock (RXLSCKOUT) should be used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the UNI device. The on-chip CRU is by-passed by setting the DSBLCRU input high. In this mode, the serial input data and corresponding clock are received by the RXDATAIN and RXCLKIN inputs respectively. RXDATAIN is clocked in on the rising edge of RXCLKIN+. See Figure 2. The receive section also includes frame detection and recovery circuitry which detects the SONET/SDH frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8117 will continually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been detected. Frame detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has been detected. The parallel output data on RXOUT[7:0] will be byte aligned starting on the third A2 byte. When a frame is detected, a single byte clock period long pulse is generated on FP which is synchronized with the byte-aligned third A2 byte on RXOUT[7:0]. The frame detector sends a FP pulse only if OOF is high. G52221-0, Rev. 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Data Sheet VSC8117 Loss of Signal The VSC8117 features Loss of Signal (LOS) detection. Loss of Signal is declared if the incoming serial data stream has no transition continuously for more than 128 bits. During an LOS condition, the VSC8117 forces the receive data low which is an indication for any downstream equipment that an optical interface failure has occurred. The receive section continues to be clocked by the CRU as it is now locked to the CRUREFCLK unless DSBLCRU is active or CRUREFSEL is inactive in which case it will be clocked by the CMU. This LOS condition will be removed when the part detects more than 16 transitions in a 128 bit time window. This LOS detection feature can be disabled by applying a high level to the LOSDETEN_ input. The VSC8117 also has a PECL input LOSPECL to force the part into a Loss of Signal state. Most optics have a PECL output usually called “SD” or “FLAG” indicating a lack of or presence of optical power. Depending on the optics manufacturer this signal is either active high or active low. The LOSPECL input on the VSC8117 is active low. Figure 2: Data and Clock Receive Block Diagram VSC8117 LOSPECL LOSDETEN_ DSBLCRU RXDATAIN+/1 0 CRU 0 RXCLKIN+/1 0 1 CMU Divide-by-8 RXLSCKOUT DQ FP DQ DQ DQ RXOUT[7:0] PM5355 DQ Facility Loopback The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set high, the Facility Loopback mode is activated and the high speed serial receive data (RXDATAIN) is presented to the high speed transmit output (TXDATAOUT). See Figure 3. In Facility Loopback mode the high speed receive data (RXDATAIN) is also converted to parallel data and presented to the low speed receive data output pins (RXOUT[7:0]). The receive clock (RXCLKIN) or the recovered clock is also divided down and presented to the low speed clock output (RXLSCKOUT). Page 4 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52221-0, Rev 4.1 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Figure 3: Facility Loopback Data Path RXDATAIN CRU D Q 1:8 Serial to Parallel D Q RXOUT[7:0] Recovered Clock 0 1 Q D Divide-by-8 1 0 8:1 Parallel to Serial Q D RXLSCKOUT TXIN[7:0] RXCLKIN TXDATAOUT 1 0 PLL FACLOOP Equipment Loopback The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the parallel to serial conversion of the low speed data (TXIN[7:0]) is selected and converted back to parallel data in the receiver section and presented to the low speed parallel outputs (RXOUT[7:0]). See Figure 4. The internally generated 155/622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In Equipment Loopback mode the transmit data (TXIN[7:0]) is serialized by the on-chip CMU and presented at the high speed output (TXDATAOUT). CRU Equipment Loopback Exactly the same as equipment loopback, the point where the transmit data is looped back is moved all the way back to the high speed I/O. When the CRUEQLP signal is set high, transmit data is looped back to the CRU, replacing RXDATAIN± Figure 4: Equipment Loopback Data Path RXDATAIN EQULOOP DQ 0 1 1:8 Serial to Parallel D Q RXOUT[7:0] ÷8 Q D 8:1 Parallel to Serial Q D RXLSCKOUT TXIN[7:0] TXDATAOUT PLL ÷8 TXLSCKOUT G52221-0, Rev. 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Data Sheet VSC8117 Split Loopback Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data received (RXDATAIN) is mux’d through to the high-speed serial output (TXDATAOUT). The low-speed transmit byte wide bus(TXIN[7:0]) and (TXLSCKIN) are mux’d into the low-speed byte wide receive output bus (RXOUT[7:0]) and (RXLSCKOUT). See Figure 5. Figure 5: Split Loopback Datapath RXDATAIN Recovered Clock CRU D Q 1:8 Serial to Parallel D Q RXOUT[7:0] 0 1 Q D 8:1 Parallel to Serial ÷8 Q D RXCLKIN DSBLCRU TXDATAOUT RXLSCKOUT TXIN[7:0] TXLSCKIN PLL Loop Timing LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single external source. Clock Synthesis The VSC8117 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector (PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feedback system. The PFD compares the selected divided down version of the 622MHz VCO (pin CMUFREQSEL selects the divide-by ratios of 8 or 32, see Table 10) and the reference clock. The integrator provides a transfer function between input phase error and output voltage control. The VCO portion of the PLL is a voltage controlled ring-oscillator with a center frequency of 622MHz. The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable reference frequencies. Page 6 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52221-0, Rev 4.1 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Good analog design practices should be applied to the board design for these external components. Tightly controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedicated PLL power (VDDA) and ground (VSSA) pins should have quiet supply planes to minimize jitter generation within the clock synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke (π filter) on the (VDDA) power pins. Note: Vitesse recommends a (π filter) C-L-C choke over using a ferrite bead. All ground planes should be tied together using multiple vias. Reference Clocks To improve jitter performance and to provide flexibility, an additional differential PECL reference clock input is provided. This reference clock is internally XNOR’d with a TTL reference clock input to generate the reference for the CMU. Vitesse recommends using the differential PECL input and tieing the unused TTL reference clock low. If the TTL reference clock is used the positive side of the differential PECL reference clock “REFCLKP+” should be tied to ground. “REFCLKP+/-” are internally biased with on-chip resistors to 1.65(for 3.3V case) volts, see figure 13 for schematic of internal biasing of differential I/O’s. The CRU has the option of either using the CMU’s reference clock or its own independent reference clock “CRUREFCLK”. This is accomplished with the control signal “CRUREFSEL”. The “CRUREFCLK” should be used if the system is being operated in either a regeneration or looptiming mode. In either of these modes the quality of the “CRUREFCLK” is not a concern, thus it can be driven by a simple 77.76MHz crystal, the key is its’ independent of the CMU’s reference clock. Table 1: Recommended External Capacitor Values Reference Frequency [MHz] 19.44 77.76 Divide Ratio 32 8 CP 0.1 0.1 CN 0.1 0.1 Type X7R X7R Size 0603/0805 0603/0805 Tol. +/-10% +/-10% Figure 6: External Integrator Capacitor CP = 0.1 µF CP1 CP2 + - CN1 CN2 CN = 0.1 µF G52221-0, Rev. 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Data Sheet VSC8117 Clock Recovery The fully monolithic Clock Recovery Unit (CRU) consists of a Phase Detector, a Frequency Detector, a Loop Filter and a Voltage Controlled Oscillator (VCO). The phase detector compares the phase information of the incoming data with the recovered clock. The frequency detector compares the frequency component of the data input with the recovered clock to provide the pull in energy during lock acquisition. The Loop Filter integrates the phase information from the phase and frequency detectors and provides the control voltage to the VCO. Jitter Tolerance Jitter Tolerance is the ability of the Clock Recovery Unit to track timing variation in the received data stream. The Bellcore and ITU specifications allow the received optical data to contain jitter. The amount that must be tolerated is a function of the frequency of the jitter. At high frequencies the specifications do not require the CRU to tolerate large amounts, whereas at low frequencies many unit intervals (bit times) of jitter have to be tolerated. The CRU is designed to tolerate this jitter with margin over the specification limits, see Figure 7. The CRU obtains and maintains lock based on the data transition information. When there is no transition on the data stream, the recovered clock frequency can drift. The VSC8117 can maintain lock over 100 bits of no switching on the data stream. Figure 7: Jitter Tolerance JITTER(UI P-P) 150 Bellcore Requirement 60 VSC8117 Guaranteed Jitter Tolerance 15 6 1.5 0.5 0.15 10 30 300 25K 250K 2.5M JITTER FREQ(HZ) Page 8 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52221-0, Rev 4.1 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 AC Timing Characteristics ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Figure 8: Receive High Speed Data Input Timing Diagram TRXCLK RXCLKIN+ RXCLKINTRXSU RXDATAIN+ RXDATAINTRXH Table 2: Receive High Speed Data Input Timing Table (STS-12 Operation) Parameter TRXCLK TRXSU TRXH Receive clock period Serial data setup time with respect to RXCLKIN Serial data hold time with respect to RXCLKIN Description Min 400 100 Typ 1.608 - Max - Units ns ps ps Table 3: Receive High Speed Data Input Timing Table (STS-3 Operation) Parameter TRXCLK TRXSU TRXH Receive clock period Serial data setup time with respect to RXCLKIN Serial data hold time with respect to RXCLKIN Description Min 1.5 1.5 Typ 6.43 - Max - Units ns ns ns Figure 9: Transmit Data Input Timing Diagram TCLKOUT TXLSCKOUT TINSU TINH TXIN [7:0] G52221-0, Rev. 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 4: Transmit Data Input Timing Table (STS-12 Operation) Parameter TCLKOUT TINSU TINH Data Sheet VSC8117 Min 1.0 1.0 Description Transmit data output byte clock period Transmit data setup time with respect to TXLSCKOUT Transmit data hold time with respect to TXLSCKOUT Typ 12.86 - Max - Units ns ns ns Table 5: Transmit Data Input Timing Table (STS-3 Operation) Parameter TCLKOUT TINSU TINH Description Transmit data output byte clock period Transmit data setup time with respect to TXLSCKOUT Transmit data hold time with respect to TXLSCKOUT Min 1.0 1.0 Typ 51.44 - Max - Units ns ns ns Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case Figure 10: Receive Data Output Timing Diagram TRXCLKIN RXCLKIN+ RXCLKINTRXLSCK RXLSCKOUT TRXVALID RXOUT [7:0] A1 A2 A2 A2 A2 TRXVALID FP Table 6: Receive Data Output Timing Table (STS-12 Operation) Parameter TRXCLKIN TRXLSCK TRXVALID TPW Receive clock period Receive data output byte clock period Time data on RXOUT [7:0] and FP is valid before and after the rising edge of RXLSCKOUT Pulse width of frame detection pulse FP Description Min 4.0 - Typ 1.608 12.86 12.86 Max - Units ns ns ns ns Page 10 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52221-0, Rev 4.1 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 Parameter TRXCLKIN TRXLSCKT TRXVALID TPW Receive clock period ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 7: Receive Data Output Timing Table (STS-3 Operation) Description Receive data output byte clock period Time data on RXOUT [7:0] and FP is valid before and after the rising edge of RXLSCKOUT Pulse width of frame detection pulse FP Min 22 - Typ 6.43 51.44 51.44 Max - Units ns ns ns ns Data Latency The VSC8117 contains several operating modes, each of which exercise different logic paths through the part. Table 10 bounds the data latency through each path with an associated clock signal. Table 8: Data Latency Circuit Mode Receive Facilities Loopback Description MSB at RXDATAIN to data on RXOUT [7:0] MSB at RXDATAIN to MSB at TXDATAOUT Clock Reference RXCLKIN RXCLKIN Range of Clock cycles 25-35 2-4 Clock Recovery Unit Table 9: Reference Frequency for the CRU CRUREFSEL CRUREFCLK Frequency [MHz] 77.76 ± 500ppm 77.76 ± 500ppm STS12 1 0 Output Frequency [MHz] 622.08 155.52 1 1 0 Uses CMU’s Reference Clock (See Table 10 below) Clock Multiplier Unit Table 10: Reference Frequency Selection and Output Frequency Control Reference Frequency [MHz] 19.44 77.76 19.44 77.76 STS12 1 1 0 0 CMUFREQSEL 1 0 1 0 Output Frequency [MHz] 622.08 622.08 155.52 155.52 G52221-0, Rev. 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 11: Clock Multiplier Unit Performance Name RCd RCj RCj RCf (1) (2) Data Sheet VSC8117 Min 40 Description Reference clock duty cycle Reference clock jitter (RMS) @ 77.76 MHz ref (1) Reference clock jitter (RMS) @ 19.44 MHz ref (1) Reference clock frequency tolerance (2) Typ Max 60 13 5 Units % ps ps ppm -20 +20 These Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirements (< 10 mUIrms) Needed to meet SONET output frequency stability requirements Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter. AC Characteristics Table 12: PECL and TTL Outputs Parameters TR,TTL TF,TTL TR,PECL TF,PECL Description TTL Output Rise Time TTL Output Fall Time PECL Output Rise Time PECL Output Fall Time Min — — — — Typ 2 1.5 350 350 Max — — — — Units ns ns ps ps Conditions 10-90% 10-90% 20-80% 20-80% DC Characteristics Table 13: PECL and TTL Inputs and Outputs Parameters VOH VOL VOCM Description Output HIGH voltage (PECL) Output LOW voltage (PECL) O/P Common Mode Range (PECL) Differential Output Voltage (PECL) Min — 0.7 Typ — — Max VDDP – 0.9V — Units V V Conditions — — — 1.1 — VDDP – 1.3V V ∆VOUT75 600 — 1300 mV 75Ω to VDDP – 2.0 V Page 12 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52221-0, Rev 4.1 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 Parameters ∆VOUT50 ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 13: PECL and TTL Inputs and Outputs Description Differential Output Voltage (PECL) Input HIGH voltage (PECL) Input LOW voltage (PECL) Differential Input Voltage (PECL) I/P Common Mode Range (PECL) Output HIGH voltage (TTL) Output LOW voltage (TTL) Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Min 600 Typ — Max 1300 Units mV Conditions 50Ω to VDDP – 2.0 V For single ended For single ended — — IOH = -1.0 mA IOL = +1.0 mA — — 2.0V< VIN < 5.5V, Typical@2.4V -0.5V < VIN < 0.8V VIH VIL ∆VIN VDDP – 0.9V 0 400 1.5 – ∆VIN/2 — — — VDDP – 0.3V VDDP – 1.72V 1600 V V mV VICM VOH VOL VIH VIL IIH IIL — VDDP – 1.0 – ∆VIN/2 — 0.5 5.5 0.8 500 -500 V 2.4 — 2.0 0 — — — — — — 50 — V V V V µA µA Power Dissipation Table 14: Power Supply Currents Parameter IDD PD Power supply current from VDD Power dissipation (worst case) Description (Max) 480 1.6 Units mA W G52221-0, Rev. 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Data Sheet VSC8117 Absolute Maximum Ratings(1) Power Supply Voltage (VDD) Potential to GND .................................................................................-0.5V to +4V PECL I/O Supply Voltage (VDDP) Potential to GND..........................................................................-0.5V to +6V DC Input Voltage (PECL inputs).......................................................................................... -0.5V to VDDP +0.5V DC Input Voltage (TTL inputs) ......................................................................................................... -0.5V to 5.5V DC Output Voltage (TTL Outputs)........................................................................................ -0.5V to VDD + 0.5V Output Current (TTL Outputs) ................................................................................................................. +/-50mA Output Current (PECL Outputs)................................................................................................................+/-50mA Case Temperature Under Bias .........................................................................................................-55o to +125oC Storage Temperature..................................................................................................................... -65oC to +150oC Maximum Input ESD (Human Body Model).............................................................................................. 1500 V Note: Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Power Supply Voltage (VDD) ................................................................................................................. +3.3V ± 5 % PECL I/O Supply Voltage (VDDP).......................................................................................... +3.3V or +5.0V ± 5 % Commercial Operating Temperature Range ..................................................................... 0o ambient to 70oC case Extended Operating Temperature Range........................................................................ 0 o ambient to 115oC case Industrial Operating Temperature Range ...................................................................... -40 o ambient to 85oC case Page 14 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52221-0, Rev 4.1 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 Package Pin Descriptions Table 15: Pin Identification Signal RESET LOOPTIM0 CMUFREQSEL VDDP TXDATAOUT+ TXDATAOUTLOSDETEN_ RXCLKIN+ RXCLKINVDDP OOF DSBLCRU RXDATAIN+ RXDATAINVDD REFCLKP+ REFCLKPVDD RXOUT0 RXOUT1 VSS RXOUT2 RXOUT3 RXOUT4 RXOUT5 RXOUT6 RXOUT7 VSS RXLSCKOUT FP VDD CRUREFCLK ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O I I I Level TTL TTL TTL +3.3/+5V Pin Description Resets frame detection, dividers, controls; active high Enable loop timing operation; active HIGH Reference clock frequency select, refer to table 10 +3.3V or +5V Power Supply for PECL I/Os Transmit output, high speed differential data + Transmit output, high speed differential data Enables internal LOS detection (active low). Receive high speed differential clock input+ Receive high speed differential clock input+3.3V or +5V Power Supply for PECL I/Os Out Of Frame; Frame detection initiated with high level Disable on-chip clock recovery unit; active high Receive high speed differential data input+ Receive high speed differential data input+3.3V Power Supply PECL reference clock input+ PECL reference clock input+3.3V Power Supply Receive output data bit0 Receive output data bit1 Ground Receive output data bit2 Receive output data bit3 Receive output data bit4 Receive output data bit5 Receive output data bit6 Receive output data bit7 Ground Receive byte clock output Frame detection pulse +3.3V Power Supply Optional external CRU reference clock @77.76MHz O O I I I PECL PECL TTL PECL PECL +3.3/+5V I I I I TTL TTL PECL PECL +3.3V I I PECL PECL +3.3V O O TTL TTL GND O O O O O O TTL TTL TTL TTL TTL TTL GND O O TTL TTL +3.3V I TTL G52221-0, Rev. 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 15: Pin Identification Signal LOSPECL VDD VSS REFCLK VSSA VDDA CP1 CN1 CN2 CP2 VDDA VSSA VSS VSS VDD VDD TXLSCKOUT TXIN7 TXIN6 VSS TXIN5 TXIN4 TXIN3 TXIN2 TXIN1 TXIN0 STS12 CRUREFSEL VDD EQULOOP FACLOOP CRUEQLP Data Sheet VSC8117 Pin Description Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I/O I Level PECL +3.3V GND Loss of Signal Control- Single ended PECL input; active low +3.3V Power Supply Ground Reference clock input, refer to table 10 Analog Ground (CMU) Analog Power Supply (CMU) CMU external capacitor (see Figure 6, and Table 1) CMU external capacitor (see Figure 6, and Table 1) CMU external capacitor (see Figure 6, and Table 1) CMU external capacitor (see Figure 6, and Table 1) Analog Power Supply (CRU) Analog Ground (CRU) Ground Ground +3.3V Power Supply +3.3V Power Supply Transmit byte clock out Transmit input data bit7 Transmit input data bit6 Ground Transmit input data bit5 Transmit input data bit4 Transmit input data bit3 Transmit input data bit2 Transmit input data bit1 Transmit input data bit0 155Mb/s or 622Mb/s mode select, refer to table 10 Selects between CMU’s or CRU’s REFCLK +3.3V Power Supply Equipment loopback, loops low speed byte wide transmit input data to receive output bus Facility loopback, loops high speed receive data and clock directly to transmit outputs. Loops TXDATAOUT to the CRU replacing RXDATAIN+/- I TTL GND +3.3V Analog Analog Analog Analog +3.3V GND GND GND +3.3V +3.3V O I I TTL TTL TTL GND I I I I I I I I TTL TTL TTL TTL TTL TTL TTL TTL +3.3V I I I TTL TTL TTL Page 16 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52221-0, Rev 4.1 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 Package Information ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery 64 Pin PQFP Package Drawings D Item D1 mm 2.45 2.00 13.20 10.00 13.20 10.00 0.88 0.50 0.22 0° - 7° .30 .20 Tol. MAX +.10/-.05 ±.25 ±.10 ±.25 ±.10 ±.15/-.10 BASIC ±.05 A 64 49 48 1 A2 D D1 E E1 E1 E L e b 16 33 θ R TYP TYP 17 10o TYP 32 R1 A A2 100 TYP e R A R1 STANDOFF 0.25 MAX. 0.17 MAX. 0.25 L θ b 0.102 MAX. LEAD COPLANARITY NOTES: All drawings not to scale All units in mm unless otherwise noted. 10 x 10 mm Package # 101-266-1 14 x 14 mm Package # 101-262-1 G52221-0, Rev. 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 17 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Data Sheet VSC8117 Package Thermal Characteristics The VSC8117 is packaged into a thermally-enhanced plastic quad flatpack (PQFP). This package adheres to the industry-standard EIAJ footprint for a 10x10mm body but has been enhanced to improve thermal dissipation with the inclusion of an exposed Copper Heat Spreader. The package construction is as shown in Figure 10. Figure 11: Package Cross Section Copper Heat Spreader Insulator Lead Wire Bond Die Plastic Molding Compound The thermal resistance for the VSC8117 package is improved through low thermal resistance paths from the die to the exposed surface of the heat spreader and from the die to the lead frame through the heat spreader overlap of the lead frame. Table 16: 64-Pin PQFP Thermal Resistance Symbol θjc θca θca-100 θca-200 θca-400 θca-600 Description Thermal resistance from junction to case Thermal resistance from case to ambient in still air including conduction through the leads for a non-thermally saturated board. Thermal resistance from case to ambient in 100 LPFM air Thermal resistance from case to ambient in 200 LPFM air Thermal resistance from case to ambient in 400 LPFM air Thermal resistance from case to ambient in 600 LPFM air Value 2.5 37 31 28 24 22 Units oC/W oC/W oC/W oC/W oC/W oC/W The VSC8117QB1 is designed to operate at a maximum case temperature of up to 115oC. The user must guarantee that the maximum case temperature specification is not violated. Given the thermal resistance of the package in still air, the user can operate the VSC8117QB1 in still air if the ambient temperature does not exceed 55oC (55oC = 115oC - 1.6W * 37oC/W). If operation above this ambient temperature is required, then an appropriate heatsink must be used with the part or adequate airflow must be provided. Page 18 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52221-0, Rev 4.1 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 Ordering Information The order number for this product are: Part Number VSC8117QP: ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Device Type 622Mb/s Mux/Dmux with CMU and CRU in 64 Pin PQFP Commercial Temperature, 0°C ambient to 70°C case 622Mb/s Mux/Dmux with CMU and CRU in 64 Pin PQFP Extended Temperature, 0°C ambient to 115°C case 622Mb/s Mux/Dmux with CMU and CRU in 64 Pin PQFP Industrial Temperature, -40°C ambient to 85°C case VSC8117QP1 VSC8117QP2 Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time without prior notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to placing orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. G52221-0, Rev. 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 19 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Data Sheet VSC8117 Application Notes DC Coupling and Terminating High-speed PECL I/Os The high speed signals on the VSC8117 (RXDATAIN, RXCLKIN, TXDATAOUT, REFCLKP, LOSPECL) use 3.3/5V programmable PECL I/Os which can be direct coupled to either +3.3V PECL or +5V PECL signals from the optics. These PECL levels are essentially ECL levels shifted positive by 3.3 volts or 5 volts. These PECL I/Os are referenced to the VDDP supply (VDDP) and are terminated to ground. To program these I/Os for either 3.3V or 5V interface, the VDDP pin (pins 4 and 10) is required to connect to 3.3V or 5V supplies accordingly. AC Coupling and Terminating High-speed PECL I/Os If the optics modules provide ECL level interface, the high speed signals can be AC coupled to the VSC8117 as well. The PECL receiver inputs of the VSC8117 are internally biased at VDD/2. Therefore, ACcoupling to the VSC8117 inputs is accomplished by providing the pull-down resistor for the open-source PECL output and an AC-coupling capacitor used to eliminate the DC component of the output signal. This capacitor allows the PECL receivers of the VSC8117 to self-bias via its internal resistor divider network (see Figure 13). The PECL output drivers are capable of sourcing current but not sinking it. To establish a LOW output level, a pull-down resistor, traditionally connected to VDD-2.0V, is needed when the output FET is turned off. Since VDD-2.0V is usually not present in the system, the resistor could be terminated to ground for convenience. The VSC8117 output drivers should be either AC-coupled to the 5.0V PECL inputs of the optics module, or translated (DC level shift). Appropriate biasing techniques for setting the DC-level of these inputs should be employed. The dc biasing and 50 ohm termination requirements can easily be integrated together using a thevenin equivalent circuit as shown in Figure 12. The figure shows the appropriate termination values when interfacing 3.3V PECL to 5.0V PECL. This network provides the equivalent 50 ohm termination for the high speed I/Os and also provides the required dc biasing for the receivers of the optics module. Table 17 contains recommended values for each of the components. TTL Input Structure The TTL inputs of the VSC8117 are 3.3V TTL which can accept 5.0V TTL levels within a given set of tolerances (see Table 13). The input structure, shown in Figure 13, uses a current limiter to avoid overdriving the input FETs. Layout of the High Speed Signals The routing of the High Speed signals should be done using good high speed design practices. This would include using controlled impedance lines and keeping the distance between components to an absolute minimum. PECL signals need 50-ohm traces, and TTL signals need 75-ohm traces. In addition, stubs should be kept at a minimum as well as any routing discontinuities. This will help minimize reflections and ringing on the high speed lines and insure the maximum eye opening. In addition the output pull down resistor should be placed as close to the VSC8117 pin as possible while the AC-coupling capacitor and the biasing resistors should be placed as close as possible to the optics input pin. The same is true on the receive circuit side. Using small outline components and minimum pad sizes also helps in reducing discontinuities. Page 20 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52221-0, Rev 4.1 1/8/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Ground Planes The ground plane for the components used in the High Speed interface should be continuous and not sectioned in an attempt to provide isolation to various components. Sectioning of the ground planes tends to interfere with the ground return currents on the signal lines. In addition, the smaller the ground planes the less effective they are in reducing ground bounce noise and the more difficult to decouple. Sectioning of the positive supplies can provide some isolation benefits. Figure 12: AC Coupled High Speed I/O +3.3V DRIVER (Optics Module) PC Board Trace R1 GND GND Note: Only one side of a differential signal is shown. C1 PC Board Trace R2 GND C2 VSC8117 PECL I/O +5.0V R3 RECEIVER (Optics Module) R4 GND Table 17: AC Coupling Component Values Component R1 R2 R3 R4 C1, C2, C3, C4 Value 270 ohms 75 ohms 68 ohms 190 ohms .01uf High Frequency Tolerance 5% 5% 1% 1% G52221-0, Rev. 4.1 1/8/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 21 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Figure 13: Input Structures VDD +3.3 V VDDP +3.3 /+5 V Data Sheet VSC8117 +3.3 V INPUT INPUT Current Limit R INPUT R GND GND All Resistors 3.3K REFCLK and TTL Inputs High Speed Differential Input (RXDATAIN+/RXDATAIN-) (RXCLKIN+/RXCLKIN-) (REFCLKP+/REFCLKP-) Page 22 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52221-0, Rev 4.1 1/8/00