VSC8124

VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8124 Features • Four Channel 2.488 Gb/s Data Recovery • SONET Quality Jitter Tolerance • Fastlock Data Acquisition less than 200 Bit Times • Loss of Signal Indicators • Long Strings of Static Data Tolerated by the Clock Recovery Circuit without Loss of Signal • First Order Clock Recovery Loop Minimizes Jitter Accumulation 2.488 Gb/s Quad Data Re-timer • Differential on Chip Terminated Serial Data I/O • Bypass for OC3, OC12 Data Rates • 155.52 MHz Reference Clock Frequency • 3.3V Supply Operation • 14 x 14mm, 100 Pin Thermally Enhanced TQFP Package General Description The VSC8124 is a four channel, 2.5 Gb/s data re-timer for cleaning up data downstream of optical links or cross point switches. Serial data at the 2.5 Gb/s rate is independently re-timed on four channels, and driven differentially by CML drivers. The re-timing function on each channel can be individually bypassed for lower rate signals or test purposes. The VSC8124 provides four independent loss of signal indicators in the event of loss of synchronous data transitions. G52271-0, Rev. 1.14 2/23/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gb/s Quad Data Re-timer Target Specification VSC8124 VSC8124 Block Diagram SD3+ CML SD3RTBYP3 TTL 1 0 CML RDAT3+ RDAT3- RDAT2+ LOSREL TTL RTBYP2 TTL SD2+ CML SD2REFCK0+ PECL REFCK0REFCK1+ PECL REFCK1REFCK+ TTL Clock Recovery Unit CML RDAT2LOSALMN 1 0 TTL LOS3N 0 1 Clock Recovery Unit LOS Logic TTL LOS2N TTL LOS1N SD1+ CML SD11 0 TTL LOS0N RTBYP1 TTL FASTLOCK Clock Recovery Unit CML RDAT1+ RDAT1- TTL RTBYP0 TTL 1 0 CML RDAT0+ RDAT0- SD0+ CML SD0- Clock Recovery Unit Page 2 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52271-0, Rev. 1.14 2/23/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8124 Functional Description Reference Clock 2.488 Gb/s Quad Data Re-timer A clean reference clock should be provided to meet jitter specifications. An arbitrary discontinuity in reference clock phase can be tolerated without data error at slightly reduced jitter tolerance. (See Table 1) Phase changes must not occur more often than every 20 µs. Serial data transition density must average ≥ 0.5 for that period. Two reference clock input ports are provided. The REFSEL pin selects the active port. When REFSEL is not driven, it floats low, selecting REFCK0. Changing REFSEL implies a phase change. Clock Recovery The incoming serial data on each channel is presented to a clock recovery and data re-timing circuit. For each channel, a phase detector and low pass filter force a local clock to track the average phase of the incoming serial data. The low pass filter is first order to prevent jitter peaking in cascaded devices. Figure 1: Serial Input Data Eye Diagram JT Eye Opening Period Table 1: Serial Input Data Specification Parameter JT JT JT Period Description Jitter tolerance Jitter tolerance Jitter tolerance Min 220 150 190 - Typ 170 210 401.88 Max - Units ps ps ps ps Conditions Normal Operation Fast Lock Mode Within 20µs after REFCLK phase change NOTE: 1) Jitter tolerance is measured at worst case power supply and temperature, using 155.52 MHz clean reference clock (REFCK to meet 2.0 ps RMS jitter at less than 10 Mhz in bandwidth), and 600mV swing differential PRBS data with150ps maximum rise time. 2) Jitter tolerance and re-timed data jitter are degraded in FASTLOCK mode. 3) Reference clock frequency tolerance: ∆f