VSC8140

VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 Features • 2.48832Gb/s 16-Bit Transceiver • Targeted for SONET OC-48 / SDH STM-16 Applications • LVPECL Low-Speed Interface • On-chip PLL-Based Clock Generator • High-Speed Clock Output With Power-Down Option • Supports Parity at the 16-Bit Parallel Transmit and Receive Interfaces 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator • Provides Equipment, Facilities and Split Loopback Modes as well as Loop Timing Modes • Loss of Signal (LOS) Detect input • Meets Bellcore Jitter Performance Specifications • Single +3.3V Supply • 2.25 Watts Typical Power Dissipation • Packages: 128-pin PQFP or 208-pin TBGA General Description The VSC8140 is a SONET/SDH compatible transceiver with integrated clock generator for use in SONET/ SDH systems operating at a 2.48832Gb/s data rate. The internal clock generator uses a Phase-Locked Loop (PLL) to multiply either a 77.76MHz or 155.52MHz reference clock in order to provide the 2.48832GHz clock for internal logic and output retiming. The 16-bit parallel interface incorporates an on-board FIFO eliminating loop timing design issues by providing a flexible parallel timing architecture. In addition, the device provides both facility and equipment loopback modes and two loop timing modes. The VSC8140 operates using a 3.3V power supply, and is available in either a thermally-enhanced 128-PQFP or a thermally-enhanced 208-pin TBGA package. VSC8140 Block Diagram LOS POL RXIN+ RXINRXCLKIN+ RXCLKINDQ voltage gen. Output Register VREFOUT VREFIN RXOUT0 RXOUT15 RXPARITYOUT RXCLK16O+ RXCLK16O- EQULOOP CLK128O+ CLK128ORXCLKO_FREQSEL OVERFLOW FIFORESET TXOUT+ TXOUTTXCLKOUT+ TXCLKOUTFACLOOP QD Divide by 128 Divide by 16 Divide by 2 RXCLKO16_32+ RXCLKO16_32PARMODE TXCLK16I+ TXCLK16IInput Register TXIN0 Write Pointer FIFO CNTRL 16x5 FIFO TXIN15 TXPARITYIN Read Pointer Divide by 16 TXCLK16O+ TXCLK16OLPTIMCLK+ LPTIMCLK- LOOPTIM0 2.48832GHz PLL PARERR REFCLK+ REFCLKLOOPTIM1 REF_FREQSEL G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Data Sheet VSC8140 Functional Description Transmitter Low-Speed Interface The Upstream Device should use the TXCLK16O as the timing source for its final output latch (see Figure 1). The Upstream Device should then generate a TXCLK16I that is phase-aligned with the data. The VSC8140 will latch TXIN[15:0]± on the rising edge of TXCLK16I+. The data must meet setup and hold times with respect to TXCLK16I (see Table 1). A FIFO exists within the VSC8140 to eliminate difficult system loop timing issues. Once the PLL has locked to the reference clock, RESET must be held low for a minimum of five CLK16 cycles to initialize the FIFO, then RESET should be set high and held constant for continuous FIFO operation. For the transparent mode of operation (no FIFO), simply hold RESET at a constant low state (see Figure 2). The use of a FIFO permits the system designer to tolerate an arbitrary amount of delay between TXCLK16O and TXCLK16I. Once RESET is asserted and the FIFO initialized, the delay between TXCLK16O and TXCLK16I can decrease or increase up to one period of the low-speed clock (6.4ns). Should this delay drift exceed one period, the write pointer and the read pointer could point to the same word in the FIFO, resulting in a loss of transmitted data (a FIFO overflow). In the event of a FIFO overflow, an active low OVERFLOW signal is asserted (for a minimum of five TXCLK16I cycles) which can be used to initiate a reset signal from an external controller. The TXCLK16O± output driver is a LVPECL output driver designed to drive a 50Ω transmission line. The transmission line can be DC terminated with a split-end termination scheme (see Figure 3), or DC terminated by 50Ω to VCC-2V on each line (see Figure 4). At any time, the equivalent split-end termination technique can be substituted for the traditional 50Ω to VCC-2V on each line. AC-coupling can be achieved by a number of methods. Figure 5 illustrates an AC-coupling method for the occasion when the downstream device provides the bias point for AC-coupling. Figure 1: Low-Speed Systems Interface OVERFLOW 16 x 5 FIFO TXCLK16I write 16 TXCLK16O read REFCLK 2.48832GHz PLL Div 16 VSC8140 Page 2 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Figure 2: Enabling FIFO Operation PLL locked to reference clock. Minimum 5 CLK16 cycles FIFO Mode Operation Transparent Mode Operation RESET Holding RESET “low” for a minimum of 5 CLK16 cycles, then setting “high” enables FIFO operation. Holding RESET constantly “low” bypasses the FIFO for transparent mode operation. Figure 3: DC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs VSC8140 V Split-end equivalent termination is ZO to VTERM CC R1 = 125Ω R2 = 83Ω, ZO=50Ω, VTERM= VCC-2V Zo R1 R1 downstream Zo R1||R2 = ZO VCCR2 + VEER1 R1+R2 = VTERM R2 VEE R2 Figure 4: DC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs downstream VSC8140 Zo R1 =50Ω VCC-2V R1 =50Ω VCC-2V G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Data Sheet VSC8140 Figure 5: AC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs VSC8140 Zo Zo 50Ω 50Ω 100nF downstream bias point generated internally 100nF VCC-2V Receiver Low-Speed Interface The demultiplexed serial stream is made available by a 16-bit single-ended LVPECL interface RXOUT[15:0] with accompanying differential LVPECL divide-by-16 clock RXCLK16O± and selectable LVPECL divide-by-16 or -32 clock RXCLK16_32O±. RXCLKO_FREQSEL is used to select RXCLK16_32O ± . RXCLKO_FREQSEL = “0” designates RXCLK16_32O± output as 77.76MHz, RXCLKO_FREQSEL = “1” designates RXCLK16_32O± output as 155.52MHz. The RXCLK16O and RXCLK16_32O output drivers are designed to drive a 50Ω transmission line. The transmission line can be DC terminated with a split-end termination scheme (see Figure 3), or DC terminated by 50Ω to VCC-2V on each line (see Figure 4). AC-coupling can be achieved by a number of methods. Figure 5 illustrates an AC-coupling method for the occasion when the downstream device provides the bias point for AC-coupling. The divide-by-16 output (RXCLK16O) or the divide-by-16 or -32 output (RXCLK16_32O) can be used to provide an external looptiming reference clock (after external filtering with a 1x REFCLK PLL) for the clock multiplication unit on the VSC8140. The RXOUT[15:0] output drivers are designed to drive a 50Ω transmission line which can be DC terminated with a split-end termination scheme (see Figure 6), or a traditional termination scheme (see Figure 7). Figure 6: Split-end DC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs Split-end equivalent termination is ZO to VTERM R1 = 125Ω R2 = 83Ω, ZO=50Ω, VTERM= VCC-2V VCC R1 = 125Ω VSC8140 Zo R1||R2 = Zo VCCR2 + VEER1 R1+R2 = VTERM R2 = 83Ω VEE Page 4 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Figure 7: Traditional DC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs VSC8140 Zo R1 =50Ω VCC-2V The RXOUT[15:0] output drivers can also be appropriately AC-coupled by a number of methods, however, DC-coupling is preferred since there is no guarantee of transition density for individual bits in the 16-bit word. Figure 8 illustrates an AC-coupling method for the occasion when the downstream device provides the bias point for AC-coupling. Figure 9 illustrates an AC-coupling method for the occasion when the bias point needs to be generated externally. The resistor values in Figure 9 were selected to generate a bias point of 1.98V, the mid-point for LVPECL VOH and VOL as specified for the VSC8140. Resistor values should be selected to generate the necessary bias point for the downstream device. Figure 8: AC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs VSC8140 Zo 100nF downstream bias point generated internally R1 = 50Ω VCC-2V G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Figure 9: AC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs Data Sheet VSC8140 VSC8140 VCC R1 = 125Ω Zo R2 = 83Ω VEE VCC R3 =83Ω downstream 100nF bias point generated externally R4 = 125Ω VEE Parity Systems employing internal parity are supported by the VSC8140. On the transmit side, a parity check is performed between the TXPARITYIN input and the 16 TXIN[15:0] bits. PARMODE is used to select even or odd parity expected for these 17 bits. (TXIN[15:0] and TXPARITYIN). PARMODE = “0” selects odd, PARMODE = “1” selects even. The PARERR output (parity error output) is asserted active high when the parity of the 17 bits (TXIN[15:0] and TXPARITYIN) does not conform to the expected parity designated by PARMODE. PARERR becomes available TDV after the rising edge of TXCLK16I. PARERR is a NRZ pulse that is updated every 6.4 ns, i.e., the period of TXCLK16I. The timing relationship of PARERR to TXCLK16I is shown in Figure 17. The PARERR pin may be left open if parity is unused. On the receive side, the parity output (RXPARITYOUT) is simply the XOR of all 16 outputs. Loss of Signal The VSC8140 has a TTL input LOS to force the part into a Loss of Signal (LOS) state. Most optics have a TTL output usually called Signal Detect (SD), based on the optical power of the incoming light stream. Depending on the optics manufacturer, this signal is either active high or low. To accommodate polarity differences, the internal Loss of Signal is generated when the POL and LOS inputs are of opposite states. Once active, all zeroes “0” will be propagated downstream using the transmit clock until the optical signal is regained and LOS and POL are in the same logic state. Page 6 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Figure 10: Facility Loopback Data Path RXIN+ RXINRXCLKIN+ RXCLKIN- DQ 1:16 Serial to Parallel RXOUT[15:0] RXCLK16O RXCLK32O TXOUT+ TXOUTTXCLKOUT+ TXCLKOUTFACLOOP QD 1 0 1 0 16:1 Parallel to Serial 2.48832GHz PLL Facility Loopback The facility loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set high, the Facility Loopback mode is activated and the high-speed serial receive data (RXIN) is presented at the high-speed transmit output (TXOUT), as depicted in Figure 10. In addition, the high-speed receive clock input (RXCLKI) is selected and presented at the high-speed transmit clock output (TXCLKOUT). In Facility Loopback mode, the high-speed receive data (RXIN) is also converted to parallel data and presented at the low-speed receive output pins (RXOUT[15:0]). The receive clock (RXCLKIN) is also divided down and presented at the low-speed clock output (RXCLK16O). Equipment Loopback Data Path The Equipment Loopback function is controlled by the EQULOOP signal, which is active high. When the Equipment Loopback mode is activated, the high-speed transmit data generated from the parallel to serial conversion of the low-speed data (TXIN[15:0]) is selected and converted back to parallel data in the receiver section and presented at the low-speed parallel data outputs (RXOUT[15:0]), as shown in Figure 11. The internally generated OC-48 clock is used to generate the low-speed receive output clocks (RXCLK16O and RXCLK16_32O). In Equipment Loopback mode, the transmit data (TXIN[15:0]) is serialized and presented at the high-speed output (TXOUT) along with the high-speed transmit clock (TXCLKOUT) which is generated by the on-chip PLL. G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Figure 11: Equipment Loopback Data Path RXIN+ RXINRXCLKIN+ RXCLKINEQULOOP TXOUT+ TXOUTTXCLKOUT+ TXCLKOUT2.48832GHz PLL DQ 0 1 0 1 1:16 Serial to Parallel Data Sheet VSC8140 RXOUT[15:0] RXCLK16O RXCLK32O TXIN[15:0] QD 16:1 Parallel to Serial TXCLK16I TXCLK16O Figure 12: Split Loopback Datapaths RXIN+ RXINRXCLKIN+ RXCLKIN- DQ 0 1 0 1 1:16 Serial to Parallel RXOUT[15:0] RXCLK16O RXCLK32O TXOUT+ TXOUTTXCLKOUT+ TXCLKOUTFACLOOP QD 1 0 1 0 16:1 Parallel to Serial TXIN[15:0] TXCLK16I TXCLK16O 2.48832GHz PLL EQULOOP Split Loopback Equipment and Facility Loopback modes can be enabled simultaneously. In this case, high-speed serial data received (RXIN) and clock (RXCLKIN) are muxed through to the high-speed serial outputs (TXOUT and TXCLKOUT). The low-speed 16-bit transmit stream (TXIN[15:0]) is muxed into the low-speed 16-bit receive output stream (RXOUT[15:0]). See Figure 12. Looptiming LOOPTIM0 mode bypasses the PLL when LOOPTIM0 is asserted high. In this mode, the PLL is bypassed using the receive high-speed clock (RXCLKIN), and the entire part is synchronously clocked from a single external source. Page 8 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator When LOOPTIM1 is asserted high, the RXCLK16_32O or RXCLK16O output can be tied to the LPTIMCLK input. In order to meet jitter transfer, the RXCLK16_32O or RXCLOCK16O needs to be filtered by a 1X PLL circuit with a narrow pass characteristic. The part is forced out of this mode in Equipment Loopback to prevent the PLL from feeding its own clock back. Clock Generator An on-chip PLL generates the 2.48832GHz transmit clock from the externally provided REFCLK input. The on-chip PLL uses a low phase noise reactance-based Voltage Controlled Oscillator (VCO) with an on-chip loop filter (with two external 0.1µF peaking capacitors). The loop bandwidth of the PLL is within the SONET specified limit of 2MHz. The customer can select to provide either a 77.76MHz reference, or 2x of that reference, 155.52MHz. REF_FREQSEL is used to select the desired reference frequency. REF_FREQSEL = “0” designates REFCLK input as 77.76MHz, REF_FREQSEL = “1” designates REFCLK input as 155.52MHz. The REFCLK should be of high quality since noise on the REFCLK below the loop bandwidth of the PLL will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a VCXO may be required to avoid passing REFCLK noise with greater than 2ps RMS of jitter to the output. The VSC8140 will output the REFCLK noise in addition to the intrinsic jitter from the VSC8140 itself during such conditions. Loop Filter The PLL on the VSC8140 employs an internal loop filter with off-chip peaking capacitors. The PLL design is fully differential, therefore the loop filter must also be fully differential. One capacitor should be connected between FILTAO and FILTAI, with the other connected between FILTAON and FILTAIN. Recommended capacitors are low-inductance 0.1µF 0603 ceramic SMT X7R devices with a voltage rating equal to or greater than 10V. Figure 13: High-Speed Output Termination VCC 50Ω 50Ω 100Ω Pre-Driver Z0 = 50Ω VEE G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Data Sheet VSC8140 Transmitter High-Speed Data and Clock Outputs The high-speed data and clock output drivers (TXOUT and TXCLKOUT) consist of a differential pair designed to drive a 50Ω transmission line. The transmission line should be terminated with a 100 Ω resistor at the load between true and complement outputs (see Figure 13). No connection to a termination voltage is required. The output driver is back terminated to 50Ω on-chip, providing a snubbing of any reflections. If used single-ended, the high-speed output driver must still be terminated differentially at the load with a 100Ω resistor between true and complement outputs. In order to save power, the high-speed transmit clock output (TXCLKOUT) can be powered down by connecting the power pins VEEP_CLK and VEE_PWRDN to the VCC supply instead of to VEE. Figure 14: AC Termination of Low-Speed LVPECL REFCLK and LPTIMCLK Inputs Chip Boundary VCC = 3.3V R1||R2 = Zo , R1 = 83Ω R2 =125Ω VCC R1 ZO CIN R2 VCCR2 + VEER1 R1+R2 = VBIAS VEE VCC R1 ZO CIN R2 VEE VEE = 0V CIN TYP = 100nF for AC operation Reference Clock Inputs The incoming low-speed reference clock inputs are received by differential LVPECL inputs REFCLK± . Off-chip termination of these inputs is required (see Figure 14). In most situations these inputs will have high transition density and little DC offset. However, in cases where this does not hold, direct DC connection is possible. All serial clock inputs have the same circuit topology, as shown in Figure 14. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about the input common-mode voltage VCM and not exceed the maximum allowable amplitude. For single-ended, DC-coupling operations, it is recommended that the user provides an external reference voltage. The external reference should have a nominal value equivalent to the common-mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate. Page 10 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Figure 15: Termination of Low-Speed LVPECL TXIN[15:0] Inputs Chip Boundary VCC = 3.3V R1||R2 = Zo , R1 = 83Ω R2 =125Ω VCC R1 ZO CIN R2 VCCR2 + VEER1 R1+R2 = VBIAS VEE VREFIN VEE = 0V VREFOUT CIN TYP = 100nF for AC operation Low-Speed Inputs The incoming low-speed inputs are received by single-ended LVPECL inputs TXIN[15:0]. A reference voltage is necessary to provide for optimal switching of the inputs. The user can either provide an input voltage reference from the upstream device (VREFIN), or can use the reference voltage provided from the VSC8140 (VREFOUT). Side-by-side placement of the VREFIN and VREFOUT pins facilitates easy implementation. For DC or AC operation, the external reference should have a nominal value equivalent to the commonmode switch point of an LVPECL DC-coupled signal, and adhere to the DC characteristics as specified by the Table 3 DC characteristics (VCM). G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Figure 16: High-Speed Clock and High-Speed Data Inputs Data Sheet VSC8140 Chip Boundary VCC = 3.3V 1.65V 3kΩ 3kΩ 1.65V ZO CIN 50Ω CAC VTERM CIN ZO 3kΩ 3kΩ 50Ω VEE = 0V CIN TYP = 100nF CAC TYP = 100nF High-Speed Clock and High-Speed Data Inputs The incoming high-speed data and high-speed clock are received by high-speed inputs RXIN and RXCLKIN. The inputs are internally biased to accommodate AC-coupling. The data input receiver is internally terminated by a center-tapped resistor network. For differential input DC-coupling, the network is terminated to the appropriate termination voltage VTERM providing a 50Ω to VTERM termination for both true and complement inputs. For differential input AC-coupling, the network is terminated to VTERM via a blocking capacitor. In most situations, these inputs will have high transition density and little DC offset. However, in cases where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit topology, as shown in Figure 16. The reference voltage is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DCcoupling operations, it is recommended that the user provides an external reference voltage which has better temperature and power supply noise rejection than the on-chip resistor divider. The external reference should have a nominal value equivalent to the common-mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate. Page 12 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Supplies The VSC8140 is specified as a PECL device with a single positive 3.3V supply. Should the user desire to use the device in an ECL environment with a negative 3.3V supply, then VCC will be ground and VEE will be 3.3V. If used with VEE tied to -3.3V, the TTL control signals are still referenced to VEE. Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is recommended that the VCC power supply be decoupled using a 0.1µF and 0.01µF capacitor placed in parallel on each VCC power supply pin as close to the package as possible. If room permits, a 0.001µF capacitor should also be placed in parallel with the 0.1µF and 0.01µF capacitors mentioned above. Recommended capacitors are low-inductance ceramic SMT X7R devices. For the 0.1µF capacitor, a 0603 package should be used. The 0.01µF and 0.001µF capacitors can be either 0603 or 0403 packages. Extra care needs to be taken when decoupling the analog power supply pins (labeled VCCANA). In order to maintain the optimal jitter and loop bandwidth characteristics of the PLL contained in the VSC8140, the analog power supply pins should be filtered from the main power supply with a 10 µH C-L-C pi filter. If preferred, a ferrite bead may be used to provide the isolation. The 0.1µF and 0.01µF decoupling capacitors are still required and must be connected to the supply pins between the device and the C-L-C pi filter (or ferrite bead). For low frequency decoupling, 47µF tantalum low-inductance SMT caps are sprinkled over the board’s main +3.3V power supply and placed close to the C-L-C pi filter. If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling VCC must be changed to VEE, and all references to decoupling 3.3V must be changed to -3.3V. Figure 17: PLL Power Supply Decoupling Scheme VEE 0.1µF 10µH 0.1µF VEEANA 0.01µF VCC VCCANA VCCANA Note: VCC can be tied to VCCANA G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Data Sheet VSC8140 AC Characteristics Figure 18: Transmitter Parallel Data Timing Waveforms TXCLK16I+ Parallel Data Clock Input tTXDSU TXIN[0:15]+, TXPRTYIN Parallel Data Inputs tTXDH Valid Data 2 Valid Data 1 TXCLK16O+ Parallel Data Clock Output = don’t care Figure 19: Transmitter Serial Data and Clock Phase Timing tDH TXOUT+ Differential Serial Data Output D15 MSB D14 D13 D1 D0 LSB Time tPD TXCLKO+ Differential Clock Output NOTE: Bit 15 (MSB) is transmitted first, Bit 0 (LSB) is transmitted last. Figure 20: Transmitter Parity Timing tD TXCLK16I+ Parallel Data Clock Input tDV PARERR+ Data Valid Output tD Page 14 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 b a b Single Ended Swing 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Figure 21: Differential and Single-Ended Input / Output Voltage Measurement =α Swing = α a * Differential swing (α) is specified as | b - a | ( or | a - b | ), as is the single-ended swing. Differential swing is specified as equal in magnitude to single-ended swing. Differential Table 1: Transmitter AC Characteristics Parameters TD TTXDSU TTXDH TTXDOR, TTXDOF TXCLKD tTXCLK16R, tTXCLK16F TXCLK16OD TXCLK16ID RCKD TDV tDH tPD Description TXCLK16I/TXCLK16O period Data setup time to the rising edge of TXCLK16I+ Data hold time after the rising edge of TXCLK16I+ TXOUT± rise and fall time Transmit clock duty cycle TXCLK16O± rise and fall times TXCLK16O± duty cycle TXCLK16I± duty cycle Reference clock duty cycle Parallel data to DINVALID TXCLKO period Center of output data eye from falling edge of TXCLKO Min — 0.75 1.0 — 40 — 46 35 40 — — -75 Typ 6.4 — — — — — — — — 3 tD + 0.3 401.9 — Max — — — 120 60 250 53 65 60 — — +75 Units ns ns ns ps % ps % % % ns ps ps — — — Conditions 20% to 80% into 100Ω load. See Figure 13. — See Figure 24 — Assuming 10% distortion of TXCLK16O. — — — See Figure 19 Clock Multiplier Performance TDJ Output data jitter — — 4 ps RMS, tested to SONET specification (12kHz to 20MHz) with 2ps RMS jitter on REFCLK. RMS, tested to SONET specification (12kHz to 20MHz) with 2ps RMS jitter on REFCLK. Exceeds SONET/SDH mask TCJ Jittertol Output clock jitter Jitter tolerance Tuning Range — — -100 — — 4 — +100 ps — ppm G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Figure 22: Receiver AC Timing Waveforms RXCLK16O+ Parallel Data Clock Output tRXDSU RXOUT[0:15]+ Parallel Data Outputs Valid Data 1 tRXPD32 RXCLK32O+ Parallel Data Clock Output = don’t care tRXPDD Valid Data 2 Data Sheet VSC8140 Figure 23: Receiver Setup and Hold Time Requirements tRXDSU RXIN+ Differential Serial Data Input D14 tRXDH D13 D1 D0 LSB Time RXCLKIN+ Differential Clock Input D15 MSB NOTE: Bit 15 (MSB) is received first, Bit 0 (LSB) is received last. Table 2: Receiver AC Characteristics Parameters tRXPDD tRXPD32 tRXDR, tRXDF tRXCLKR, tRXCLKF RXCLK16OD tRXDSU Description Data valid from falling edge of RXCLK16O+ RXCLK32O transition from falling edge of RXCLK16O+ RXOUT[15:0]+/- rise and fall times RXCLK16O+/- rise and fall times RXCLK16O+/- duty cycle distortion RXIN+ setup time with respect to falling edge of RXCLKIN+ Min 0 0 — — 45 100 Typ Max 800 1.0 300 250 55 — Units ps ns ps ps % of clock cycle ps — — Conditions 20% to 80% into DC termination. See Figure 24. 20% to 80% into 100Ω load. See Figure 24. High-speed clock input at 2.48832GHz. — tRXDH RXCLKIND RXIN+ hold time with respect to falling edge of RXCLKIN+ RXCLKIN+/- duty cycle distortion 75 — ps % of clock cycle — 40 60 — Page 16 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 DC Characteristics 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Table 3: DC Characteristics (Over recommended operating conditions) Parameters VOHHSO VOLHSO Description Output HIGH voltage (TXOUT, TXCLKOUT) Output LOW voltage (TXOUT, TXCLKOUT) Output differential voltage (TXCLKOUT) Output differential voltage (TXOUT) Output common-mode voltage Back termination impedance Serial input differential voltage (RXIN, RXCLKIN) Output HIGH voltage (LVPECL) Output LOW voltage (LVPECL) Low-speed output voltage singleended, peak-to-peak swing (LVPECL) Input HIGH voltage (LVPECL) Input LOW voltage(LVPECL) Input HIGH current (LVPECL) Input LOW current (LVPECL) Input Resistance (LVPECL) Input differential voltage (LVPECL) Input common-mode voltage (LVPECL) Output HIGH voltage (TTL) Output LOW voltage (TTL) Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH Current (TTL) Input LOW current (TTL) Supply voltage Power dissipation Supply current Min VCC-0.40 VCC-1.20 450 500 VCC-1.20 40 200 VCC-1.020 VCC-2.000 600 VCC-1.100 VCC-2.0 — -50 10k 200 VCC-1.5 2.4 — 2.0 0.0 — — 3.14 — — Typ — — 600 600 — — — — — — — — — — — — — — — — — — — — 2.25 — Max VCC VCC-0.50 1000 Units V V Conditions 50Ω termination to VCC 50Ω termination to VCC 100Ω termination between ± output at load. See Figure 13. 100Ω termination between ± output at load. See Figure 13. Guaranteed, but not tested AC-coupled, internally biased to (VCC+VEE)/2. See Figure 24 See Figure 24 See Figure 24 — — VIN=VIH (max) VIN=VIL(min) — — — IOH = -1.0mA IOL = +1.0mA — — VIN = 2.4V VIN = 0.5V 3.3V± 5% Outputs open Outputs open ∆VODHSO mV 1000 VCC-0.300 60 — VCC-0.700 VCC-1.620 1300 VCC-0.700 VCC-1.540 200 — — — VCC-0.5 — 0.5 5.5 0.8 500 -500 3.47 2.75 800 V Ω mV V V mV V V µA µA Ω mV V V V V V µA µA V W mA VCMHSO RHSO ∆VIHS VOHL VOL ∆VO VIH VIL IIH IIL Ri ∆VI VCM VOH VOL VIH VIL IIH IIL VCC PD ICC G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 17 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Figure 24: Parametric Measurement Information Data Sheet VSC8140 PECL Rise and Fall Time 80% 20% Parametric Test Load Circuit Serial Output Load Z0 = 50Ω 50Ω VCC-2V Tr Tf Absolute Maximum Ratings (1) Power Supply Voltage (VCC)...........................................................................................................-0.5V to +3.8V DC Input Voltage (differential inputs).....................................................................................-0.5V to VCC +0.5V DC Input Voltage (TTL inputs) .......................................................................................................-0.5V to +5.5V DC Output Voltage (TTL outputs) .........................................................................................-0.5V to VCC + 0.5V Output Current (TTL outputs) .................................................................................................................. +/-50mA Output Current (differential outputs).........................................................................................................+/-50mA Case Temperature Under Bias ...................................................................................................... -55oC to +125oC Recommended Operating Conditions Power Supply Voltage (VCC)..................................................................................................................+3.3V+5% Operating Temperature Range ...........................................................0oC Ambient to +110oC Case Temperature NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. ESD Ratings Proper ESD procedures should be used when handling this product. The VSC8140 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V. Page 18 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 Package Pin Descriptions Table 4: Package Pin Identification - 128 PQFP Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Name OVERFLOW VEET VCCT VEE HSDREF VEE RXIN+ RXINVCC VEE VEE VCC RXCLKINHSCLKREF RXCLKIN+ VCC NC VCC VCC TXOUT+ TXOUTVCC VEE VEE VEE VCC VCC TXCLKOUT+ TXCLKOUTVCC VEEP_CLK VEEP_CLK VEE_PWRDN VCC VCC VCC I/O O — — — I — I I — — — — I I I — — — — O O — — — — — — O O — — — I — — — Level TTL GND typ. +3.3V typ. GND typ. 0V->3.3V GND typ. HS HS 3.3V typ. GND typ. GND typ. 3.3V typ. HS 0V->3.3V HS 3.3V typ. — 3.3V typ. 3.3V typ. HS HS 3.3V typ. GND typ. GND typ. GND typ. 3.3V typ. 3.3V typ. HS HS 3.3V typ. GND typ. GND typ. GND typ. 3.3V typ. 3.3V typ. 3.3V typ. FIFO overflow indication TTL VEE power supply TTL VCC power supply Negative power supply Description High-speed data input termination voltage reference Negative power supply High-speed data input, true High-speed data input, complement Positive power supply Negative power supply Negative power supply Positive power supply High-speed clock input, complement High-speed clock input termination voltage reference High-speed clock Input, true Positive power supply No connect, leave unconnected(1) Positive power supply Positive power supply High-speed data output, true High-speed data output, complement Positive power supply Negative power supply Negative power supply Negative power supply Positive power supply Positive power supply High-speed clock output, true High-speed clock output, complement Positive power supply HS clock VEE power supply (tie to VCC for power down) HS clock VEE power supply (tie to VCC for power down) HS clock VEE power supply (tie to VCC for power down) Positive power supply Positive power supply Positive power supply G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 19 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Table 4: Package Pin Identification - 128 PQFP Pin # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Data Sheet VSC8140 Name VEE FACLOOP LOOPTIM0 PARMODE FIFORESET LOOPTIM1 REF_FREQSEL LPTIMCLK+ LPTIMCLKVCC_ANA VEE_ANA REFCLK+ REFCLKVEE FILTAO FILTAON FILTAI FILTAIN VCC TXCLK16O+ TXCLK16OVEE TXCLK16ITXCLK16I+ VCC TXPARITYIN TXIN15 TXIN14 VEE VCC TXIN13 TXIN12 TXIN11 TXIN10 TXIN9 I/O — I I I I I I I I — — I I — — — — — — O O — I I — I I I — — I I I I I Level GND typ. TTL TTL TTL TTL TTL TTL LVPECL LVPECL +3.3V typ. GND typ. LVPECL LVPECL GND typ. — — — — 3.3V typ. LVPECL LVPECL GND typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL LVPECL GND typ. 3.3V typ. LVPECL LVPECL LVPECL LVPECL LVPECL Negative power supply Description Facility loopback, active high Enable internal looptiming operation, active high Parity mode select Reset to align FIFO write and read pointers Enable external loop timing operation, active high Reference clock input select External loop timing clock, true External loop timing clock, complement Positive power supplys for analog parts of CMU Negative power supplys for analog parts of CMU Reference clock input, true Reference clock input, complement Negative power supply Loop filter pin - connect via capacitor to FILTAI (pin 53) Loop filter pin - connect via capacitor to FILTAIN (pin 54) Loop filter pin - connect via capacitor to FILTAO (pin 51) Loop filter pin - connect via capacitor to FILTAON (pin 52) Positive power supply Low-speed clock output, true. A divide-by-16 version of the PLL clock. Low-speed clock output, complement. A divide-by-16 version of the PLL clock. Negative power supply Low-speed clock input for latching low-speed data, complement Low-speed clock input for latching low-speed data, true Positive power supply Transmitter parity bit input Low-speed single-ended data (MSB)(2) Low-speed single-ended data Negative power supply Positive power supply Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Page 20 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 Table 4: Package Pin Identification - 128 PQFP Pin # 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Name VEE TXIN8 TXIN7 TXIN6 TXIN5 TXIN4 VCC TXIN3 TXIN2 VEE TXIN1 TXIN0 VCC VREFIN VREFOUT VCC RXOUT0 RXOUT1 VEE RXOUT2 RXOUT3 VCC RXOUT4 RXOUT5 VCC RXOUT6 RXOUT7 VEE RXOUT8 RXOUT9 VCC VCC RXOUT10 RXOUT11 RXOUT12 VCC RXOUT13 I/O — I I I I I — I I — I I — I O — O O — O O — O O — O O — O O — — O O O — O Level GND typ. LVPECL LVPECL LVPECL LVPECL LVPECL 3.3V typ. LVPECL LVPECL GND typ. LVPECL LVPECL 3.3V typ. Voltage Voltage 3.3V typ. LVPECL LVPECL GND typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL GND typ. LVPECL LVPECL 3.3V typ. 3.3V typ. LVPECL LVPECL LVPECL 3.3V typ. LVPECL Negative power supply Description Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Positive power supply Low-speed single-ended data Low-speed single-ended data Negative power supply Low-speed single-ended data Low-speed single-ended data (LSB)(2) Positive power supply Voltage reference for single-ended TXIN VCM or VREFOUT Voltage reference for single-ended RXOUT (VOH+VOL)/2. Positive power supply Low-speed single-ended data (LSB)(2) Low-speed single-ended data Negative power supply Low-speed single-ended data Low-speed single-ended data Positive power supply Low-speed single-ended data Low-speed single-ended data Positive power supply Low-speed single-ended data Low-speed single-ended data Negative power supply Low-speed single-ended data Low-speed single-ended data Positive power supply Positive power supply Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Positive power supply Low-speed single-ended data G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 21 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Table 4: Package Pin Identification - 128 PQFP Pin # 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Data Sheet VSC8140 Name RXOUT14 VEE RXOUT15 RXPARITYOUT VCC RXCLK16ORXCLK16O+ VEE VCC RXCLK16_32ORXCLK16_32O+ CLK128OCLK128O+ VCC RXCLKO_FREQSEL LOS POL EQULOOP VCC PARERR I/O O — O O — O O — — O O O O — I I I I — O Level LVPECL GND typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL GND typ. 3.3V typ. LVPECL LVPECL LVPECL LVPECL 3.3V typ. TTL TTL TTL TTL 3.3V typ. TTL Negative power supply Description Low-speed single-ended data Low-speed single-ended data (MSB) (2) Receiver parity bit output Positive power supply Parallel clock output (155.52MHz), complement Parallel clock output (155.52MHz), true Negative power supply Positive power supply Divide-by-16 or -32 clock output, complement Divide-by-16 or -32 clock output, true Divide-by-128 clock output, complement Divide-by-128 clock output, true Positive power supply RXCLKO16_32 frequency select Loss of Signal control Polarity Signal Control Equipment loopback, active high Positive power supply Parity error output NOTES: (1) No connect (NC) pin must be left unconnected. Connecting this pin to either the positive or negative power supply rails may cause improper operation or failure of the device; or in extreme cases, cause permanent damage to the device. (2) There has been a change in the naming of the pins of the Low-Speed Parallel Receive and Transmit pins of the VSC8140. RXOUT0; pin 88 (MSB) has been changed to RXOUT15; pin 111 (MSB) and TXIN15; pin 63 (LSB) has been changed to TXIN0; pin 83 (LSB). Page 22 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 Package Information 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator 128 PQFP Package Drawings PIN 128 PIN 1 PIN 102 Key RAD. 2.92 ± .50 (2) mm 2.35 0.25 2.00 17.20 14.00 23.20 20.00 .88 .50 .22 0°-7° .30 .20 Tolerance MAX MAX +.10 ±.20 ±.10 ±.20 ±.10 +.15/-.10 BASIC ±.05 TYP TYP A A1 A2 E1 E D D1 E E1 L e b EXPOSED INTRUSION 0.127 MAX. EXPOSED HEATSINK 2.54 ± .50 PIN 38 D1 D TOP VIEW 10° TYP. PIN 64 q R R1 A2 A A1 10° TYP. e R R1 θ1 STANDOFF A Notes: 1) 2) 3) Drawing is not to scale All dimensions in mm Package represented is also used for the 64, 80, & 100 PQFP packages. Pin count drawn does not reflect the 128 Package. .25 A1 θ 0.17 MAX. b LEAD COPLANARITY NOTES: Package #: 101-322-5 Issue #: 2 L G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 23 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Data Sheet VSC8140 Package Pin Descriptions Table 5: Package Pin Identification - 208 BGA Pin # B17 B16 B15 C14 D13 A16 B14 B13 A14 A13 D11 C11 B11 D10 B10 A10 B9 D9 A9 A8 C8 D8 A7 A6 D7 A5 A4 A3 B4 D5 A2 A1 C4 Name OVERFLOW VEET VCCT VEE HSDREF VEE RXIN+ RXINVCC VEE VEE VCC RXCLKINHSCLKREF RXCLKIN+ VCC VCC VCC TXOUT+ TXOUTVCC VEE VEE VEE VCC VCC TXCLKOUT+ TXCLKOUTVCC VEEP_CLK VEEP_CLK VEE_PWRDN VCC I/O O — — — I — I I — — — — I I I — — — O O — — — — — — O O — — — I — Level TTL GND typ. Description FIFO overflow indication TTL VEE power supply Negative power supply High-speed data input termination voltage reference Negative power supply High-speed data input, true High-speed data input, complement Positive power supply Negative power supply Negative power supply Positive power supply High-speed clock input, complement High-speed clock input termination voltage reference High-speed clock input, true Positive power supply Positive power supply Positive power supply High-speed data output, true High-speed data output, complement Positive power supply Negative power supply Negative power supply Negative power supply Positive power supply Positive power supply High-speed clock output, true High-speed clock output, complement Positive power supply HS clock VEE power supply (tie to VCC for power down) HS clock VEE power supply (tie to VCC for power down) HS clock VEE power supply (tie to VCC for power down) +3.3V typ. TTL VCC power supply GND typ. 0V->3.3V GND typ. HS HS 3.3V typ. GND typ. GND typ. 3.3V typ. HS 0V->3.3V HS 3.3V typ. 3.3V typ. 3.3V typ. HS HS 3.3V typ. GND typ. GND typ. GND typ. 3.3V typ. 3.3V typ. HS HS 3.3V typ. GND typ. GND typ. GND typ. 3.3V typ. Positive power supply Page 24 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 Table 5: Package Pin Identification - 208 BGA Pin # B3 D4 C3 C1 F4 F3 D1 E1 G4 G3 F2 G2 F1 H3 H2 G1 H1 J2 J4 J3 K1 K2 K3 K4 L1 M1 L2 L3 L4 M2 M3 M4 P1 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Name VCC VCC VEE FACLOOP LOOPTIM0 PARMODE FIFORESET LOOPTIM1 REF_FREQSEL VEE LPTIMCLK+ LPTIMCLKVCC_ANA VEE_ANA REFCLK+ REFCLKVEE VCC FILTAO FILTAON FILTAI FILTAIN VCC TXCLK16O+ TXCLK16OVEE TXCLK16ITXCLK16I+ VCC TXPARITYIN TXIN15 TXIN14 VEE I/O — — — I I I I I I — I I — — I I — — — — — — — O O — I I — I I I — Level 3.3V typ. 3.3V typ. GND typ. TTL TTL TTL TTL TTL TTL GND typ. LVPECL LVPECL GND typ. LVPECL LVPECL GND typ. 3.3V typ. — — — — 3.3V typ. LVPECL LVPECL GND typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL LVPECL GND typ. Positive power supply Positive power supply Negative power supply Description Facility loopback, active high Enable internal looptiming operation, active high Parity mode select Reset to align FIFO write and read pointers Enable external loop timing operation, active high Reference clock input select Negative power supply External loop timing clock, true External loop timing clock, complement Negative power supplies for analog parts of CMU Reference clock input, true Reference clock input,complement Negative power supply Positive power supply Loop filter pin - connect via capacitor to FILTAI (pin 53) Loop filter pin - connect via capacitor to FILTAIN (pin 54) Loop filter pin - connect via capacitor to FILTAO (pin 51) Loop filter pin - connect via capacitor to FILTAON (pin 52) Positive power supply Low-speed clock output, true. A divide-by-16 version of the PLL clock. Low-speed clock output, complement. A divide-by-16 version of the PLL clock. Negative power supply Low-speed clock input for latching low-speed data, complement Low-speed clock input for latching low-speed data, true Positive power supply Transmitter parity bit input Low-speed single-ended data (MSB)(1) Low-speed single-ended data Negative power supply +3.3V typ. Positive power supplies for analog parts of CMU G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 25 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Table 5: Package Pin Identification - 208 BGA Pin # T3 P5 R5 T4 P6 T5 R6 U5 R7 T6 U6 P8 R8 T8 U7 U8 T9 P9 R9 U9 U10 T10 R10 P10 U11 U12 T11 R11 P11 U13 T12 T13 R12 P12 Data Sheet VSC8140 Name VCC TXIN13 TXIN12 TXIN11 TXIN10 TXIN9 VEE TXIN8 TXIN7 TXIN6 TXIN5 TXIN4 VCC TXIN3 TXIN2 VEE TXIN1 TXIN0 VCC VREFIN VREFOUT VCC RXOUT0 RXOUT1 VEE RXOUT2 RXOUT3 VCC RXOUT4 RXOUT5 VCC RXOUT6 RXOUT7 VEE I/O — I I I I I — I I I I I — I I — I I — I O — O O — O O — O O — O O — Level 3.3V typ. LVPECL LVPECL LVPECL LVPECL LVPECL GND typ. LVPECL LVPECL LVPECL LVPECL LVPECL 3.3V typ. LVPECL LVPECL GND typ. LVPECL LVPECL 3.3V typ. Voltage Voltage 3.3V typ. LVPECL LVPECL GND typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL GND typ. Positive power supply Description Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Negative power supply Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Positive power supply Low-speed single-ended data Low-speed single-ended data Negative power supply Low-speed single-ended data Low-speed single-ended data (LSB)(1) Positive power supply Voltage reference for single-ended TXIN VCM or VREFOUT Voltage reference for single-ended RXOUT (VOH+VOL)/2 Positive power supply Low-speed single-ended data (LSB)(1) Low-speed single-ended data Negative power supply Low-speed single-ended data Low-speed single-ended data Positive power supply Low-speed single-ended data Low-speed single-ended data Positive power supply Low-speed single-ended data Low-speed single-ended data Negative power supply Page 26 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 Table 5: Package Pin Identification - 208 BGA Pin # U14 U15 R13 N16 P17 L14 L15 M16 L16 M17 K14 K15 K16 L17 J17 H17 H16 H15 H14 G17 F17 G16 G15 G14 D17 C17 E15 D16 E14 A17 A15 A12 A11 B12 B8 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Name RXOUT8 RXOUT9 VCC VCC RXOUT10 RXOUT11 RXOUT12 VCC RXOUT13 RXOUT14 VEE RXOUT15 RXPARITYOUT VCC RXCLK16ORXCLK16O+ VEE VCC RXCLK16_32ORXCLK16_32O+ CLK128OCLK128O+ VCC RXCLKO_FREQSEL LOS POL EQULOOP VCC PARERR NC NC NC NC NC NC I/O O O — — O O O — O O — O O — O O — — O O O O — I I I I — O — — — — — — Level LVPECL LVPECL 3.3V typ. 3.3V typ. LVPECL LVPECL LVPECL 3.3V typ. LVPECL LVPECL GND typ. LVPECL LVPECL 3.3V typ. LVPECL LVPECL GND typ. 3.3V typ. LVPECL LVPECL LVPECL LVPECL 3.3V typ. TTL TTL TTL TTL 3.3V typ. TTL — — — — — — Description Low-speed single-ended data Low-speed single-ended data Positive power supply Positive power supply Low-speed single-ended data Low-speed single-ended data Low-speed single-ended data Positive power supply Low-speed single-ended data Low-speed single-ended data Negative power supply Low-speed single-ended data (MSB)(1) Receiver Parity bit output Positive power supply Parallel clock output (155.52MHz), complement Parallel clock output (155.52MHz), true Negative power supply Positive power supply Divide-by-16 or -32 clock output, complement Divide-by-16 or -32 clock output, true Divide-by-128 clock output, complement Divide-by-128 clock output, true Positive power supply RXCLKO16_32 frequency select Loss of Signal control Polarity Signal Control Equipment loopback, active high Positive power supply Parity error output No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 27 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Table 5: Package Pin Identification - 208 BGA Pin # B7 B6 B5 B2 B1 C16 C15 C13 C12 C10 C9 C7 C6 C5 C2 D15 D14 D12 D6 D3 D2 E17 E16 E4 E3 E2 F16 F15 F14 H4 J16 J15 J14 J1 K17 Data Sheet VSC8140 Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC I/O — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Level — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Description No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) Page 28 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 Table 5: Package Pin Identification - 208 BGA Pin # M15 M14 N17 N15 N14 N4 N3 N2 N1 P16 P15 P14 P13 P7 P4 P3 P2 R17 R16 R15 R14 R4 R3 R2 R1 T17 T16 T15 T14 T7 T2 T1 U17 U16 U4 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC I/O — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Level — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Description No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 29 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Table 5: Package Pin Identification - 208 BGA Pin # U3 U2 U1 Data Sheet VSC8140 Name NC NC NC I/O — — — Level — — — Description No connect, leave unconnected(2) No connect, leave unconnected(2) No connect, leave unconnected(2) NOTES: (1) There has been a change in the naming of the pins of the Low-Speed Parallel Receive and Transmit pins of the VSC8140. RXOUT0; pin R10 (MSB) has been changed to RXOUT15; pin K15 (MSB) and TXIN15; pin M3 (LSB) has been changed to TXIN0; pin P9 (LSB). (2) No connect (NC) pins must be left unconnected. Connecting any of these pins to either the positive or negative power supply rails may cause improper operation or failure of the device; or in extreme cases, cause permanent damage to the device. Page 30 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 Package Information 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator 208 TBGA Package Drawings 0.10 D -Ae -B- 10 17 15 16 14 13 11 9 12 10 8 7 6 5 4 3 2 1 11 CORNER A B C D E G H J K M P T U F E1 L N E R e DETAIL B 45 DEGREE 0.5MM CHAMFER (4 PLCS) D1 TOP VIEW BOTTOM VIEW DETAIL A b 0.30 S C A S B S 0.10 S C 4 SIDE VIEW DETAIL B A1 c A ccc -C- c P DETAIL A 6 5 aaa C NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. "e" REPRESENTS THE BASIC SOLDER BALL GRID PITCH. 3. "M" REPRESENTS THE BASIC SOLDER BALL MATRIX SIZE, AND SYMBOL "N" IS THE MAXIMUM ALLOWABLE NUMBER OF BALLS AFTER DEPOPULATING. 4. "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM -C- . 5. DIMENSION "aaa" IS MEASURED PARALLEL TO PRIMARY DATUM -C- . 6. PRIMARY DATUM -C- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 7. PACKAGE SURFACE SHALL BE BLACK OXIDE. 8. CAVITY DEPTH VARIOUS WITH DIE THICKNESS 9. SUBSTRATE MATERIAL BASE IS COPPER. 10. BILATERIAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF PACKAGE BODY 11. 45 DEG. 0.5 MM CHAMFER CORNER AND WHITE DOT FOR PIN1 IDENTIFICATION DIMENSIONAL REFERENCES NOM. MAX. REF. MIN. 1.45 1.55 A 1.65 0.70 A1 0.65 0.60 23.00 22.80 D 23.20 20.32 (BSC.) D1 22.80 23.00 23.20 E 20.32 (BSC.) E1 0.65 0.85 0.75 b c 0.95 0.90 0.85 17 M 208 N aaa 0.25 ccc 0.25 e 1.27 TYP. P 0.15 G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 31 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Data Sheet VSC8140 Package Thermal Considerations This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance is shown in the following table: Table 6: Thermal Resistance Symbol θjc θca Description Thermal resistance from junction to case. Thermal resistance from case to ambient with no airflow, including conduction through the leads. °C/W - (BGA) 2.2 18.5 °C/W (PQFP) 1.34 25.0 Thermal Resistance with Airflow Shown in the table below is the thermal resistance with airflow. This thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. The temperature difference between the ambient airflow temperature and the case temperature should be the worst case power of the device multiplied by the thermal resistance. Table 7: Thermal Resistance with Airflow Airflow 100 lfpm 200 lfpm 400 lfpm θca (oC/W) (BGA) 18 17 16 θca (oC/W) (PQFP) 21 18 16 Maximum Ambient Temperature without Heatsink The worst case ambient temperature without use of a heatsink is given by the equation: T A ( MAX ) = T C ( MAX ) – P ( MAX ) θ CA where: θCA Theta case to ambient at appropriate airflow ΤA(MAX) Ambient Air temperature ΤC(MAX) Case temperature (110oC for VSC8140) P(MAX) Power (2.75 W for VSC8140) Page 32 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator The results of this calculation are listed below: Table 8: Maximum Ambient Air Temperature without Heatsink Airflow None 100 lfpm 200 lfpm 400 lfpm o C (TBGA) 59 60 63 66 o C (PQFP) 41 52 60 66 Note that ambient air temperature varies throughout the system based on the positioning and magnitude of heat sources and the direction of air flow. Surface Mount Solderability The make-up of each lead on the PQFP and TBGA package is 85% Tin and 15% Lead. The solderability requirements for the various methods is described below. Reflow Soldering This is the suitable method of soldering for these components. When using reflow soldering to mount the IC package, solder paste (a suspension of fine solder particles, flux, and binding agent) is required to be applied to the printed-circuit board by screen printing, stenciling, or pressure-syringe dispensing before package placement. Throughput times (this includes preheating, soldering, and cooling) are shown in Table 9. Table 9: Reflow Running Profile Condition Average ramp up (from Preheat Temperature 183oC to peak temperature) Average ramp down (from peak to 183oC) (125oC) oC TBGA 1.553oC/sec -1.152oC/sec 77 sec 80 sec 19 sec 220-225oC 224 oC PQFP 1.5432oC/sec -1.085oC/sec 79 sec 80 sec 19 sec 220-225oC 224oC 228 sec Temperature maintained above 183 Peak Temperature Range Peak Temperature Time 25oC to Peak Temperature Time within 5oC of actual peak temperature 233 sec Wave Soldering Conventional single wave soldering is not recommended for surface mount devices or printed circuit boards with high component density, as solder bridging and non-wetting can present problems. Double-wave soldering can be used, only if the method comprises a turbulent wave with high upward pressure followed by a smooth laminar wave and the footprint must incorporate solder thieves at the downstream end. The package must be fixed with a droplet of adhesive during placement before soldering. After the adhesive is cured, the package can be soldered. G52251-0, Rev. 4.0 9/6/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 33 VITESSE SEMICONDUCTOR CORPORATION 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Data Sheet VSC8140 Manual Soldering When manually soldering the device to the printed circuit board, contact time should be limited to 10 seconds at up to 240oC. Layout Considerations Refer to Application Note, AN56 “High-Speed Design Guidelines.” Ordering Information The order number for this product is formed by a combination of the device type and package type. VSC8140 Device Type xx 2.48832Gb/s Multi-Rate SONET/SDH Transceiver Package QR: 28-Pin PQFP, 14x20mm TW: 208-Pin BGA, 23x23mm Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products, specifications or other information at any time without prior notice. Therefore the reader is cautioned to confirm that this data sheet is current prior to placing any orders. The Company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation’s products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. Page 34 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52251-0, Rev. 4.0 9/6/00