VSC830QZ

VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 Features • Dual 2x2 Crosspoint Switch • 2.7Gb/s NRZ Data Bandwidth, 2.7GHz Signal Bandwidth • PECL/TTL-Compatible Control Inputs • PECL-Compatible High-Speed I/O 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch • 50Ω Source Terminated Output Driver and Programmable Input Terminations • Single 3.3V Supply, 1W Typical Dissipation • Power-Down Capability for Unused Outputs • Compact 44-Pin PQFP, 10x10mm Package General Description The VSC830 is a monolithic dual 2x2 asynchronous crosspoint switch, designed for critical signal path control and buffering applications, such as loop-back, protection switching, and multi-channel backplane driver/receivers. Signal path delay is tightly matched between each output channel to eliminate the need for delay path compensation when switching between signal sources. The crosspoint function is based on a multiplexer tree architecture. Each 2x2 switch can be considered as a pair of 2:1 multiplexers that share the same inputs. The signal path through each switch is fully differential and delay matched. The signal path is unregistered, so there are no restrictions on the phase, frequency, or signal pattern at each input. Unused outputs can be independently powered off, thereby eliminating power on unused sections (see Design Guide section in this data sheet). The switch control inputs can be configured to be compatible with PECL or TTL levels. The high-speed input and output levels are nominally PECL compatible and capable of interfacing with a wide range of termination schemes. VSC830 Symbol Diagram S1,S2 A1 A2 S1,S2 A1 A2 Y1 Y2 Y1 Y2 G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Data Sheet VSC830 Functional Block Diagram PEMODE S1A A1A+ A1ATERM_ENABLE_A SL VCC VCCP1A 0 Y1A Y1AN VEE1A VCCP2A 1 S2A SL A2A+ A2A- 0 Y2A Y2AN VEE2A 1 S1B A1B+ A1BSL VCCP1B 0 Y1B Y1BN VEE1B VCCP2B SL 1 TERM_ENABLE_B S2B 0 A2B+ A2B- Y2B Y2BN VEE2B 1 Page 2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52192-0, Rev 4.0 05/23/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 Functional Description 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Select As shown in Figure 1, each output can be treated as a 2:1 multiplexer, with the A1 and A2 inputs common to both multiplexers. The select input S1 independently controls the state of the multiplexer that drives output Y1, and select input S2 independently controls the output of Y2. Figure 1: Select Functional Block Diagram S1 S2 A1 A2 Y1 Y2 Table 1 specifies the function of the select inputs. Table 1: Select Function S1 0 1 0 1 S2 0 0 1 1 Y1 A1 A2 A1 A2 Y2 A1 A1 A2 A2 MODE The interface level of the select pins, S1 and S2, can be programmed to either TTL or PECL levels by shorting the MODE pin to either VCC or VEE. Note that the MODE pin must be tied to either VCC or VEE. The function of MODE is specified in Table 2. Table 2: MODE Function MODE VEE VCC S1, S2 TTL PECL G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Data Sheet VSC830 Power-Down Power to each output stage is provided through VCC, VCCP, and VEE. VCC is common to all outputs. To power off unused outputs, tie the respective VEE and VCCP pin to VCC, as shown in Figure 2. Figure 2: Power-Down Mode Example VCC VCCP1A VCCP2A VCCP1B VCCP2B VEE1A “ON” VEE2A “ON” VEE1B “OFF” VEE2B “OFF” Minimum power configuration requires output channel 1A active, so power must be applied to VCCP1A and VEE1A at all times. Programmable input termination Across each differential input (from the + input to the - input) of the VSC830 is a switched 100Ω termination resistor. Using the TERM_ENABLE pin, the termination can be optionally disabled. To enable the input termination, connect the respective TERM_ENABLE pin to VCC. To disable the internal termination, connect TERM_ENABLE to VEE. If unconnected, the TERM_ENABLE pin will self-bias to VEE and disable the internal termination. Independent termination controls are provided for the “A” and “B” switches. Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52192-0, Rev 4.0 05/23/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 AC Characteristics Table 3: AC Timing Symbol FRATE FBW TSKW TCON tR, tF tjP Signal path data rate Signal path bandwidth (-3dB) Channel to channel delay skew Switch configuration setup time(1) High-speed output rise/fall times, 20% to 80% Signal path added jitter, peak-peak(1) 23 (2) 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Parameter Min Typ Max 2.7 2.7 Units Gb/s GHz ps ns ps ps 50 1 150 40 NOTES: (1) Tested on a sample basis only, with 2 -1 PRBS data, input signal rise/fall time < 150ps. Value stated in table is added to measurement system jitter. (2) Input signal rise/fall time < 150ps, measured using an alternating 1, 0 pattern. DC Characteristics (All characteristics are over the specified operating conditions) Table 4: Power Supply Symbol ICC PD PT Parameter Total VCC(P) supply current Power dissipation per output (Y1A±, Y2A±, Y1B±, Y2B±) Total chip power (all outputs powered on) Min Typ Max 350 300 1.2 Units mA mW W Conditions NOTE: Specified with outputs terminated, 100Ω between true and complement, VCC = 3.45V. Table 5: Select Input Levels—TTL Mode Symbol VIH VIL IIH IIL Parameter Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Min 2.0 Typ Max 0.8 500 -500 Units V V µA µA Conditions VIN = 2.4V VIN = 0.5V Table 6: Select Input Levels—PECL Mode Symbol VIH VIL IIH IIL Parameter Input HIGH voltage (PECL) Input LOW voltage (PECL) Input HIGH current (PECL) Input LOW current (PECL) Min VCC1.0 Typ Max Units V Conditions VCC1.6 500 -500 V µA µA VIN = 2.5V VIN = 1.5V Table 7: Control Inputs Symbol RPEMODE Parameter PEMODE pin impedance Min Typ 3100 Max Units Ω Conditions G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 5 VITESSE SEMICONDUCTOR CORPORATION 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Table 8: “A” Input Levels (Differential PECL) Data Sheet VSC830 Min 200 VCC1.7 Symbol VID VICM Parameter Input differential voltage Input common-mode voltage Typ Max 1000 VCC0.9 Units mV V Conditions See Note 1 NOTE: (1) Peak-to-peak swing of each side of the differential input. Table 9: “Y” Output Levels (Differential PECL) Symbol VOD1 VOD2 VOCM Parameter Output differential voltage (Data) Output differential voltage (Clock) Output common-mode voltage Min 400 400 VCC1.6 Typ 700 550 Max 1000 850 VCC1.0 Units mV mV V Conditions See Note 1 See Note 2 NOTES: (1) Peak-peak swing of each side of the differential output. 223-1 PRBS data. (2) Peak-to-peak swing of each side of the differential output. Alternating 1, 0 pattern. Absolute Maximum Ratings Power Supply Voltage (VCC) Potential to GND ..............................................................................-0.5V to +4.0V TTL Input Voltage Applied ................................................................................................... -0.5V to VCC +0.5V ECL Input Voltage Applied .................................................................................................... -0.5V to VCC +0.5V Output Current (IOUT) .................................................................................................................................... 50mA Case Temperature Under Bias (TC) .............................................................................................-55oC to + 125oC Storage Temperature (TSTG)........................................................................................................-65oC to + 150oC NOTE: (1) Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Operating Conditions Supply voltage (VEE) .......................................................................................................................................... 0V Supply voltage (VCC) ............................................................................................................................ +3.3V ±5% Supply voltage (VCCP) .......................................................................................................................... +3.3V ±5% Operating Range(1) (T) ..................................................................................................................... 0oC to +85oC NOTE: (1) Lower limit of specification is ambient temperature and upper limit is case temperature. ESD Ratings Proper ESD procedures should be used when handling this product. The VSC830 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V. Page 6 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52192-0, Rev 4.0 05/23/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 Package Pin Descriptions Figure 3: Pin Diagram 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch TERM_ENABLE_A VCCP1A VEE1A 35 44 43 42 41 40 39 38 37 36 34 33 32 31 30 29 VCC S2A A2A+ A2AVCC PEMODE VCC A1B+ A1BS1B VCC VEE1A A1A+ Y1A+ A1A- S1A VCC Y1A- VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 VSC830 VEE2A VEE2A Y2A+ Y2AVCCP2A VCC VCCP1B Y1B+ Y1BVEE1B VEE1B 28 27 26 25 24 23 S2B A2B+ A2B- VEE2B TERM_ENABLE_B VCCP2B VEE2B Y2B- Y2B+ VCC VCC G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 7 VITESSE SEMICONDUCTOR CORPORATION 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Table 10: Pin Identification Data Sheet VSC830 Function Positive Supply Negative Supply Negative Supply Negative Supply Negative Supply Positive Supply Positive Supply Positive Supply Positive Supply Termination Enable Signal Name VCC VEE1A VEE2A VEE1B VEE2B VCCP1A VCCP2A VCCP1B VCCP2B TERM_ENABLE_A Pin(s) 1, 5, 7, 11, 12, 16, 28, 40, 44 34, 35 32, 33 23, 24 21, 22 38 29 27 18 39 Description Global supply for chip For channel output 1A. Must always be powered on. For output 2A. Connect to VCC to power-off. For output 1B. Connect to VCC to power-off. For output 2B. Connect to VCC to power-off. Output driver supply for channel 1A Output driver supply for channel 2A Output driver supply for channel 1B Output driver supply for channel 2B Input termination enable for the “A” switch. Normally low (VEE). Connect to VCC to enable internal 100 ohm termination between AxA+ inputs. Input termination enable for the “B” switch. Normally low (VEE). Connect to VCC to enable internal 100Ω termination between AxA+ inputs. PECL/TTL interface control Channel 1A differential signal input Channel 1A input selector Channel 1A differential output Channel 2A differential signal input Channel 2A input selector Channel 2A differential output Channel 1B differential signal input Channel 1B input selector Channel 1B differential output Channel 2B differential signal input Channel 2B input selector Channel 2B differential output TERM_ENABLE_B PEMODE A1A± S1A Y1A± A2A± S2A Y2A± A1B± S1B Y1B± A2B± S2B Y2B± 17 6 41, 42 43 37, 36 3, 4 2 31, 30 8, 9 10 26, 25 14, 15 13 20, 19 Termination Enable Control PECL Input PECL/TTL Input PECL Output PECL Input PECL/TTL Input PECL Output PECL Input PECL/TTL Input PECL Output PECL Input PECL/TTL Input PECL Output Page 8 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52192-0, Rev 4.0 05/23/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 Package Thermal Characteristics 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch The VSC830 is packaged into a standard plastic quad flatpack with an embedded, but unexposed thermal slug. This package adheres to industry-standard EIAJ footprints for a 10x10mm body, 44 lead PQFP. The package construction is as shown in Figure 4. The 44-pin PQFP with embedded slug has the thermal properties shown in Table 11. This package allows the VSC830 to operate with ambient temperatures up to 70oC in still air. Figure 4: Package Cross Reference Wire Bond Die Plastic Molding Compound Lead Insulator Copper Heat Spreader Table 11: 44-Pin PQFP Thermal Resistance Symbol θCA-0 θCA-100 θCA-200 θCA-400 θCA-600 Description Thermal resistance from case-to-ambient, still air Thermal resistance from case-to-ambient, 100 LFPM air Thermal resistance from case-to-ambient, 200 LFPM air Thermal resistance from case-to-ambient, 400 LFPM air Thermal resistance from case-to-ambient, 600 LFPM air Value (oC/W) 28.4 22.7 19.9 16.2 13.9 TA(MAX) (oC) 50.9 57.8 61.1 65.6 68.3 NOTE: TA(MAX) = max case temperature - (max power dissipation • θCA AIRFLOW). G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 9 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 Package Information 44-Pin PQFP, 10mm x 10mm Package Drawing 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch F G 44 34 Item A mm 2.45 2.00 0.35 13.20 10.00 13.20 10.00 0.88 0.80 0.80 3.56 Tol. MAX +.10 / -.05 ±.05 ±.25 ±.10 ±.25 ±.10 +.15 / -.10 +.15 / -.10 BASIC ±.50 DIA. 1 33 D E L F IH G H 11 23 I J 12 10 o TYP 22 J1 K D L 10 o TYP K 0.30 RAD.TYP. A 0.20 RAD. TYP . 0 o- 8 o 0.25 MAX. 0.17 MAX. 0.25 J1 J 0.102 MAX. LEAD COPLANARITY E NOTES: Drawing not to scale. Heat spreader up. All units in mm unless otherwise noted. Package #: 101-299-1 Issue #: 1 G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 10 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 Ordering Information 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch The order number for this product is formed by a combination of the device number, and package type. VSC830 Device Type 2.7Gb/s Asynchronous Dual 2x2 Crosspint Switch Package QZ: 44-Pin PQFP, 10 x 10mm Body XX Evaluation Boards An evaluation board for the VSC830 is available. Please contact your local sales representative. Notice Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 11 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 Design Guide 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Introduction The purpose of this document is to make it easier for system designers to use the VSC830 2.7Gb/s dual 2x2 crosspoint switch. This guide provides guidelines for I/O terminations, power supply decoupling and board layout. Signal Terminations The high-speed inputs (A1A+/-, A1B+/-, A2A+/- and A2B+/-) on the VSC830 are internally terminated with a programmable 100Ω termination between the true and complement input. The input termination can be disabled by connecting the TERM_ENABLE pin to VEE. High impedance internal biasing resistors provide the correct bias voltage at the inputs for AC-coupled applications (Figure 5). Figure 5: High-Speed Input Termination a) Termination Enabled Chip Boundary VCC = 3.3 V ZO CIN 2.0 V 2.0 V 100 ZO CIN VEE = GND R| | = 3.15kΩ (approx.) b) Termination Disabled Chip Boundary VCC = 3.3 V ZO RT = ZO VTT VTT CIN VEE = GND CIN 2.0 V 2.0 V R| | = 3.15 kΩ (approx.) CIN TYP = 0.1µF (capacitor value is selected for data input = 2.7Gb/s) VTT = VCC - 1.3V G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 12 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch The high-speed outputs (Y1A+/-, Y1B+/-, Y2A+/- and Y2B+/-) each consist of a differential pair designed to drive a 50Ω transmission line. The transmission line should be terminated with a 100Ω resistor at the receiver of the downstream device between the true and complement outputs. No connection to a termination voltage is required. The output driver is source terminated to 50Ω on-chip, providing a snubbing of any reflections. Output power can be cut by tying VEE to VCC. In single ended mode, the unused output must be terminated with 50Ω. Some output termination examples are shown in Figures 6 and 7. Figure 6: Examples of High-Speed Output I/O Termination for VSC830 a) AC Termination #1 VCC 50Ω VCC ZO = 50Ω 0.1 µF 50Ω 0.1 µF 50Ω VCC VCC 50Ω b) AC Termination #2 (Internal biasing required for Receiver) VCC 50Ω ZO = 50Ω 0.1 µF 100Ω 0.1 µF 50Ω VCC c) AC Termination #3 VCC 50Ω ZO = 50Ω 0.1 µF 50Ω 100 pF 50Ω 0.1 µF 50Ω VCC G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 13 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 a) Single-Ended AC Termination (Receiver internal biasing required) VCC 50Ω 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Figure 7: Examples of High-Speed Output I/O Termination for VSC830 ZO = 50Ω 0.1µF 100Ω 0.1µF 50Ω VCC b) DC Termination VCC 50Ω VCC ZO = 50Ω 50Ω 0.1µF 50Ω VCC 50Ω VCC 0.1µF Power Supply and Layout Considerations The VSC830 is a single supply part, requiring only a 3.3V supply. The location and hook-up of the bypass capacitors is critical to providing the VSC830 with a clean 3.3V power supply. VCC that are adjacent can share a 0.027µF capacitor connected to VEE. Normally the four channel specific VCC pins (VCCP1A, VCCP1B, VCCP2A, VCCP2B) are connected to one common VCC plane. In the same way the four channel specific VEE pins are connected to the common VEE plane. A suggested decoupling schematic for this configuration is shown in Figure 7a. However, a slightly higher signal integrity can be achieved if these pins are treated as different power supplies. In this case, VCCP1A should then be decoupled to VEE1A etc, as shown in Figure 7b. G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 14 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Figure 8: Decoupling Example: Common VCC and VEE Planes VEE VEE C1 C1 44 43 42 41 40 39 38 37 36 35 VCC VCC C1 VEE 1 2 3 C1 VEE 4 5 6 C1 VEE 7 8 9 C1 VEE 10 VCC VCC VCCP1A 34 VCCS2A 33 32 31 30 VSC830 Top View Heat Spreader Up VCCP2A VCC VCCP1B 29 28 27 26 25 24 C1 VEE 12 13 14 15 16 17 18 19 VCCP2B 11 VCC VCC VCC 23 20 21 C1 VEE C1 VEE 22 C1 = 0.027µF VCC = VEE = +3.3V (VEE typically ground) Recommended resistor and capacitor is size 805 G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 15 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Figure 9: Decoupling Example: Separate VCC and VEE Planes VEE C1 C1 VEE VEE1A C1 44 43 42 41 40 39 38 37 36 35 VCC VCC C1 VEE 1 2 3 C1 VEE 4 5 6 C1 VEE 7 8 9 C1 VEE 10 VCC VCC VCC VCCP1A 34 33 32 31 30 C1 C1 C1 VEE2A VEE VEE1B VSC830 Top View Heat Spreader Up VCCP2A VCC VCCP1B 29 28 27 26 25 24 12 13 14 15 16 17 18 19 VCCP2B 11 VCC VCC VCC 23 20 21 C1 VEE C1 VEE C1 VEE2B C1 = 0.027µF VCC = VEE = +3.3V (VEE typically ground) Recommended resistor and capacitor is size 805 22 G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 16 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch High-Speed Serial I/O Layout Considerations The high-speed serial signals contain digital data at fundamental frequencies up to 2.488GHz clock rate. Given that, in order to preserve the edges of such data sequences, it is necessary to have excellent frequency and phase response up to at least the 3rd harmonic, if not the 7th harmonic. Improved signal quality will result should the reader follow the general design rules below: 1. Keep traces as short as possible. Initial component placement should be very carefully considered. 2. The impedance of the traces must match that of the terminations, connectors and cable(s) in order to reduce reflections and impedance mismatches. Reflections can create standing waves that will increase the signal jitter. 3. Differential transmission line impedance must be maintained at 100Ω. 4. When routing differential pairs, keep the lengths identical for both traces. Differences in trace length translate directly into signal skew and can add to the signal jitter. Remember also that the differential impedance is affected by the separation between the traces. 5. Keep differential pair traces on the same side of the PCB to minimize impedance discontinuity, such as the one caused when using printed-circuit board vias. 6. Eliminate or reduce stubs. 7. Use rounded corners rather than 45° or 90° corners. 8. Keep signal traces far from other signals which might capacitively couple noise into the signals. This includes the other trace of a differential pair or the traces of the parallel PECL or TTL interface. 9. Do not cut up the power or ground planes in an effort to steer current paths. This usually produces more noise, not less. G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 17 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 18