VSC837

VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 Features • • • • • • • 68 Input by 68 Output Crosspoint Switch 3.2Gb/s NRZ Data Bandwidth 66MHz Multi-Mode Programming Port TTL/2.5V CMOS Control I/O (3.3V tolerant) Programmable On-Chip I/O Termination Input Signal Activity (ISA) Monitoring Function Integrated Signal Equalization (ISE) for Deterministic Jitter Reduction 3.2Gb/s 68x68 Crosspoint Switch • Single 2.5V Supply • Differential CML Output Driver • 11W typ/14W max (low drive mode) 13W typ/16W max (high drive mode) • Hard and Soft Power-Down for Unused Channels • High Performance 37.5mm, 480 TBGA Package General Description The VSC837 is a monolithic 68x68 asynchronous crosspoint switch, designed to carry broadband data streams. The non-blocking switch core is programmed through a triple-mode port interface that allows random access programming of each input/output port. A high degree of signal integrity is maintained throughout the chip via fully differential signal paths. The crosspoint function is based on a multiplexer array architecture. Each data output is driven by a 68:1 multiplexer that can be programmed to one and only one of its 68 inputs. The signal path is unregistered and fully asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input. Each high-speed output is a fully differential switched current driver with switchable on-die terminations for maximum signal integrity. Data inputs are terminated on die through 100Ω resistors between true and complement inputs (see Input Termination section for further detail). A triple-mode programming interface is provided that allows programming commands to be sent as serial data or one of two forms of parallel data. The input-referred mode (burst mode) allows an input port to be routed to all outputs in only 4 program cycles. Core programming can be random for each port address, or multiple program assignments can be queued and issued simultaneously. The programming may be initialized to a “straight-through” configuration (A0 to Y0, A1 to Y1, etc.) using the INITB pin. An activity monitor is provided to allow in-system diagnostics. The activity monitor can observe any highspeed input via an internal 69th multiplexer. Unused channels may be powered down to allow efficient use of the switch in applications that require only a subset of the channels. Power-down can be accomplished in hardware, via dedicated power pins for pairs of input and output channels, or in software by programming individual unused outputs with a disable code. VSC837 Block Diagram A0 2 2 Y0 A67 2 2 Y67 µP control G52309-0, Rev 3.0 02/16/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 68x68 Crosspoint Switch Preliminary Data Sheet VSC837 Functional Block Diagram A, AN[0:67] 68x69 Switch Core Y, YN[0:67] Internal 69th Output CONFIG INITB Core Program Registers Program Memory Program Interface Activity Monitor ACTCLK ALE_SCN ACTIVITY CSB LOAD OUTCHAN[18:0] SERIAL Functional Description Input / Output Characteristics All input data must be differential and should be nominally biased to +2.0V or AC-coupled. Other levels are allowed as described under the Input Termination section. On-chip terminations are provided, with a nominal impedance of 100Ω differential. All input termination resistors float with an internal bias provided for ACcoupling. For direct interconnection of multiple VSC837 devices, a CML termination mode is provided by tying the ITC pin to VCC, which ties the center point of the 100Ω termination to VCC, causing the terminations to act as loads for an open-drain or open-collector differential output. Data outputs are provided through differential current switches with on-chip back-termination. The output circuit is capable of driving external 50Ω far-end termination (recommended). The output back-terminations are electronically switchable to enable a power savings of 2W (max) by reducing the output driver current. Page 2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com INCHAN[6:0] SDOUT BURST G52309-0, Rev 3.0 02/16/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 Programming Interface 3.2Gb/s 68x68 Crosspoint Switch Parallel Mode In parallel mode (SERIAL=0, BURST=0), the binary word on INCHAN[6:0] is the numerical identifier of the input that will be routed to the specified output. OUTCHAN[6:0] is the numerical identifier of the output being programmed. A rising edge on the LOAD signal will transfer the programming data to the shadow register in the program memory. Raising CONFIG (asynchronously) will transfer the programming data to the main latches in the program memory and cause the internal select signals in the core to re-configure the multiplexer. Lowering CONFIG will latch the main latches. CONFIG may be tied HIGH to enable programming take effect instantaneously. This interface may be used with multiplexed address/data buses by using only INCHAN[6:0] without OUTCHAN[6:0] and dropping ALE when the address of the output to be programmed is present on INCHAN[6:0]. After the address is latched, the input address may be presented on INCHAN[6:0] and programming proceeds as above. No read-back capability is provided in parallel mode. Read-back for diagnostic purposes is provided in serial mode via the scan function. Serial Mode In serial mode (SERIAL=1, BURST=0), the INCHAN0 pin becomes the serial data input and the INCHAN1 pin becomes the serial clock (rising edge triggered). A serial word of the form [Output][Input] is shifted into the internal shift register, and the LOAD pin is asserted (HIGH) coincident with the last bit of the data word to signal that the word is to be applied. This transfers the input identifier to the shadow register of the addressed output. CONFIG is then applied (asynchronously) to transfer one or more program commands to the main latches of the program memories. The SDOUT pin follows the data on the INCHAN0_SDIN pin 14 clock cycles later. This enables the user to chain the serial ports of several crosspoints, shift program data for all switches through such a chain, and assert LOAD on all switches simultaneously to program all of the connections simultaneously. The output field is 7 bits long, representing the binary numerical identifier of the output to be programmed. The input field is 7 bits long, representing the numerical identifier of the input that will be routed to the specified output. Serial Read-Back Read-back of the program memory contents is accomplished in serial mode by setting the ALE_SCN pin HIGH. This will serially shift out the contents of the main latches in the program memories, slice 68 first and slice 0 last, and MSB-first, LSB-last for each 7-bit word. One rising edge of INCHAN1_SCLK with ALE_SCN=0 and SERIAL=1 must occur to load the entire 483-bit shift register prior to shifting out data. At a clock rate of 66MHz, this operation takes 7.26µs. G52309-0, Rev 3.0 02/16/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 68x68 Crosspoint Switch Preliminary Data Sheet VSC837 Burst Mode Burst mode programming (BURST=1, SERIAL=0) enables an input to be broadcast to any group of 1 to 17 outputs with a single command. In this mode, rising edges on the LOAD pin will trigger program operations. The INCHAN[6:0] pins represent the input to be broadcast. The OUTCHAN[18:17] pins represent the page (quarter) of the program memory to access, and each of the OUTCHAN[16:0] pins represents 1 of the 17 outputs within that page. A ’1’ on any of those pins will cause that output to be programmed to connect to the input named on INCHAN[6:0]. No read-back capability is provided in burst mode. See Serial Read-Back section above. Activity Monitoring The activity monitor observes the output of the internal 69th output from the core. By programming the 69th output to observe various inputs, the input signals can be scanned for activity or lack thereof. Each rising edge of ACTCLK causes the monitor to read out the activity state from the previous ACTCLK period and clears the internal activity state until a data transition triggers it again. There must be a minimum of one rising and one falling edge on the observed input data pin during the ACTCLK period for activity to be detected. After poweron the output of ACTIVITY after the first ACTCLK rising edge is unknown. Selective Power-Down Unused input and output channels can be made to consume little or no power via one of two methods of selective power-down. Software Power-Down Using this feature, unused outputs may be disabled, saving approximately 170 mW per channel for maximum dissipation conditions. This is accomplished by programming each unused output to look at input 127 (7F Hex), which represents a non-existent input channel. The channel may be subsequently activated by programming a valid input address. It is recommended, however, that any changes in power programming only be executed as part of an initialization sequence to guard against the effects of any switching transients that might result from changing the power supply current suddenly. Software mode does not affect the functioning or power of unused input channels. Hardware Power-Down Using this feature, the power associated with given pairs of inputs may be shut off by tying the corresponding VEE pin to VCC (see Table 10). Approximately 160 mW per input pair is saved under the maximum dissipation conditions. The power associated with given pairs of outputs, including their contribution to the core power, can be shut off by tying the corresponding VEE pin to VCC (see Table 10). Approximately 360 mW per output pair is saved under the maximum dissipation conditions. Certain VEE pins must always be active. In other words, tied to the most negative supply, so the corresponding inputs and outputs will always be on and consuming power. See Figure 6 and Table 10 for the location of these pins. Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52309-0, Rev 3.0 02/16/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 AC Characteristics Table 1: Data Path 3.2Gb/s 68x68 Crosspoint Switch Symbol fRATE tSKW tPDAY tR, tF tR, tF tJR tJP Maximum Data Rate Channel-to-channel delay skew Parameter Min — — — — — — — Typ — 300 750 — — — — Max 3.2 — — 150 150 10 40 Units Gb/s ps ps ps ps ps ps Propagation Delay from an A input to a Y output High-speed input rise/fall times, 20% to 80% High-speed output rise/fall times, 20% to 80% Output added delay jitter, rms (1, 2) Output added delay jitter, peak-to-peak(1, 2) NOTES:(1) Tested on a sample basis only. (2) Broadband (unfiltered) deterministic jitter added to a jitter-free input, 223-1 PRBS data pattern. Table 2: Program Interface Timing Symbol tsWRB thWRB tpwLW tsCSB thCSB tpwCFG tsSDIN thSDIN tperSCLK tsLOAD thLOAD tsSERIAL thSERIAL tsBURST thBURST tdsDOUT tpwINITB tsSCAN thSCAN Parameter Setup time from INCHAN[6:0] or OUTCHAN[6:0] to rising edge of WRB Hold time from rising edge of WRB to INCHAN[6:0] or OUTCHAN[6:0] Pulse width (HIGH or LOW) on LOAD Setup time from CSB to falling edge of LOAD or ALE_SCN in parallel or burst mode, or rising edge of LOAD in serial mode. Hold time of CSB rising edge after LOAD or ALE_SCN rising in parallel or burst mode, or falling edge of LOAD in serial mode, or falling edge of CONFIG in any mode. Pulse width (HIGH or LOW) on CONFIG Setup time from INCHAN0_SDIN to INCHAN1_SCLK rising Hold time of INCHAN0_SDIN after INCHAN1_SCLK rising Minimum period of SCLK in serial mode Setup time from LOAD to INCHAN1_SCLK rising Hold time of LOAD after INCHAN1_SCLK rising Setup time from SERIAL rising to INCHAN1_SCLK rising when entering serial mode or SERIAL falling to LOAD falling when entering parallel mode or SERIAL falling to LOAD rising when entering burst mode. Hold time from INCHAN1_SCLK rising to SERIAL falling when exiting serial mode. Setup time from BURST rising to LOAD rising when entering burst mode or BURST falling to LOAD falling when entering parallel mode. Hold time from LOAD rising to BURST falling when exiting burst mode. Delay from INCHAN1_SCLK rising to SDOUT, 20pF load. Pulse width (HIGH or LOW) on INITB Setup time from ALE_SCN to INCHAN1_SCLK rising when starting or completing a serial read-back sequence. Hold time of ALE_SCN after INCHAN1_SCLK rising when starting or completing a serial read-back sequence. Min 3.35 1.45 6.75 0 0 6.75 1.65 1.0 15 1.85 0.95 0.90 0 1.85 2.45 — 6.75 1.65 1.0 Typ — — — — — — — — — — — — — — — — — — — Max — — — — — — — — — — — — — — — 6.20 — — — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns G52309-0, Rev 3.0 02/16/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 5 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 68x68 Crosspoint Switch Preliminary Data Sheet VSC837 Output Address Input Address tsWRB thWRB thCSB Figure 1: Parallel Mode—Separate Address/Data (leave ALE_SCN pin HIGH) OUTCHAN[6:0] INCHAN[6:0] LOAD tsCSB CSB tpwCFG CONFIG tsSERIAL SERIAL tpwLW Figure 2: Parallel Mode—Multiplexed Address/Data INCHAN[6:0] Output Address Input Address tsWRB ALE_SCN tpwLW LOAD tsCSB tpwCFG CONFIG tsSERIAL thCSB thWRB CSB SERIAL Figure 3: Burst Mode OUTCHAN[18:17] OUTCHAN[16:0] INCHAN[6:0] Output Page Output ID Bits Input Address tsWRB LOAD tsCSB CSB tpwCFG CONFIG tpwLW thCSB Output Page Output ID Bits Input Address thWRB BURST tsBURST thBURST Page 6 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52309-0, Rev 3.0 02/16/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 3.2Gb/s 68x68 Crosspoint Switch Figure 4: Serial Mode (leave ALE_SCN pin LOW during programming) INCHAN0_SDIN O6 tsSDIN INCHAN1_SCLK tdsDOUT SDOUT tsLOAD LOAD tsCSB tpwCFG CONFIG tsSERIAL SERIAL O(n) = Output Address Bit (n), I(n) = Input Address Bit (n) thCSB O6 O5 O4 O3 O5 O4 thSDIN O3 O2 O1 O0 I6 I5 I4 I3 I2 I1 I0 tperSCLK thLOAD CSB Figure 5: Serial Read-Back thSCAN ALE_SCN tsSCAN INCHAN1_SCLK tdsDOUT SDOUT tsSERIAL SERIAL MSB of program memory for output 68 Read-back shift register (483 bits long) is loaded here on rising edge of INCHAN1_SCLK with SERIAL HIGH and ALE_SCN LOW 68 68 68 68 68 68 68 67 67 67 67 67 67 67 66 tperSCLK B6 B5 B4 B3 B2 B1 B0 B6 B5 B4 B3 B2 B1 B0 B6 G52309-0, Rev 3.0 02/16/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 7 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 68x68 Crosspoint Switch Preliminary Data Sheet VSC837 DC Characteristics All characteristics are over the specified operating conditions. Table 3: Power Supply Requirements Symbol ICC PT Parameter VCC supply current Total chip power (with ITERM = 0 and backterminations ON, high drive) Min Typ 5600 13 Max 6095 16 Units mA W Conditions Table 4: Control Port Input Levels (TTL/CMOS) Symbol VIH VIL IIH IIL VOH VOL VOHPU VOLPU Parameter Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Output HIGH voltage Output LOW voltage VOH with external pull-up VOL with external pull-up Min 1.7 0 Typ Max VCC+ 1.0 Units V V µA µA V V V V Conditions 0.8 TBD TBD VCC0.2 VCC 0.2 0.4 DC load < 500µA DC load < 2mA 250Ω to 3.3V(5%) 250Ω to 3.3V(5%) 0 2.4 Table 5: Signal Input Levels (high-speed signal path) Symbol VIN VICM Parameter Input voltage amplitude Input common-mode voltage Min 150 VCC 0.7 Typ Max 1100 VCC 0.2 Units mV V Conditions See Note 1 See Note 2 Table 6: Signal Output Levels (high-speed signal path) TERM_CTRL=ON, DRIVE_CTRL=HI Symbol VOUT VOCM Parameter Output differential voltage Output common-mode voltage Min 400 VCC0.3 Typ Max 600 VCC0.2 Units mV V Conditions See Note 1, 3 See Note 2, 3 NOTES: (1) Mean peak-to-peak amplitude measurement of either true or complement of the differential signal. (2) VCC = VCCP = 2.5V, VEE = 0V. (3) Terminated in 50Ω to VCC. This termination is used for testing the part, but other terminations are allowed—see Table 9. Page 8 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52309-0, Rev 3.0 02/16/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 I/O Equivalent Circuits ITC VCC 3.2Gb/s 68x68 Crosspoint Switch TERM_CTRL 50 PAD 50 PAD PAD 50 50 PAD DRIVE_CTRL H/S Input Equivalent Circuit H/S Output Equivalent Circuit Input Termination The high-speed inputs of the VSC837 are internally terminated by a 100Ω resistor between true and complement inputs. Termination resistors are isolated from each other on-chip. The termination will self-bias to +2.0V (nominal) for AC-coupled applications. The ITC pin enables direct interconnection of multiple VSC837 devices. With ITC tied to VCC, the center point of the 100Ω termination resistor is tied to VCC, causing the terminations to act as loads for an open-drain or open-collector differential output. Table 7: Allowed Input Termination Schemes Type 1 2 3 4 5 AC-coupled input Description Comments Tie ITC LOW, 100Ω differential input termination, input self-biased Tie ITC HIGH, terminations acts as 50Ω load to VCC Tie ITC HIGH, terminations acts as 50Ω load to VCC Tie ITC LOW, 100Ω differential termination (preferred over Type 3) Tie ITC LOW, 100Ω differential termination DC-coupled from open-drain CML DC-coupled from back-terminated 2.5V CML DC-coupled from back-terminated 2.5V CML DC-coupled from back-terminated 3.3V LV-PECL Some allowed termination schemes result in additional ICC current and power dissipation on-chip. See Table 8. Table 8: Additional Current and Power Symbol ICC-C PCC-C Description Additional ICC current when receiving DC-Coupled CML (ITC = HIGH) Min Typ Max 680 0.340 Units mA W Conditions Additional power dissipated on-chip for DC terminating CML at inputs G52309-0, Rev 3.0 02/16/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 9 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 68x68 Crosspoint Switch Preliminary Data Sheet VSC837 Output Termination The high-speed outputs of the VSC837 are internally back terminated by 50 Ω t o V CC w hen the TERM_CTRL pin is HIGH. When this pin is LOW, the output driver functions as an open-drain CML driver. Setting DRIVE_CTRL LOW (GND) saves 2W under maximum power dissipation conditions. See Table 9 for allowable types of terminations and modes of operation. Table 9: Allowed High-Speed Output Terminations and Modes of Operation Type 1 2 3 4 5 6 7 8 Description AC-Coupled to 50Ω termination to any voltage AC-Coupled to 100Ω differential termination DC-Coupled, terminated in 50Ω to VCC at far-end only DC-Coupled, terminated in 50Ω to VCC at far-end only DC-Coupled, source and far-end terminated in 50Ω to VCC DRIVE_ CTRL VCC (HIGH) VCC (HIGH) GND (LOW) VCC (HIGH) GND (LOW) VCC (HIGH) GND (LOW) VCC (HIGH) TERM_ CTRL VCC (ON) VCC (ON) GND (OFF) GND (OFF) VCC (ON) VCC (ON) VCC (ON) VCC (ON) VOD(1) (mV) typ 500 500 500 1000 250 500 250 500 VOCM(1) (V) typ 2.0 2.0 2.25 2.0 2.375 2.25 2.25 2.0 DC-Coupled, 100Ω differential termination DC-Coupled, source and far-end terminated in 50Ω to VCC DC-Coupled, 100Ω differential termination NOTE: (1) Measured at output of VSC837, with VCC = 2.5V. Absolute Maximum Ratings(1) Power Supply Voltage (VCC) Potential to GND ................................................................................-0.5V to +4.V TTL Input Voltage Applied .....................................................................................................-0.5V to VCC+1.0V ECL Input Voltage Applied ....................................................................................................-0.5V to VCC +0.5V Output Current (IOUT) .................................................................................................................................... 50mA Case Temperature Under Bias (TC) ............................................................................................. -55oC to + 125oC Storage Temperature (TSTG) ........................................................................................................ -65oC to + 150oC NOTE: (1) Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Operating Conditions Supply Voltage (VEE).......................................................................................................................................... 0V Supply Voltage (VCC) ............................................................................................................................+2.5V ±5% Supply Voltage (VCCP)...........................................................................................................................+2.5V ±5% Case Temperature Operating Range (T).............................................................................................. 0oC to 85oC Page 10 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52309-0, Rev 3.0 02/16/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 Package Pin Descriptions Figure 6: Pinout Diagram—Bottom View 3.2Gb/s 68x68 Crosspoint Switch 29 28 27 26 25 24 23 2 22 6 21 10 20 14 19 18 18 22 17 26 16 30 15 34 14 38 13 42 12 46 11 50 10 54 9 58 8 62 7 66 6 5 4 3 2 1 Ball grid index A OUTCHAN10 OUTCHAN11 OUTCHAN14 OUTCHAN13 OUTCHAN12 OUTCHAN5 OUTCHAN6 B OUTCHAN9 C OUTCHAN8 D OUTCHAN15 OUTCHAN16 OUTCHAN18 OUTCHAN17 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 OUTCHAN7 OUTCHAN2 OUTCHAN3 OUTCHAN4 OUTCHAN1 OUTCHAN0 E F G H J K L M N P R T U V W Y AA AB AC CONFIG Inputs [An, ANn] Outputs [Yn, YNn] Common VEE (always On) control port Outputs [Yn, YNn] INCHAN6 ALE_SCN LOAD TERM_CTRL INCHAN5 ACTCLK CMV ITC Inputs [An, ANn] INCHAN2 SERIAL DRIVE_CTRL ACTIVITY G52309-0, Rev 3.0 02/16/01 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 INCHAN1_SCLK INCHAN0_SDIN INCHAN3 INCHAN4 2 6 1 5 3 7 VCC Dedicated VEE 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 3 7 11 15 19 23 1 5 9 13 17 21 11 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 15 19 23 27 31 35 39 43 47 51 55 59 63 67 AD AE AF 27 31 35 39 43 47 51 55 59 63 67 CSB SDOUT AG BURST AH 25 29 33 37 41 45 49 53 57 61 65 INITB AJ © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 11 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 68x68 Crosspoint Switch Table 10: Package Pin Identifications Preliminary Data Sheet VSC837 Function Level Signal Name Pin High-Speed Data Inputs A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 D23 AH23 B23 AF23 D22 AH22 B22 AF22 D21 AH21 B21 AF21 D20 AH20 B20 AF20 D19 AH19 B19 AF19 D18 AH18 B18 AF18 D17 AH17 B17 AF17 D16 AH16 B16 AF16 D15 AH15 B15 AF15 High-Speed Data Input Channel 0, True High-Speed Data Input Channel 1, True High-Speed Data Input Channel 2, True High-Speed Data Input Channel 3, True High-Speed Data Input Channel 4, True High-Speed Data Input Channel 5, True High-Speed Data Input Channel 6, True High-Speed Data Input Channel 7, True High-Speed Data Input Channel 8, True High-Speed Data Input Channel 9, True High-Speed Data Input Channel 10, True High-Speed Data Input Channel 11, True High-Speed Data Input Channel 12, True High-Speed Data Input Channel 13, True High-Speed Data Input Channel 14, True High-Speed Data Input Channel 15, True High-Speed Data Input Channel 16, True High-Speed Data Input Channel 17, True High-Speed Data Input Channel 18, True High-Speed Data Input Channel 19, True High-Speed Data Input Channel 20, True High-Speed Data Input Channel 21, True High-Speed Data Input Channel 22, True High-Speed Data Input Channel 23, True High-Speed Data Input Channel 24, True High-Speed Data Input Channel 25, True High-Speed Data Input Channel 26, True High-Speed Data Input Channel 27, True High-Speed Data Input Channel 28, True High-Speed Data Input Channel 29, True High-Speed Data Input Channel 30, True High-Speed Data Input Channel 31, True High-Speed Data Input Channel 32, True High-Speed Data Input Channel 33, True High-Speed Data Input Channel 34, True High-Speed Data Input Channel 35, True PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL Page 12 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52309-0, Rev 3.0 02/16/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 Signal Name A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 AN0 AN1 AN2 AN3 AN4 AN5 AN6 3.2Gb/s 68x68 Crosspoint Switch Function High-Speed Data Input Channel 36, True High-Speed Data Input Channel 37, True High-Speed Data Input Channel 38, True High-Speed Data Input Channel 39, True High-Speed Data Input Channel 40, True High-Speed Data Input Channel 41, True High-Speed Data Input Channel 42, True High-Speed Data Input Channel 43, True High-Speed Data Input Channel 44, True High-Speed Data Input Channel 45, True High-Speed Data Input Channel 46, True High-Speed Data Input Channel 47, True High-Speed Data Input Channel 48, True High-Speed Data Input Channel 49, True High-Speed Data Input Channel 50, True High-Speed Data Input Channel 51, True High-Speed Data Input Channel 52, True High-Speed Data Input Channel 53, True High-Speed Data Input Channel 54, True High-Speed Data Input Channel 55, True High-Speed Data Input Channel 56, True High-Speed Data Input Channel 57, True High-Speed Data Input Channel 58, True High-Speed Data Input Channel 59, True High-Speed Data Input Channel 60, True High-Speed Data Input Channel 61, True High-Speed Data Input Channel 62, True High-Speed Data Input Channel 63, True High-Speed Data Input Channel 64, True High-Speed Data Input Channel 65, True High-Speed Data Input Channel 66 True High-Speed Data Input Channel 67, True High-Speed Data Input Channel 0, Complement High-Speed Data Input Channel 1, Complement High-Speed Data Input Channel 2, Complement High-Speed Data Input Channel 3, Complement High-Speed Data Input Channel 4, Complement High-Speed Data Input Channel 5, Complement High-Speed Data Input Channel 6, Complement Pin D14 AH14 B14 AF14 D13 AH13 B13 AF13 D12 AH12 B12 AF12 D11 AH11 B11 AF11 D10 AH10 B10 AF10 D9 AH9 B9 AF9 D8 AH8 B8 AF8 D7 AH7 B7 AF7 E23 AJ23 A23 AE23 E22 AJ22 A22 Level PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL G52309-0, Rev 3.0 02/16/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 13 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 68x68 Crosspoint Switch Signal Name AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 AN40 AN41 AN42 AN43 AN44 AN45 Preliminary Data Sheet VSC837 Function High-Speed Data Input Channel 7, Complement High-Speed Data Input Channel 8, Complement High-Speed Data Input Channel 9, Complement High-Speed Data Input Channel 10, Complement High-Speed Data Input Channel 11, Complement High-Speed Data Input Channel 12, Complement High-Speed Data Input Channel 13, Complement High-Speed Data Input Channel 14, Complement High-Speed Data Input Channel 15, Complement High-Speed Data Input Channel 16, Complement High-Speed Data Input Channel 17, Complement High-Speed Data Input Channel 18, Complement High-Speed Data Input Channel 19, Complement High-Speed Data Input Channel 20, Complement High-Speed Data Input Channel 21, Complement High-Speed Data Input Channel 22, Complement High-Speed Data Input Channel 23, Complement High-Speed Data Input Channel 24, Complement High-Speed Data Input Channel 25, Complement High-Speed Data Input Channel 26, Complement High-Speed Data Input Channel 27, Complement High-Speed Data Input Channel 28, Complement High-Speed Data Input Channel 29, Complement High-Speed Data Input Channel 30, Complement High-Speed Data Input Channel 31, Complement High-Speed Data Input Channel 32, Complement High-Speed Data Input Channel 33, Complement High-Speed Data Input Channel 34, Complement High-Speed Data Input Channel 35, Complement High-Speed Data Input Channel 36, Complement High-Speed Data Input Channel 37, Complement High-Speed Data Input Channel 38, Complement High-Speed Data Input Channel 39, Complement High-Speed Data Input Channel 40, Complement High-Speed Data Input Channel 41, Complement High-Speed Data Input Channel 42, Complement High-Speed Data Input Channel 43, Complement High-Speed Data Input Channel 44, Complement High-Speed Data Input Channel 45, Complement Pin AE22 E21 AJ21 A21 AE21 E20 AJ20 A20 AE20 E19 AJ19 A19 AE19 E18 AJ18 A18 AE18 E17 AJ17 A17 AE17 E16 AJ16 A16 AE16 E15 AJ15 A15 AE15 E14 AJ14 A14 AE14 E13 AJ13 A13 AE13 E12 AJ12 Level PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL Page 14 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52309-0, Rev 3.0 02/16/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 Signal Name AN46 AN47 AN48 AN49 AN50 AN51 AN52 AN53 AN54 AN55 AN56 AN57 AN58 AN59 AN60 AN61 AN62 AN63 AN64 AN65 AN66 AN67 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 3.2Gb/s 68x68 Crosspoint Switch Function High-Speed Data Input Channel 46, Complement High-Speed Data Input Channel 47, Complement High-Speed Data Input Channel 48, Complement High-Speed Data Input Channel 49, Complement High-Speed Data Input Channel 50, Complement High-Speed Data Input Channel 51, Complement High-Speed Data Input Channel 52, Complement High-Speed Data Input Channel 53, Complement High-Speed Data Input Channel 54, Complement High-Speed Data Input Channel 55, Complement High-Speed Data Input Channel 56, Complement High-Speed Data Input Channel 57, Complement High-Speed Data Input Channel 58, Complement High-Speed Data Input Channel 59, Complement High-Speed Data Input Channel 60, Complement High-Speed Data Input Channel 61, Complement High-Speed Data Input Channel 62, Complement High-Speed Data Input Channel 63, Complement High-Speed Data Input Channel 64, Complement High-Speed Data Input Channel 65, Complement High-Speed Data Input Channel 66, Complement High-Speed Data Input Channel 67, Complement High-Speed Data Output Channel 0, True High-Speed Data Output Channel 1, True High-Speed Data Output Channel 2, True High-Speed Data Output Channel 3, True High-Speed Data Output Channel 4, True High-Speed Data Output Channel 5, True High-Speed Data Output Channel 6, True High-Speed Data Output Channel 7, True High-Speed Data Output Channel 8, True High-Speed Data Output Channel 9, True High-Speed Data Output Channel 10, True High-Speed Data Output Channel 11, True High-Speed Data Output Channel 12, True High-Speed Data Output Channel 13, True High-Speed Data Output Channel 14, True High-Speed Data Output Channel 15, True Pin A12 AE12 E11 AJ11 A11 AE11 E10 AJ10 A10 AE10 E9 AJ9 A9 AE9 E8 AJ8 A8 AE8 E7 AJ7 A7 AE7 G28 G4 G26 G2 H28 H4 H26 H2 J28 J4 J26 J2 K28 K4 K26 K2 Level PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML High-Speed Data Outputs G52309-0, Rev 3.0 02/16/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 15 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 68x68 Crosspoint Switch Signal Name Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51 Y52 Y53 Y54 Preliminary Data Sheet VSC837 Function High-Speed Data Output Channel 16, True High-Speed Data Output Channel 17, True High-Speed Data Output Channel 18, True High-Speed Data Output Channel 19, True High-Speed Data Output Channel 20, True High-Speed Data Output Channel 21, True High-Speed Data Output Channel 22, True High-Speed Data Output Channel 23, True High-Speed Data Output Channel 24, True High-Speed Data Output Channel 25, True High-Speed Data Output Channel 26, True High-Speed Data Output Channel 27, True High-Speed Data Output Channel 28, True High-Speed Data Output Channel 29, True High-Speed Data Output Channel 30, True High-Speed Data Output Channel 31, True High-Speed Data Output Channel 32, True High-Speed Data Output Channel 33, True High-Speed Data Output Channel 34, True High-Speed Data Output Channel 35, True High-Speed Data Output Channel 36, True High-Speed Data Output Channel 37, True High-Speed Data Output Channel 38, True High-Speed Data Output Channel 39, True High-Speed Data Output Channel 40, True High-Speed Data Output Channel 41, True High-Speed Data Output Channel 42, True High-Speed Data Output Channel 43, True High-Speed Data Output Channel 44, True High-Speed Data Output Channel 45, True High-Speed Data Output Channel 46, True High-Speed Data Output Channel 47, True High-Speed Data Output Channel 48, True High-Speed Data Output Channel 49, True High-Speed Data Output Channel 50, True High-Speed Data Output Channel 51, True High-Speed Data Output Channel 52, True High-Speed Data Output Channel 53, True High-Speed Data Output Channel 54, True Pin L28 L4 L26 L2 M28 M4 M26 M2 N28 N4 N26 N2 P28 P4 P26 P2 R28 R4 R26 R2 T28 T4 T26 T2 U28 U4 U26 U2 V28 V4 V26 V2 W28 W4 W26 W2 Y28 Y4 Y26 Level CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML Page 16 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52309-0, Rev 3.0 02/16/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 Signal Name Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 YN0 YN1 YN2 YN3 YN4 YN5 YN6 YN7 YN8 YN9 YN10 YN11 YN12 YN13 YN14 YN15 YN16 YN17 YN18 YN19 YN20 YN21 YN22 YN23 YN24 YN25 3.2Gb/s 68x68 Crosspoint Switch Function High-Speed Data Output Channel 55, True High-Speed Data Output Channel 56, True High-Speed Data Output Channel 57, True High-Speed Data Output Channel 58, True High-Speed Data Output Channel 59, True High-Speed Data Output Channel 60, True High-Speed Data Output Channel 61, True High-Speed Data Output Channel 62, True High-Speed Data Output Channel 63, True High-Speed Data Output Channel 64, True High-Speed Data Output Channel 65, True High-Speed Data Output Channel 66, True High-Speed Data Output Channel 67, True High-Speed Data Output Channel 0, Complement High-Speed Data Output Channel 1, Complement High-Speed Data Output Channel 2, Complement High-Speed Data Output Channel 3, Complement High-Speed Data Output Channel 4, Complement High-Speed Data Output Channel 5, Complement High-Speed Data Output Channel 6, Complement High-Speed Data Output Channel 7, Complement High-Speed Data Output Channel 8, Complement High-Speed Data Output Channel 9, Complement High-Speed Data Output Channel 10, Complement High-Speed Data Output Channel 11, Complement High-Speed Data Output Channel 12, Complement High-Speed Data Output Channel 13, Complement High-Speed Data Output Channel 14, Complement High-Speed Data Output Channel 15, Complement High-Speed Data Output Channel 16, Complement High-Speed Data Output Channel 17, Complement High-Speed Data Output Channel 18, Complement High-Speed Data Output Channel 19, Complement High-Speed Data Output Channel 20, Complement High-Speed Data Output Channel 21, Complement High-Speed Data Output Channel 22, Complement High-Speed Data Output Channel 23, Complement High-Speed Data Output Channel 24, Complement High-Speed Data Output Channel 25, Complement Pin Y2 AA28 AA4 AA26 AA2 AB28 AB4 AB26 AB2 AC28 AC4 AC26 AC2 G29 G5 G25 G1 H29 H5 H25 H1 J29 J5 J25 J1 K29 K5 K25 K1 L29 L5 L25 L1 M29 M5 M25 M1 N29 N5 Level CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML G52309-0, Rev 3.0 02/16/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 17 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 68x68 Crosspoint Switch Signal Name YN26 YN27 YN28 YN29 YN30 YN31 YN32 YN33 YN34 YN35 YN36 YN37 YN38 YN39 YN40 YN41 YN42 YN43 YN44 YN45 YN46 YN47 YN48 YN49 YN50 YN51 YN52 YN53 YN54 YN55 YN56 YN57 YN58 YN59 YN60 YN61 YN62 YN63 YN64 Preliminary Data Sheet VSC837 Function High-Speed Data Output Channel 26, Complement High-Speed Data Output Channel 27, Complement High-Speed Data Output Channel 28, Complement High-Speed Data Output Channel 29, Complement High-Speed Data Output Channel 30, Complement High-Speed Data Output Channel 31, Complement High-Speed Data Output Channel 32, Complement High-Speed Data Output Channel 33, Complement High-Speed Data Output Channel 34, Complement High-Speed Data Output Channel 35, Complement High-Speed Data Output Channel 36, Complement High-Speed Data Output Channel 37, Complement High-Speed Data Output Channel 38, Complement High-Speed Data Output Channel 39, Complement High-Speed Data Output Channel 40, Complement High-Speed Data Output Channel 41, Complement High-Speed Data Output Channel 42, Complement High-Speed Data Output Channel 43, Complement High-Speed Data Output Channel 44, Complement High-Speed Data Output Channel 45, Complement High-Speed Data Output Channel 46, Complement High-Speed Data Output Channel 47, Complement High-Speed Data Output Channel 48, Complement High-Speed Data Output Channel 49, Complement High-Speed Data Output Channel 50, Complement High-Speed Data Output Channel 51, Complement High-Speed Data Output Channel 52, Complement High-Speed Data Output Channel 53, Complement High-Speed Data Output Channel 54, Complement High-Speed Data Output Channel 55, Complement High-Speed Data Output Channel 56, Complement High-Speed Data Output Channel 57, Complement High-Speed Data Output Channel 58, Complement High-Speed Data Output Channel 59, Complement High-Speed Data Output Channel 60, Complement High-Speed Data Output Channel 61, Complement High-Speed Data Output Channel 62, Complement High-Speed Data Output Channel 63, Complement High-Speed Data Output Channel 64, Complement Pin N25 N1 P29 P5 P25 P1 R29 R5 R25 R1 T29 T5 T25 T1 U29 U5 U25 U1 V29 V5 V25 V1 W29 W5 W25 W1 Y29 Y5 Y25 Y1 AA29 AA5 AA25 AA1 AB29 AB5 AB25 AB1 AC29 Level CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML Page 18 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52309-0, Rev 3.0 02/16/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 Signal Name YN65 YN66 YN67 3.2Gb/s 68x68 Crosspoint Switch Function High-Speed Data Output Channel 65, Complement High-Speed Data Output Channel 66, Complement High-Speed Data Output Channel 67, Complement Clock for Activity Monitor (