VSC838UG

VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC838 Features • 36 Input by 37 Output Crosspoint Switch • 3.2Gb/s NRZ Data Bandwidth • Non-Blocking Architecture Broadcast and Multicast Capabilities • LVTTL/2.5V CMOS Control I/O (3.3V tolerant) • Input Signal Activity Monitoring Function • Integrated Signal Equalization (ISE) for Deterministic Jitter Reduction 3.2Gb/s 36x37 Crosspoint Switch • 66MHz Dual Programming Port • Parallel and Serial programming modes • Programmable On-Chip I/O Termination • Differential CML Output Drivers • Single 2.5V Supply • 6W Typical—Low Drive Mode 7W Typical—High Drive Mode • High Performance 37.5mm, 480 TBGA Package General Description The VSC838 is a monolithic 36x36 asynchronous crosspoint switch, designed to carry broadband data streams. The VSC838 also has an internal 37th output channel which is used in conjunction with the Activity Monitor to allow in system diagnostics. A high degree of signal integrity is maintained throughout the chip via fully differential signal paths. The crosspoint function is based on a multiplexer array architecture. Each data output is driven by a 36:1 multiplexer that can be programmed to one and only one of its 36 inputs. The signal path is unregistered and fully asynchronous, so there are not any restrictions on the phase, frequency, or signal pattern at each input. Each high-speed output is a fully differential, switched current driver with switchable on-die terminations for maximum signal integrity. Data inputs are terminated on-die through 100Ω impedance between true and complement inputs (see Input Termination section for further details). A dual mode programming interface is provided that allows programming commands to be sent as serial data or parallel data. Core programming can be random for each port address, or multiple program assignments can be queued and issued simultaneously. The programming may be initialized to a “straight-through” configuration (A0 to Y0, A1 to Y1, etc.) using the INIT pin. Unused channels may be powered down to allow efficient use of the switch in applications that require only a subset of the channels. Power-down can be accomplished in hardware, via dedicated power pins for pairs of input and output channels, or in software by programming individual unused outputs with a disable code. VSC838 Block Diagram A0 2 2 Y0 A35 2 2 Y35 µP control G52351-0, Rev 3.0 02/12/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 36x37 Crosspoint Switch Preliminary Data Sheet VSC838 Functional Block Diagram A, AN[0:35] 36 x 37 SWITCH CORE Y, YN[0:35] INTERNAL 37th OUTPUT CONFIG CORE PROGRAM REGISTERS INIT PROGRAM MEMORY PROGRAM INTERFACE ACTIVITY MONITOR OUTCHAN [5:0] INCHAN [5:0] ALE_SCN Page 2 ACTIVITY SERIAL SDOUT ACTCLK ACTCHAN LOAD CS © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52351-0, Rev 3.0 02/12/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC838 Functional Description 3.2Gb/s 36x37 Crosspoint Switch Input / Output Characteristics All input data must be differential and should be nominally biased to +2.0V or AC-coupled. Other levels are allowed as described under the Input Termination section. On-chip terminations are provided, with a nominal impedance of 100Ω differential. All input termination resistors float with an internal bias provided for ACcoupling. For direct interconnection of multiple VSC838 devices, a CML termination mode is provided by tying the ITC pin to VCC, which ties the center point of the 100Ω termination to VCC, causing the terminations to act as loads for an open-drain or open-collector differential output. Data outputs are provided through differential current switches with on-chip back-termination. The output circuit is capable of driving external 50Ω far-end termination (recommended). The output back-terminations are electronically switchable to enable a power savings of 1W (max) by reducing the output driver current. Programming Interface Parallel Mode In parallel mode (SERIAL=0), the binary word on INCHAN[5:0] is the numerical identifier of the input that will be routed to the specified output. OUTCHAN[5:0] is the numerical identifier of the output being programmed. A rising edge on the LOAD signal will transfer the programming data to the shadow register in the program memory. Raising CONFIG (asynchronously) will transfer the programming data to the main latches in the program memory and cause the internal select signals in the core to re-configure the multiplexer. Lowering CONFIG will latch the main latches. CONFIG may be tied HIGH to enable programming to take effect instantaneously. This interface may be used with multiplexed address/data buses by using only INCHAN[5:0] without OUTCHAN[5:0] and dropping ALE when the address of the output to be programmed is present on INCHAN[5:0]. After the address is latched, the input address may be presented on INCHAN[5:0] and programming proceeds as above. No read-back capability is provided in parallel mode. Read-back for diagnostic purposes is provided in serial mode via the scan function. Serial Mode In serial mode (SERIAL=1), the INCHAN[0] pin becomes the serial data input SDIN and the INCHAN[1] pin becomes the serial clock SCLK (rising edge triggered). A serial word of the form [Output][Input] is shifted into the internal shift register, and the LOAD pin is asserted (HIGH) coincident with the last bit of the data word to signal that the word is to be applied. This transfers the input identifier to the shadow register of the addressed output. CONFIG is then applied (asynchronously) to transfer one or more program commands to the main latches of the program memories. The SDOUT pin follows the data on the INCHAN[0](SDIN) pin 14 clock cycles later. This enables the user to chain the serial ports of several crosspoints, shift program data for all switches through such a chain, and assert LOAD on all switches simultaneously to program all of the connections simultaneously. The output field is 7 bits long, representing the binary numerical identifier of the output to be programmed. The input field is 7 bits long, representing the numerical identifier of the input that will be routed to the specified output. G52351-0, Rev 3.0 02/12/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 36x37 Crosspoint Switch Preliminary Data Sheet VSC838 Serial Read-Back Read-back of the program memory contents is accomplished in serial mode by setting the ALE_SCN pin HIGH. This will serially shift out the contents of the main latches in the program memories, slice 36 first and slice 0 last, and MSB-first, LSB-last for each 7-bit word (see Figure 3). One rising edge of INCHAN[1](SCLK) with ALE_SCN=0 and SERIAL=1 must occur to load the entire 483-bit shift register prior to shifting out data. At a clock rate of 66MHz, this operation takes 7.26µs. Activity Monitoring The activity monitor observes the output of the internal 37th output from the core. By programming the th output to observe various inputs, the input signals can be scanned for activity or lack thereof. Each rising 37 edge of ACTCLK causes the monitor to read out the activity state from the previous ACTCLK period and clears the internal activity state until a data transition triggers it again. There must be a minimum of one rising and one falling edge on the observed input data pin during the ACTCLK period for activity to be detected. After poweron the output of ACTIVITY after the first ACTCLK rising edge is unknown. To access the 37th output, ACTCHAN and INCHAN[5] must both be HIGH. Selective Power-Down Unused input and output channels can be made to consume little or no power via one of two methods of selective power-down. Software Power-Down Using this feature, unused outputs may be disabled, saving approximately 170 mW per channel for maximum dissipation conditions. This is accomplished by programming each unused output to look at input 127 (7F Hex), which represents a non-existent input channel. The channel may be subsequently activated by programming a valid input address. It is recommended, however, that any changes in power programming only be executed as part of an initialization sequence to guard against the effects of any switching transients that might result from changing the power supply current suddenly. Software mode does not affect the functioning or power of unused input channels. Hardware Power-Down Using this feature, the power associated with given pairs of inputs may be shut off by tying the corresponding VEE pin to VCC (see Table 10). Approximately 160 mW per input pair is saved under the maximum dissipation conditions. The power associated with given pairs of outputs, including their contribution to the core power, can be shut off by tying the corresponding VEE pin to VCC (see Table 10). Approximately 360 mW per output pair is saved under the maximum dissipation conditions. Certain VEE pins must always be active. In other words, tied to the most negative supply, so the corresponding inputs and outputs will always be on and consuming power. See Figure 7 and Table 10 for the location of these pins. Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52351-0, Rev 3.0 02/12/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC838 AC Characteristics Table 1: Data Path 3.2Gb/s 36x37 Crosspoint Switch Parameter fRATE TSKW TPDAY tR, tF tR, tF tjR tjP Maximum data rate Description Channel-to-channel delay skew Propagation Delay from an A input to a Y output High-speed input rise/fall times, 20% to 80% High-speed output rise/fall times, 20% to 80% Output added delay jitter, rms (1, 2) Min - Typ 300 750 - Max 3.2 150 150 10 40 23 Units Gb/s ps ps ps ps ps ps Output added delay jitter, peak-to-peak(1, 2) NOTES: (1) Tested on a sample basis only. (2) Broadband (unfiltered) deterministic jitter added to a jitter-free input, 2 -1 PRBS data pattern. Table 2: Program Interface Timing Parameter TsWR ThWR TPWLW TsCS ThCSB TPWCFG TsSDIN ThSDIN TperSCLK TsLOAD ThLOAD TsSERIAL Description Setup time from INCHAN[5:0] or OUTCHAN5:0] to rising edge of WR. Hold time from rising edge of WRB to INCHAN[5:0] or OUTCHAN[5:0]. Pulse width (HIGH or LOW) on LOAD Setup time from CS to falling edge of LOAD or ALE_SCN in parallel or burst mode, or rising edge of LOAD in serial mode. Hold time of CS rising edge after LOAD or ALE_SCN rising in parallel or burst mode, or falling edge of LOAD in serial mode, or falling edge of CONFIG in any mode. Pulse width (HIGH or LOW) on CONFIG. Setup time from INCHAN0(SDIN) to INCHAN1(SCLK) rising. Hold time of INCHAN0(SDIN) after INCHAN1(SCLK) rising. Minimum period of SCLK in serial mode. Setup time from LOAD to INCHAN1(SCLK) rising. Hold time of LOAD after INCHAN1(SCLK) rising. Setup time from SERIAL rising to INCHAN1(SCLK) rising when entering serial mode or SERIAL falling to LOAD falling when entering parallel mode or SERIAL falling to LOAD rising when entering burst mode. Hold time from INCHAN1(SCLK) rising to SERIAL falling when exiting serial mode. Delay from INCHAN1(SCLK) rising to SDOUT, 20pF load. Pulse width (HIGH or LOW) on INIT. Setup time from ALE_SCN to INCHAN1(SCLK) rising when starting or completing a serial read-back sequence. Hold time of ALE_SCN after INCHAN1(SCLK) rising when starting or completing a serial read-back sequence. Min 3.35 1.45 6.75 0 0 6.75 1.65 1.0 15 1.85 0.95 0.90 Typ — — — — — — — — — — — — Max — — — — — — — — — — — — Units ns ns ns ns ns ns ns ns ns ns ns ns ThSERIAL TdSDOUT TPWINIT TsSCAN ThSCAN 0 — 6.75 1.65 1.0 — — — — — — 6.20 — — — ns ns ns ns ns G52351-0, Rev 3.0 02/12/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 5 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 36x37 Crosspoint Switch Preliminary Data Sheet VSC838 Figure 1: Parallel Mode -- Separate Address/Data (leave ALE_SCN pin HIGH) OUTCHAN[5:0] INCHAN[5:0] LOAD CS CONFIG SERIAL TsCS Output Addr Input Addr ThCS TsWR TPWLW TsSERIAL ThWR TPWCFG Figure 2: Parallel Mode -- Multiplexed Address/Data INCHAN[5:0] ALE_SCN LOAD CS CONFIG SERIAL Output Addr Input Addr ThCS TsWR TsCS TsSERIAL TPWLW ThWR TPWCFG Page 6 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52351-0, Rev 3.0 02/12/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC838 3.2Gb/s 36x37 Crosspoint Switch Figure 3: Serial Mode (leave ALE_SCN pin LOW during programming) INCHAN0_SDIN INCHAN1_SCLK Y5 Y4 Y3 Y2 low Y1 Y0 A5 A4 A3 A2 low A1 A0 TdSDOUT SDOUT LOAD CS CONFIG SERIAL TsSERIAL Y(n) = Output Address Bit (n); A(n) = Input Address Bit (n) Y5 Y4 Y3 Y2 TsSDIN ThSDIN TsCS TperSCLK TsLOAD ThLOAD TPWCFG ThCS Figure 4: Serial Read-Back ALE_SCN INCHAN1_SCLK SDOUT SERIAL TsSERIAL ThSCAN TsSCAN TdSDOUT TperSCLK 36 b5 36 b4 36 b3 36 b2 36 low 36 b1 36 b0 35 b5 35 b4 35 b3 35 b2 35 low 35 b1 35 b0 34 b5 MSB of Program memory for Activity Monitor Channel MSB of Program memory for 36th output channel Read-back shift register (483 bits long) is loaded here on rising edge of INCHAN1_SCLK with SERIAL HIGH and ALE_SCN LOW NOTE: The word pattern during serial read back will be four valid words followed by four ‘DON’T CARE’ words. G52351-0, Rev 3.0 02/12/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 7 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 36x37 Crosspoint Switch Preliminary Data Sheet VSC838 DC Characteristics All characteristics are over the specified operating conditions. Table 3: Power Supply Requirements Parameter ICC PT Description VCC supply current Total chip power (with ITERM = 0 and back-terminations ON, high drive) Min Typ 2,286 6 Max 3,428 9 Units mA W Conditions MAX PT is with +5% Supply, +85°C case temperature and high drive Table 4: Control Port Input Levels (LVTTL/CMOS) Parameter VIH VIL IIH IIL VOH VOL VOHPU VOLPU Description Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Output HIGH voltage Output LOW voltage VOH with external pull-up VOL with external pull-up Min 1.7 0 Typ Max VCC+1.0 Units V V mA mA V V V V Conditions 0.8 TBD TBD VCC-0.2 VCC 0.2 0.4 DC Load < 500µA DC Load < 2mA 250Ω to 3.3V(5%) 250Ω to 3.3V(5%) 0 2.4 Table 5: Signal Input Levels (high-speed signal path) Parameter VIN VICM Description Input voltage amplitude Input common-mode voltage Min 150 VCC-0.7 Typ Max 1100 VCC-0.2 Units mV V Conditions See Note 1 See Note 2 Table 6: Signal Output Levels (high-speed signal path), TERM_CTRL=ON, DRIVE_CTRL=HI Parameter VOUT VOCM Description Output differential voltage Output common-mode voltage Min 400 VCC-0.3 Typ Max 600 VCC-0.2 Units mV V Conditions See Note 1, 3 See Note 2, 3 NOTES: (1) Mean peak-to-peak amplitude measurement of either true or complement of the differential signal. (2) VCC = VCCP = 2.5V, VEE = 0V. (3) Terminated in 50Ω to VCC. This termination is used for testing the part, but other terminations are allowed—see Table 9. Page 8 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52351-0, Rev 3.0 02/12/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC838 I/O Equivalent Circuits ITC VCC 3.2Gb/s 36x37 Crosspoint Switch TERM_CTRL 50 PAD 50 PAD PAD 50 50 PAD DRIVE_CTRL H/S Input Equivalent Circuit H/S Output Equivalent Circuit Input Termination The high-speed inputs of the VSC838 are internally terminated by a 100Ω impedance between true and complement inputs. Termination resistors are isolated from each other on-chip. The termination will self-bias to +2.0V (nominal) for AC-coupled applications. The ITC pin enables direct interconnection of multiple VSC838 devices. With ITC tied to VCC, the center point of the 100Ω termination impedance is tied to VCC, causing the terminations to act as loads for an open-drain or open-collector differential output. Table 7: Allowed Input Termination Schemes Type 1 2 3 4 5 Description AC-coupled input DC-coupled from open-drain CML DC-coupled from back-terminated 2.5V CML DC-coupled from back-terminated 2.5V CML DC-coupled from back-terminated 3.3V LV-PECL Comments Tie ITC LOW, 100Ω differential input termination, input self-biased Tie ITC HIGH, terminations acts as 50Ω load to VCC Tie ITC HIGH, terminations acts as 50Ω load to VCC Tie ITC LOW, 100Ω differential termination (preferred over Type 3) Tie ITC LOW, 100Ω differential termination Some allowed termination schemes result in additional ICC current and power dissipation on-chip. See Table 8. Table 8: Additional Current and Power Parameter ICC-C PCC-C Description Additional ICC current when receiving DCCoupled CML (ITC = HIGH) Min Typ Max 180 0.180 Units mA W Conditions Additional power dissipated on-chip for DC terminating CML at inputs G52351-0, Rev 3.0 02/12/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 9 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 36x37 Crosspoint Switch Preliminary Data Sheet VSC838 Output Termination The high-speed outputs of the VSC838 are internally back terminated by 50 Ω t o V CC w hen the TERM_CTRL pin is HIGH. When this pin is LOW, the output driver functions as an open-drain CML driver. Setting DRIVE_CTRL LOW (GND) saves 1W under maximum power dissipation conditions. See Table 9 for allowable types of terminations and modes of operation. Table 9: Allowed High-Speed Output Terminations and Modes of Operation Type 1 2 3 4 5 6 7 8 Description AC-coupled to 50Ω termination to any voltage AC-coupled to 100Ω differential termination DC-coupled, terminated in 50Ω to VCC at far-end only DC-coupled, terminated in 50Ω to VCC at far-end only DC-coupled, source and far-end terminated in 50Ω to VCC DC-coupled, source and far-end terminated in 50Ω to VCC DC-coupled, 100Ω differential termination DC-coupled, 100Ω differential termination DRIVE_ CTRL VCC (HIGH) VCC (HIGH) GND (LOW) VCC (HIGH) GND (LOW) VCC (HIGH) GND (LOW) VCC (HIGH) TERM_ CTRL VCC (ON) VCC (ON) GND (OFF) GND (OFF) VCC (ON) VCC (ON) VCC (ON) VCC (ON) VOD(1) (mV) typ 500 500 500 1000 250 500 250 500 VOCM(1) (V) typ 2.0 2.0 2.25 2.0 2.375 2.25 2.25 2.0 NOTE: (1) Measured at output of VSC838, with VCC = 2.5V. Absolute Maximum Ratings(1) Power Supply Voltage (VCC) Potential to GND ..............................................................................-0.5V to +4.0V LVTTL Input Voltage Applied ................................................................................................-0.5V to VCC+1.0V ECL Input Voltage Applied ....................................................................................................-0.5V to VCC +0.5V Output Current (IOUT) .................................................................................................................................... 50mA Case Temperature Under Bias (TC) ............................................................................................. -55oC to + 125oC Storage Temperature (TSTG) ........................................................................................................ -65oC to + 150oC NOTE: (1) Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Operating Conditions Supply Voltage (VEE).......................................................................................................................................... 0V Supply Voltage (VCC) ............................................................................................................................+2.5V ±5% Supply Voltage (VCCP)...........................................................................................................................+2.5V ±5% Case Temperature Operating Range (T)..................................................... 0oC to 85oCPackage Pin Descriptions Page 10 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52351-0, Rev 3.0 02/12/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC838 Figure 5: Pinout Diagram -- Bottom View 29 A NC 3.2Gb/s 36x37 Crosspoint Switch 28 27 26 25 24 NC 23 22 NC 21 20 NC 19 18 NC 17 16 NC 15 14 NC 13 12 NC 11 10 NC 9 8 NC 7 6 5 4 3 2 1 Ball grid index A OUTCHAN4 2 NC NC NC 6 NC NC NC 10 NC NC NC 14 NC NC NC 18 NC NC NC 22 NC NC NC 26 NC NC NC 30 NC NC NC 34 OUTCHAN5 B NC NC B C NC NC C D NC D 0 NC 4 NC 8 NC 12 NC 16 NC 20 NC 24 NC 28 NC 32 NC ACTCHAN OUTCHAN2 OUTCHAN3 OUTCHAN1 OUTCHAN0 E CONFIG NC NC NC NC E F G F G H J K L M N P R T U V W Y AA AB AC AD AE AF Outputs [Yn, YNn] VCC Dedicated VEE Common VEE (always On) Control port Outputs [Yn, YNn] 0 NC NC NC NC NC NC NC NC NC LOAD NC 2 NC NC 1 3 Inputs [An, ANn] NC NC NC NC NC H J 4 NC NC 6 NC NC 5 NC NC NC 7 NC NC K L 10 11 8 NC NC 9 NC NC NC NC NC NC NC M N 15 12 NC NC 14 NC NC 13 NC NC NC NC NC P R 19 16 NC NC 18 NC NC 17 NC NC NC NC NC T U 20 NC NC 22 NC NC 21 NC NC NC 23 NC NC V W 27 24 NC NC 26 NC NC 25 NC NC NC NC NC Y AA 31 30 29 28 NC NC NC NC NC NC NC NC NC AB AC 34 33 35 32 INCHAN4 ITC Inputs [An, ANn] NC NC NC NC NC NC NC NC SERIAL ALE_SCN ACTCLK INCHAN1(SCLK) INCHAN0(SDIN) INCHAN5 ACTIVITY DRIVE_CTRL TERM_CTRL CMV AD AE AF 3 NC NC NC 7 NC NC NC 11 NC NC NC 15 NC NC NC 19 NC NC NC 23 NC NC NC 27 NC NC NC 31 NC NC NC 35 CS SDOUT AG INCHAN2 AG AH INCHAN3 AH 1 NC 5 NC 9 NC 13 NC 17 NC 21 NC 25 NC 29 NC 33 INIT AJ 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AJ G52351-0, Rev 3.0 02/12/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 11 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 36x37 Crosspoint Switch Table 10: Package Pin Indentifications Signal Name High-Speed Data Inputs A0, AN0 A1, AN1 A2, AN2 A3, AN3 A4, AN4 A5, AN5 A6, AN6 A7, AN7 A8, AN8 A9, AN9 A10, AN10 A11, AN11 A12, AN12 A13, AN13 A14, AN14 A15, AN15 A16, AN16 A17, AN17 A18, AN18 A19, AN19 A20, AN20 A21, AN21 A22, AN22 A23, AN23 A24, AN24 A25, AN25 A26, AN26 A27, AN27 A28, AN28 A29, AN29 A30, AN30 A31, AN31 A32, AN32 A33, AN33 A34, AN34 A35, AN35 D23, E23 AH23, AJ23 B23, A23 AF23, AE23 D21, E21 AH21, AJ21 B21, A21 AF21, AE21 D19, E19 AH19, AJ19 B19, A19 AF19, AE19 D17, E17 AH17, AJ17 B17, A17 AF17, AE17 D15, E15 AH15, AJ15 B15, A15 AF15, AE15 D13, E13 AH13, AJ13 B13, A13 AF13, AE13 D11, E11 AH11, AJ11 B11, A11 AF11, AE11 D9, E9 AH9, AJ9 B9, A9 AF9, AE9 D7, E7 AH7, AJ7 B7, A7 AF7, AE7 Preliminary Data Sheet VSC838 Ball Description Level High-Speed Data Input Channel 0; True, Complement High-Speed Data Input Channel 1; True, Complement High-Speed Data Input Channel 2; True, Complement High-Speed Data Input Channel 3; True, Complement High-Speed Data Input Channel 4; True, Complement High-Speed Data Input Channel 5; True, Complement High-Speed Data Input Channel 6; True, Complement High-Speed Data Input Channel 7; True, Complement High-Speed Data Input Channel 8; True, Complement High-Speed Data Input Channel 9; True, Complement High-Speed Data Input Channel 10; True, Complement High-Speed Data Input Channel 11; True, Complement High-Speed Data Input Channel 12; True, Complement High-Speed Data Input Channel 13; True, Complement High-Speed Data Input Channel 14; True, Complement High-Speed Data Input Channel 15; True, Complement High-Speed Data Input Channel 16; True, Complement High-Speed Data Input Channel 17; True, Complement High-Speed Data Input Channel 18; True, Complement High-Speed Data Input Channel 19; True, Complement High-Speed Data Input Channel 20; True, Complement High-Speed Data Input Channel 21; True, Complement High-Speed Data Input Channel 22; True, Complement High-Speed Data Input Channel 23; True, Complement High-Speed Data Input Channel 24; True, Complement High-Speed Data Input Channel 25; True, Complement High-Speed Data Input Channel 26; True, Complement High-Speed Data Input Channel 27; True, Complement High-Speed Data Input Channel 28; True, Complement High-Speed Data Input Channel 29; True, Complement High-Speed Data Input Channel 30; True, Complement High-Speed Data Input Channel 31; True, Complement High-Speed Data Input Channel 32; True, Complement High-Speed Data Input Channel 33; True, Complement High-Speed Data Input Channel 34; True, Complement High-Speed Data Input Channel 35; True, Complement PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL Page 12 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52351-0, Rev 3.0 02/12/01 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC838 Signal Name High-Speed Data Outputs Y0, YN0 Y1, YN1 Y2, YN2 Y3, YN3 Y4, YN4 Y5, YN5 Y6, YN6 Y7, YN7 Y8, YN8 Y9, YN9 Y10, YN10 Y11, YN11 Y12, YN12 Y13, YN13 Y14, YN14 Y15, YN15 Y16, YN16 Y17, YN17 Y18, YN18 Y19, YN19 Y20, YN20 Y21, YN21 Y22, YN22 Y23, YN23 Y24, YN24 Y25, YN25 Y26, YN26 Y27, YN27 Y28, YN28 Y29, YN29 Y30, YN30 Y31, YN31 Y32, YN32 Y33, YN33 Y34, YN34 Y35, YN35 G28, G29 G4, G5 G26, G25 G2, G1 J28, J29 J4, J5 J26, J25 J2, J1 L28, L29 L4, L5 L26, L25 L2, L1 N28, N29 N4, N5 N26, N25 N2, N1 R28, R29 R4, R5 R26, R25 R2, R1 U28, U29 U4, U5 U26, U25 U2, U1 W28, W29 W4, W5 W26, W25 W2, W1 AA28, AA29 AA4 , AA5 AA26, AA25 AA2, AA1 AC28, AC29 AC4, AC5 AC26, AC25 AC2, AC1 3.2Gb/s 36x37 Crosspoint Switch Description High-Speed Data Output Channel 0; True, Complement High-Speed Data Output Channel 1; True, Complement High-Speed Data Output Channel 2; True, Complement High-Speed Data Output Channel 3; True, Complement High-Speed Data Output Channel 4; True, Complement High-Speed Data Output Channel 5; True, Complement High-Speed Data Output Channel 6; True, Complement High-Speed Data Output Channel 7; True, Complement High-Speed Data Output Channel 8; True, Complement High-Speed Data Output Channel 9; True, Complement High-Speed Data Output Channel 10; True, Complement High-Speed Data Output Channel 11; True, Complement High-Speed Data Output Channel 12; True, Complement High-Speed Data Output Channel 13; True, Complement High-Speed Data Output Channel 14; True, Complement High-Speed Data Output Channel 15; True, Complement High-Speed Data Output Channel 16; True, Complement High-Speed Data Output Channel 17; True, Complement High-Speed Data Output Channel 18; True, Complement High-Speed Data Output Channel 19; True, Complement High-Speed Data Output Channel 20; True, Complement High-Speed Data Output Channel 21; True, Complement High-Speed Data Output Channel 22; True, Complement High-Speed Data Output Channel 23; True, Complement High-Speed Data Output Channel 24; True, Complement High-Speed Data Output Channel 25; True, Complement High-Speed Data Output Channel 26; True, Complement High-Speed Data Output Channel 27; True, Complement High-Speed Data Output Channel 28; True, Complement High-Speed Data Output Channel 29; True, Complement High-Speed Data Output Channel 30; True, Complement High-Speed Data Output Channel 31; True, Complement High-Speed Data Output Channel 32; True, Complement High-Speed Data Output Channel 33; True, Complement High-Speed Data Output Channel 34; True, Complement High-Speed Data Output Channel 35; True, Complement Ball Level CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML G52351-0, Rev 3.0 02/12/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 13 VITESSE SEMICONDUCTOR CORPORATION 3.2Gb/s 36x37 Crosspoint Switch Preliminary Data Sheet VSC838 Signal Name Control Pins ACTCLK ACTIVITY ALE_SCN Ball AD2 AD1 AD25 Description Clock for Activity Monitor (