VSC870

VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC870 Features • Performs 32-Bit Parallel to Serial and Serial to Parallel Functions • Serial Data Rates are 2.0Gb/s • Designed in Conjunction with the VSC880 Serial Crosspoint Switch • Performs Bit Alignment, Word Alignment and Cell Alignment • Three Modes of Operation: Distributed Control Packet Mode, Central Control Cell Mode and Direct Mode • Support for Multicast and Multiple Input Queues High Performance Serial Backplane Transceiver • Supports Priorities, Camp-on and Retransmission Capability in Packet Mode • Built-in Flow Control Channel in Packet Mode • Supports Cell Synchronization in Cell Mode • Interfaces Directly with Industry Standard FIFOs • Contains Redundant Serial I/Os and Internal Loopback Mode • 5V Tolerant TTL Inputs • Single 3.3V Power Supply • Available in 192 BGA Package VSC870 Block Diagram RFM RTM/TCLK REN WSIN WSOUT OOS RESYNEN RESET Retiming Register TXIN[31:0] TXTYP[1:0] TXEN RTR ABORT BYPASS WCLK TXOK RXOK SCRAM Transmit Control SCRAM Parallel to Serial TXCLK Generator TXSA+/TXSA- TXSB+/TXSBFACLPBK Alignment Word Gen Word/Cell Aligner CMU REFCLK DLYEN/CCKIN MODE[1] MODE[0] LOOPBACK RXSA+/RXSARXSB+/RXSBRXSEL TESTEN VSCTE RXCLK Generator Register Receive Control Retiming RXWA RXTYP[1:0] RXOUT[31:0] ACK/RCLK Serial to Parallel CRU DeSCRAM RXEN Signal Detect CELLSYN ALIVE LTIME G52190-0, Rev 4.1 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION High Performance Serial Backplane Transceiver Data Sheet VSC870 General Description The VSC870 serial backplane transceiver has been designed to operate with the VSC880 serial crosspoint switch to establish a synchronous high performance switching system. The VSC870 can also connect directly to another transceiver to act as a high bandwidth backplane interconnect link. The transmitter converts a 32-bit parallel interface operating at 62.5Mb/s to a 34-bit serial data stream operating a 2.125Gb/s. The receiver converts a 34-bit serial interface operating at 2.125Gb/s to a 32-bit parallel interface operating at 62.5Mb/s. The transceiver performs automatic bit alignment, word alignment and cell alignment to a connected switch chip or another transceiver. The parallel interface has been designed with industry-standard FIFOs in mind to provide such features as automatic packet retransmission, multicast with retransmission, camp-on and support for virtual output queues. These features can also be bypassed to give the user direct control of the serial data stream. In addition, the transceiver and switch chip can operate in a early arbitration mode that greatly improves bandwidth utilization. The transceiver also contains a built-in a flow control channel and redundant serial I/O buffers. The transceiver and switch chip have been optimized to be used in both distributed-controlled packet-based switching systems (Packet Mode), and centrally-controlled cell-based switching systems (Cell Mode). The transceiver can also be directly connected to another transceiver (Direct Mode) for backplane interconnect applications. The transceiver runs off a 3.3V power supply. The serial I/O buffers contain on-chip termination resistors (See Figure 19). Page 2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52190-0, Rev 4.1 01/05/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC870 Package Pin Descriptions Symbol TXIN[31:0] TXTYP[1:0] High Performance Serial Backplane Transceiver Name Transmit Parallel Data In Transmit Word Type I/O I I Freq Type 62.5Mb/s TTL 62.5Mb/s TTL 62.5Mb/s TTL Description 32-bit parallel data input for the transmit side. If BYPASS is LOW, these signals designate the transmit word type. If BYPASS is HIGH, these signals directly control the overhead bits sent on the serial channel. When TXEN is HIGH, TXIN[31:0], TXTYP[1:0] are loaded in to the transceiver on the next WCLK. When TXEN is LOW, the transceiver ignores TXIN[31:0] and TXTYP[1:0] and sends IDLE words at the serial output. When RTR is HIGH, the receiving side memory system is ready to receive data. If LOW, it sends a back pressure (flow control) signal to the source port card telling it to stop sending data. In Cell Mode, set RTR LOW to cell synchronize to the external cell clock. If RTR is HIGH, cell clock is recovered from the bit stream. In Packet Mode, when BYPASS is LOW, RTM/TCLK is set HIGH at the beginning of each data transmission and set LOW when the data packet has been successfully sent to all outputs. In Cell Mode, a HIGH pulse represents the transmit cell clock. When BYPASS is LOW, RFM is set HIGH whenever a retransmission of data is required due to contention for destination ports. This signal is LOW if MODE[1] is HIGH and the transceiver is word aligned on the transmit side. After initialization it will go HIGH for one word clock if there is a cell clock error. When REN is HIGH, the transceiver is ready to read data at TXIN[31:0] and TXTYP[1:0]. This signal can be forced low by the received flow control signal. These mode control pins are used to configure link synchronization. See Section 1.5. High speed serial differential transmit channel A High speed serial differential transmit channel B When LOOPBACK is HIGH, the CRU and signal detector select the serial data output channel as an input. High speed serial differential receive channel A High speed serial differential receive channel B TXEN Transmit Enable I RTR Ready To Receive I 62.5Mb/s TTL RTM/TCLK Retransmit Mode/ Transmit Cell Clock O 62.5Mb/s TTL RFM Read From Mark O 62.5Mb/s TTL