128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
128Mb SDRAM Specification
P2V28S20DTP-7,-75,-8 P2V28S30DTP-7,-75,-8 P2V28S40DTP-7,-75,-8
MIRA TECHNOLOGY INC.
8F., 68, SEC.3, NANKING E. RD. , TAIPEI, TAIWAN, R.O.C. TEL:886-2-25170055.25170066 FAX:886-2-25174575
JULY.2000
Rev.2.2
128Mb Synchronous DRAM
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 P2V28S30ATP-7,-75,-8 P2V28S40ATP-7,-75,-8
PRELIMINARY
(4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT)
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Some of contents are described for general products and are subject to change without notice.
DESCRIPTION
P2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and P2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and P2V28S40ATP is organized as 4-bank x 2,097, 152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. P2V28S20ATP,P2V28S30ATP and P2V28S40ATP achieve very high speed data rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems.
FEATURES
ITEM
tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3
-7
7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4ns 63ns 85mA 85mA 85mA 1mA
P2V28S20/30/40ATP -75 -8
10ns 7.5ns 45ns 20ns 6ns 5.4ns 67.5ns 85mA 85mA 85mA 1mA 10ns 8ns 48ns 20ns 6ns 6ns 70ns 85mA 85mA 85mA 1mA
Active to Precharge Command Period (Min.) (Min.) Row to Column Delay Access Time from CLK Ref /Active Command Period Operation Current (Single Bank) (Max.) (Min.) (Max.) V28S30D V28S40D -7,-75,-8
Icc6
Self Refresh Current
(Max.)
- Single 3.3V ±0.3V power supply - Max. Clock frequency -7:143MHz/-75:133MHz/-8:100MHz - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0,BA1(Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- DQML and DQMU (P2V28S40ATP) - Random column access - Auto precharge / All bank precharge controlled by A10 - Auto and self refresh - 4096 refresh cycles /64ms - LVTTL Interface - Package P2V28S20ATP/30ATP/40ATP 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
JULY.2000
Page-1
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
PIN CONFIGURATION (TOP VIEW)
P2V28S20ATP P2V28S30ATP P2V28S40ATP
PIN CONFIGURATION (TOP VIEW)
Vdd NC VddQ NC DQ0 VssQ NC NC VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss
400mil 54pin TSOP(II)
CLK CKE /CS /RAS /CAS /WE DQ0-15
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O
DQM A0-11 BA0,1 Vdd VddQ Vss VssQ
: Output Disable / Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output
JULY.2000
Page-2
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
BLOCK DIAGRAM
DQ0-7
I/O Buffer
Memory Array
4 096 x1024 x8 Cell Array
Memory Array
4096 x1024 x8 Cell Array
Memory Array
4096 x1024 x8 Cell Array
Memory Array
4096 x1024 x8 Cell Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode Register Control Circuitry
Address Buffer Clock Buffer
Control Signal Buffer
A0-11
BA0,1
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
Note:This figure shows the P2V28S30ATP The A2V28S20ATP configuration is 4096x2048x4 of cell array and DQ0-3 The A2V28S40ATP configuration is 4069x512x16 of cell array and DQ0-15
Type Designation Code
P2 V 28 S 3 0 A TP -8
Access Item -7 : 7 ns (143MHz/3-3-3) -75 : 7.5ns (100MHz/2-2-2 or 133MHz/3-3-3) -8 : 8 ns (100MHz/2-2-2 or 125MHz/3-3-3) TP : TSOP(II) A : 2nd generation 0 : Random Column 2 : x4, 3 : x8, 4: x16
Package Type Process Generation Function Organization Synchronous DRAM Density Interface PSC DRAM
128 :128Mbit V :LVTTL
JULY.2000
Page-3
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK Clock Enable: CKE controls internal clock.When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self-refresh. After self-refresh mode is started, CKE becomes asynchronous input. Self-refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A 0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified by A0-9,11(x4)/A0-9(x8)/A0-8(x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE , READ , WRITE commands.
C KE
Input
/CS /RAS, /CAS, /WE
Input Input
A0-11
Input
BA0,1 DQ0-3(x4), DQ0-7(x8), DQ0-15(x16) DQM(x4,x8), DQMU/L(x16) V dd, Vss VddQ, VssQ
Input
I nput / Output D ata In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable: When DQM(U/L) is high in burst write, Din for the current cycle is masked. When DQM(U/L) is high in burst read, Dout is disabled at the next but one cycle. P ower Supply for the memory array and peripheral circuitry.
Input
Power Supply
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
JULY.2000
Page-4
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
BASIC FUNCTIONS
The P2V28S20 , 30 and 40ATP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh opt ion, and precharge option, respectively . To know the detailed definition of commands, please see the command truth table.
CLK /CS /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Refresh Option @ refresh command Precharge Option @ precharge or read/write command
define basic command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
JULY.2000
Page-5
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Active Single Bank Precharge Precharge All Banks Column Address Entry &Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry
MNEMONIC DESEL NOP ACT PRE PREA WRITE WRITE A READ READA REFA REFS CKE n-1 H H H H H H H H H H H L CKE n X X X X X X X X X H L H H X X /CS H L L L L L L L L L L H L L L /RAS /CAS X H L L L H H H H L L X H H L X H H H H L L L L L L X H H L /WE BA0,1 A1 1 X H H L L L L H H H H X H L L X X V V X V V V V X X X X X L X X V X X V V V V X X X X X L A1 0 X X V L H L H L H X X X X X L A0-9 X X V X X V V V V X X X X X V*1
Self-Refresh Exit
REFSX L
Burst Terminate Mode Register Set
TBST MRS
H H
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address
JULY.2000
Page-6
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE Address IDLE
H L L L L L L L X H H H L L L L X H H H H L L L L X H H L H H L L X H H L L H H L L X H L X H L H L X H L H L H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
Command Action
DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS NOP NOP ILLEGAL*2 ILLEGAL*2 Bank Active, Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL*2 Precharge / Precharge All ILLEGAL ILLEGAL
ROW ACTIVE
H L L L L L L L L
JULY.2000
Page-7
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE (continued)
Current State READ /CS
H L L L L L L L L
/RAS /CAS /WE Address
X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
Command Action
DESEL NOP TBST READ /READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA,Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA,Begin Write, Determine Auto-Precharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst, Latch CA,Begin Terminate Burst, Latch CA,Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA,Begin Write, Determine Auto-Precharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL
WRIT E
H L L L L L L L L
JULY.2000
Page-8
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE (continued)
Current State READ with AUTO PRECHARGE /CS H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L /RAS /CAS /WE X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L Address X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / READA WRITE / WRITE A ACT PRE / PREA REFA MRS DESEL NOP TBST Action NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
READ / ILLEGAL READA WRITE / ILLEGAL WRITEA ACT PRE / PREA REFA MRS Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
JULY.2000
Page-9
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE (continued)
Current State PRE CHARGING /CS H L L L L L L L ROW ACTIVATING H L L L L L L L /RAS /CAS /WE X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H L X H L H L X H L X H L H L Address X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
JULY.2000
Page-10
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE (continued)
Current State WRITE RECOVERING /CS H L L L L L L L REFRESHING H L L L L L L L /RAS /CAS /WE X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H L X H L H L X H L X H L H L Address X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS Action NOP NOP ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
JULY.2000
Page-11
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE (continued)
Current State MODE REGISTER SETTING /CS H L L L L L L L /RAS /CAS /WE Address X H H H L L L L X H H L H H L L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS Action NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
JULY.2000
Page-12
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
FUNCTION TRUTH TABLE for CKE
Current State SELFREFRESH*1 CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L CKE n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Power Down) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Susspend at Next Cycle*3 Exit CLK Susspend at Next Cycle*3 Maintain CLK Suspend
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command.
JULY.2000
Page-13
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
REFS REFSX
MODE REGISTER SET
MRS
REFA
IDLE
AUTO REFRESH
CKEL
CLK SUSPEND
ACT CKEL CKEH
CKEH
POWER DOWN
ROW ACTIVE
TERM WRITE CKEL WRITEA READA READ WRITE
TERM READ CKEL
WRITE SUSPEND
WRITE
CKEH
READ
CKEH
READ SUSPEND
WRITEA WRITEA READA
READA
WRITEA SUSPEND
CKEL
CKEL
WRITEA
CKEH PRE
PRE PRE
READA
CKEH
READA SUSPEND
POWER APPLIED
POWER ON
PRE
PRE CHARGE Automatic Sequence Command Sequence
JULY.2000
Page-14
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
CLK /CS /RAS /CAS /WE BA0,1 A11-A0
V
BA0 BA1 A1 1 A1 0 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
LTMODE
BT
BL
BL 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0
BT= 0 1 2 4 8 R R R FP
BT= 1 1 2 4 8 R R R R
CL 000 001 LATENCY MODE 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1
/CAS LATENCY R R 2 3 R R R R R: Reserved for Future Use FP: Full Page
BURST LENGTH
101 110 111 BURST TYPE 0 1
SEQUENTIAL INTERLEAVED
JULY.2000
Page-15
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
CLK Command Address DQ CL= 3 BL= 4
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
/CAS Latency
Burst Length Burst Type
Burst Length
Initial Address A2 0 0 0 0 1 1 1 1 A1 A0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1
BL Sequential 0 1 2 3 8 4 5 6 7 0 1 4 2 3 0 2 1 1 2 3 4 5 6 7 0 1 2 3 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 3 4 5 6 7 0 1 2 3 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
0 1 0 1 0 1 0 1 0 1
JULY.2000
Page-16
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A0-11. The minimum activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed within tRC , although the number of banks which are active concurrently is not limited.
READ
After tRCD from the bank activation, a READ command can be issued. 1st output data is available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The start address is specified by A0-A9(x4), A0-8(X8), A0-7 (X16) , and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, TBST, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after READA. (Need to keep tRAS min.) The next ACT command can be issued after (BL + tRP) from the previous READA.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
2 ACT command / tRCmin tRCmin
Command A0-9 A10 A11 BA0,1 DQ
ACT tRRD Xa Xa Xa 00
ACT READ tRAS Y 0 Xb tRCD Xb Xb 01 00 Qa0
PRE tRP
ACT Xb
1
Xb Xb 01
Qa1
Qa2
Qa3
Precharge all
JULY.2000
Page-17
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Multi Bank Interleaving READ (BL=4, CL=3)
CLK Command A0-9 A10 A11 BA0,1 DQ
/CAS latency Burst Length ACT tRCD Xa Xa Xa 00 00 Y 0 Xb Xb Xb 10 Qa0 10 Qa1 00 Qa2 Qa3 Qb0 Qb1 Qb2 Y 0 0 READ ACT READ PRE
READ with Auto-Precharge (BL=4, CL=3)
CLK
BL + tRP
Command A0-9 A10 A11 BA0,1 DQ
ACT tRCD Xa Xa Xa 00
READ BL Y 1 tRP
ACT Xa Xa Xa
00 Qa0 Qa1 Qa2 Qa3
00
Internal precharge start
READ Auto-Precharge Timing (BL=4)
CLK Command CL=3 CL=2 DQ DQ
Qa0 AC T READ BL Qa0 Qa1 Qa2 Qa3
Qa1
Qa2
Qa3
Internal Precharge Start Timing
JULY.2000
Page-18
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A0-A9(x4), A0-8(X8), A0-7(X16) and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the autoprecharge (WRITEA) is performed. Any command (READ, WRITE, PRE, TBST, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. (Need to keep tRAS min.) The next ACT command can be issued after tRP from the internal precharge timing.
WRITE with Auto-Precharge (BL=4)
CLK Command A0-9 A10 A11 BA0,1 DQ
ACT tRCD Xa Xa Xa Xa Xa 00 00 Da0 Y 0 Xb Xb Xb 10 Da1 Da2 Da3 10 Db0 0 Write ACT tRCD Y 0 0 00 Db1 Db2 Db3 0 0 10 Write PRE PRE
Multi Bank Interleaving WRITE (BL=4)
CLK Command A0-9 A10 A11 BA0,1 DQ
ACT tRCD Xa Xa Xa 00 00 tWR Da0 Da1 Da2 Da3 Internal precharge starts Y 1 Write tRP Xa Xa Xa 00 ACT
JULY.2000
Page-19
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
BURST INTERRUPTION [ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed READ to READ interval is minimum 1 CLK..
Read Interrupted by Read (BL=4, CL=3)
CLK Command A0-9 A10 A11 BA0,1 DQ
00 00 10 Qai0 Qaj0 01 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3 READ READ Yi 0 Yj 0 READ Yk 0 0 READ Yl
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CLK Command A0-9 A10 A11 BA0,1 DQM Q D
Qai0 Daj0 Daj1 Daj2 Daj3 00 00 READ Yi 0 Write Yj 0
DQM control Write control
JULY.2000
Page-20
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=4.
Read Interrupted by Precharge (BL=4)
CLK
Command DQ Command
READ
PRE Q0 Q1 Q2
READ
PRE Q0 Q1
CL=3
DQ Command DQ
READ PRE
Q0
Command DQ Command
READ Q0
PRE Q1 Q2
READ
PRE Q0 Q1
CL=2
DQ Command DQ
READ PRE
Q0
JULY.2000
Page-21
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
[Read Interrupted by Burst Terminate]
rupt the burst read operation and disable the data output. The terminated bank remains active.
READ to TBST interval is minimum 1 CLK. A TBST command to
Similarly to the precharge, a burst terminate command can inter- output disable latency is equivalent to the /CAS Latency.
Read Interrupted by Terminate (BL=4)
CLK
Command DQ Command
READ
TBST Q0 Q1 Q2
READ
TBST Q0 Q1
CL=3
DQ Command DQ
READ TBST
Q0
Command DQ Command
READ Q0
TBST Q1 Q2
READ
TBST Q0 Q1
CL=2
DQ Command DQ
READ TBST
Q0
JULY.2000
Page-22
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (CL=3,BL=4)
CLK Command A0-9 A10 A11 BA0,1 DQ
00 Dai0 00 Daj0 Daj1 10 Dbk0 Dbk1 Dbk2 00 Dal0 Dal1 Dal2 Dal3 Write Write Yi 0 Yj 0 Write Yk 0 Write Yl 0
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (CL=3,BL=4)
CLK Command A0-9 A10 A11 BA0,1 DQM DQ
Dai0 Qaj0 Qaj1 Dbk0 Dbk1 Qal0 00 00 10 00 Write READ Yi 0 Yj 0 Write Yk 0 READ Yl 0
JULY.2000
Page-23
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank.Write recovery time(tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CLK Command ACT Write PRE
tRP
ACT
A0-9,11
Xa
Ya
Xa
A10
0
0
0
0
BA0-1 DQM
00
00
00
00
tWR
DQ
Da 0
Da 1
[Write Interrupted by Burst Terminate]
Burst terminate command can terminate burst write operation.In this case, the write recovery time is not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write Interrupted by Terminate (BL=4)
CLK Command ACT Write TBST Write
A0-9,11
Xa
Ya
Yb
A10
0
0
0
BA0-1
00
00
00
DQ
Da 0
Da 1
Db 0
Db 1
Db 2
Db 3
JULY.2000
Page-24
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
[Write with Auto-Precharge Interrupted by Write or Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after tRP. Auto-precharge interruption by a command to the same bank is inhibited.
Write Interrupted by WRITE to another bank (BL=4)
CLK Command Write Write
BL tRP
ACT
A0-9,11
Ya
Yb
tWR
Xa
A10
1
0
Xa
BA0-1
00
10
00
DQ
Da 0
Da 1
Db 0
Db 1
Db 2
Db 3 activate
auto-precharge
interrupted
Write Interrupted by READ to another bank (CL=2,BL=4)
CLK Command Write Read
BL tRP
ACT
A0-9,11
Ya
Yb
tWR
Xa
A10
1
0
Xa
BA0-1
00
10
00
DQ
Da 0
Da 1 interrupted
Qb0
Qb1
Qb2
Qb3 activate
auto-precharge
JULY.2000
Page-25
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
[Read with Auto-Precharge Interrupted by Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after tRP. Auto-precharge interruption by a command to the same bank is inhibited.
Read Interrupted by Read to another bank (CL=2,BL=4)
CLK Command Read Read
BL tRP
ACT
A0-9,11
Ya
Yb
Xa
A10
1
0
Xa
BA0-1
00
10
00
DQ
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
auto-precharge
interrupted
activate
[Full Page Burst]
Full page burst length is available for only the sequential burst type. Full page burst read or write is repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read or write with auto-precharge command is illegal.
[Single Write]
When single write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0).
JULY.2000
Page-26
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= / CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64M bit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be supplied to the device before tRC from the REFA command.
Auto-Refresh
CLK /CS NOP or DESELECT /RAS /CAS /WE CKE A0-11 BA0,1 m inimum tRFC
Auto Refresh on All Banks
Auto Refresh on All Banks
JULY.2000
Page-27
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the selfrefresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input ,all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRC from the 1st CLK egde following CKE=H, all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK
/CS /RAS /CAS /WE CKE
NOP
new command
A0-11 BA0,1
X 00
Self Refresh Entry
Self Refresh Exit
minimum tRFC for recovery
JULY.2000
Page-28
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.
ext.CLK tIH CKE tIS tIH tIS
int.CLK
Power Down by CKE
CLK CKE Command
PRE NOP NOP NOP Standby Power Down
CKE Command
ACT NOP NOP NOP
Active Power Down
DQ Suspend by CKE (CL=2)
CLK CKE Command
Write Read
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
JULY.2000
Page-29
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
DQM CONTROL
DQM is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM(U,L) masks input data word by word. DQM(U,L) to write mask latency is 0. During reads, DQM(U,L) forces output to Hi-Z word by word. DQM(U,L) to output Hi-Z latency is 2.
DQM Function(CL=3)
CLK Command DQM
Write READ
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQM(U,L)=H
disabled by DQM(U,L)=H
JULY.2000
Page-30
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd VddQ VI VO IO Pd Topr Tstg
Parameter
Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature
Conditions
with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ
Ratings
-0.5 - 4.6 -0.5 - 4.6 -0.5 - 4.6 -0.5 - 4.6 50
Unit
V V V V mA mW ˚C ˚C
Ta = 25˚C
1000 0 - 70 -65 - 150
RECOMMENDED OPERATING CONDITIONS
(Ta=0 - 70 ˚C ,unless otherwise noted)
Symbol
Vdd Vss VddQ VssQ VIH*1 VIL*2
Parameter
Supply Voltage Supply Voltage Supply Voltage for output Supply Voltage for output High-Level Input Voltage all inputs Low-level Input Voltage all inputs
Limits
Min.
3.0 0 3.0 0 2.0 -0.3
Typ.
3.3 0 3.3 0
Max.
3.6
Unit
V V
3.6 0 VddQ +0.3 0.8
V V V V
NOTES: 1. VIH(max)=5.5V for pulse width less than 10ns. 2. VIL(min)=-1.0V for pulse width less than 10ns.
CAPACITANCE
(Ta=0 -70˚C,Vdd=VddQ=3.3± 0 . 3 V , V s s = V s s Q = 0 V , u n l e s s o t h e r w i s e n o t e d )
Limits (max.) -75/-8 5.0 5.0 4.0 6.5
Symbol
CI(A) CI(C) CI(K) CI/O
Parameter
Input Capacitance, address pin Input Capacitance, contorl pin Input Capacitance, CLK pin Input Capacitance, I/O pin
Test Condition
Limits (min.) 2.5 2.5 2.5 4.0
-7 3.8 3.8
Unit pF pF pF pF
@ 1MHz 1.4V bias 200mV swing Vcc=3.3V
3.5 6.5
JULY.2000
Page-31
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Organization Limits (max.) -7 -75 -8
ITEM
Symbol
Unit
Operating current Precharge Standby current in Non-Power down mode
Icc1
tRC=min, tCLK=min BL=1,IOL=0mA CKE=VILmax tCLK=15ns CKE=VIHmin CLK=VILmax(fixed) CKE=VIHmin tCLK=15ns(Note) CKE=VIHmin tCLK=VILmax(fixed) CKE=/CS=VIHmin tCLK=15ns(Note) CKE=VIHmin tCLK=VILmax(fixed)
All Bank Active tCLK = min BL=4, CL=3, IOL=0mA
x4/x8/x16
100
95
85
mA
Icc2N
x4/x8/x16
20
20
20
mA
Icc2NS
x4/x8/x16
15
15
15
mA
Precharge Standby current in Power down mode
Icc2P
x4/x8/x16
2
2
2
mA
Icc2PS
x4/x8/x16
1
1
1
mA
Icc3N
x4/x8/x16
30
30
30
Active Standby current
Icc3NS
mA
x4/x8/x16
25 140
25 130
25 120 mA
Burst current Auto-refresh current Self-refresh current
Icc4
x4/x8/x16
Icc5 Icc6
tRC=min, tCLK=min CKE < 0.2V x4/x8/x16
x4/x8/x16 7,7.5,8
130 1
130 1
130 1
mA mA
NOTE: 1. Icc(max) is specified at the output open condition. 2. Input signals are changed one time during 30ns.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Symbol
Parameter High-Level Output Voltage (DC) Low-level Output Voltage (DC) Off-state Output Current Input Current
Test Conditions Min.
Limits Max.
unit V 0.4 V µA µA
VOH (DC) VOL (DC) IOZ II
IOH=-2mA IOL= 2mA Q floating VO=0 -- VddQ VIH = 0 -- VddQ +0.3V
2.4
-5 -5
5 5
JULY.2000
Page-32
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
AC TIMING REQUIREMENTS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Input Pulse Levels:0.8V-2.0V Input Timing Measurement Level:1.4V
Limits Symbol
tCLK
Parameter
Min. CLK cycle time
CL=2 CL=3 7 2.5 2.5 1 1.5 0.8 63 70 20 45 20 14 14 14
-7 Max. Min.
10 7.5 2.5 2.5 10 1 1.3 0.8 67.5 75 20 100K 45 20 15 15 15 64
-75 Max. Min.
10 8 3 3 10 1 2 0.8
-8 Max.
Unit
ns ns ns ns 10 ns ns ns ns ns ns 100K ns ns ns ns ns 64 ms
tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tRSC tREF
CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time Input Hold time Row Cycle time Refresh Cycle Time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Delay time Mode Register Set Cycle time Refresh Interval time
(all inputs) (all inputs)
07 80 20 100K 48 20 20 20 20 64
CLK
1.4V
DQ
1.4V
Any AC timing is referenced to the input signal passing through 1.4V.
JULY.2000
Page-33
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
SWITCHING CHARACTERISTICS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Limits S ymbol Parameter Min. CL=2 tAC Access time from CLK CL=3 tOH Output Hold time from CLK Delay time , output lowimpedance from CLK Delay time , output highimpedance from CLK CL=2 CL=3 2.7 0 2.7 5.4 5.4 3 3 0 3 5.4 -7 Max. Min. -7.5 Max. 6 5.4 3 3 0 3 6 Min. -8 Max. 6 6 ns ns ns ns ns ns *1 Unit Note
tOLZ tOHZ
NOTE: 1. If clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter.
Output Load Condition
VOUT 50pF DQ 1.4V CLK 1.4V
Output Timing Measurement Reference Point
CLK tOLZ DQ
1.4V
1.4V
tAC
tOH
tOHZ
JULY.2000
Page-34
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Burst Write (single bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRAS tRP
/RAS
t RCD tRCD
/CAS
tWR tWR
/WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y
X
X
X
X
0
0
0
0
0
0
D0
D0
D0
D0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT # 0
WRITE#0
PRE#0
Italic parameter indicates minimum case
JULY.2000
Page-35
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC tRC
/CS
tRAS tRRD tRP
/RAS
tRCD tRCD tRCD
/CAS
tWR tWR
/WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y X Y X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
0
1
0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
ACT#0 WRITE#0 ACT#1
PRE#0
ACT# 0
WRITE#0 ACT#1
PRE#0
WRITEA#1 (Auto-Precharge)
Italic parameter indicates minimum case
JULY.2000
Page-36
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Burst Read (single bank) @BL=4 CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRAS tRP tRAS
/RAS
tRCD tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y
X
X
X
X
0
0
0
0
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
ACT#0
READ# 0
PRE#0
ACT# 0
READ# 0
PRE#0
Italic parameter indicates minimum case
JULY.2000
Page-37
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Burst Read (multiple bank) @BL=4 CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC tRC
/CS
tRRD tRAS
/RAS
tRCD tRCD tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y X Y X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
0
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT#0 READA# 0 ACT#1 READA# 1
ACT# 0
READ# 0 ACT# 1
PRE#0
Italic parameter indicates minimum case
JULY.2000
Page-38
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
W rite Interrupted by Write @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK /CS
tRRD
/RAS
tRCD
/CAS
tWR
/WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y Y Y X
X
X
X
X
X
X
0
0
1
0
1
0
0
1
D0
D0
D0
D0
D0
D1
D1
D1
D0
D0
D0
D0
ACT#0 WRITE# 0 ACT#1
WRITE# 0 WRITEA# 1 interrupt interrupt other same bank bank
WRITE# 0 interrupt other bank
PRE#0 ACT# 1
Italic parameter indicates minimum case
JULY.2000
Page-39
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Read Interrupted by Read @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK /CS
tRRD
/RAS
tRCD tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y Y Y X
X
X
X
X
X
X
0
0
1
1
1
0
1
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT#0 READ#0 ACT#1
READ#1 interrupt other bank
READA# 1 interrupt same bank
READ# 0 interrupt other bank
ACT# 1
Italic parameter indicates minimum case
JULY.2000
Page-40
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Write Interrupted by Read, Read Interrupted by Write @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK /CS
tRRD
/RAS
tRCD tRCD
/CAS
tWR
/WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X X Y Y Y
X
X
X
X
0
1
0
1
1
1
D0
D0
Q1
Q1
D1
D1
D1
D1
ACT#0
WRITE# 0 ACT#1
READ#1
WRITE# 1
PRE#1
Italic parameter indicates minimum case
JULY.2000
Page-41
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Write/Read Terminated by Precharge @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRP tRAS tRP
/RAS
tRCD tRCD
/CAS
tWR
/WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y X
X
X
X
X
X
X
0
0
0
0
0
0
0
D0
D0
Q0
Q0
ACT#0
WRITE# 0
PRE#0 ACT#0 Te rminate
READ# 0
PRE#0 ACT#0 Te rminate
Italic parameter indicates minimum case
JULY.2000
Page-42
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Write/Read Terminated by Burst Terminate @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK /CS /RAS
tRCD
/CAS
tWR
/WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y Y Y
X
X
0
0
0
0
0
D0
D0
Q0
Q0
D0
D0
D0
D0
ACT#0
WRITE# 0 TERM READ# 0 TERM
WRITE#0
PRE#0
Italic parameter indicates minimum case
JULY.2000
Page-43
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Single Write Burst Read @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y Y
X
X
0
0
0
D0
Q0
Q0
Q0
Q0
ACT#0 WRITE# 0
READ# 0
Italic parameter indicates minimum case
JULY.2000
Page-44
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Power-Up Sequesce and Intialize
CLK
200µs
/CS
tRP tRFC tRFC tRSC
/RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
NOP Power On PRE ALL REFA REFA REFA MRS ACT# 0
MA
X
0
X
0
X
0
0
Minimum 8 REFA cycles
Italic parameter indicates minimum case
JULY.2000
Page-45
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Auto Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y
X
X
0
0
D0
D0
D0
D0
PRE ALL
REFA
ACT#0
WRITE#0
All bank m ust be idle before REFA is issued. s
Italic parameter indicates minimum case
JULY.2000
Page-46
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Self Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS /CAS /WE CKE DQM A0-8, A10 A9,11 BA0,1 DQ
X
X
X
0
PRE ALL Self Refres h Entry All bank m ust be idle before REFS is issued. s
Self Refres h Exit
ACT#0
Italic parameter indicates minimum case
JULY.2000
Page-47
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
CLK Suspension @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y Y
X
X
0
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0 WRITE# 0 internal CLK suspended
READ# 0
internal CLK suspended
Italic parameter indicates minimum case
JULY.2000
Page-48
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Power Down
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK /CS /RAS /CAS /WE
Standby Power Down Active Power Down
CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X
X
X
0
PRE ALL
ACT# 0
JULY.2000
Page-49
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
DQM Write Mask @BL=4
JULY.2000
Page-50
Rev.2.2
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