VG26S17400FJ-5

VIS Description or 3.3V only power supply. Low voltage operation is more suitable to be used on battery VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM The device is CMOS Dynamic RAM organized as 4,194,304 words x 4 bits. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only backup, portable electronic application. A new refresh feature called “ self-refresh “ is supported and very slow CBR cycles are being performed. It is packaged in JEDEC standard 26/24 - pin plastic SOJ or TSOP (II). Features • Single 5V ( ± 10 %) or 3.3V (+10%,-5%) only power supply • High speed tRAC access time : 50/60 ns • Low power dissipation - Active mode : 5V version 605/550 mW (Max.) 3.3V version 396/360 mW (Max.) - Standby mode : 5V version 1.375 mW (Max.) 3.3V version 0.54 mW (Max.) • Fast Page Mode access • I/O level : TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V) • 2048 refresh cycles in 32 ms (Std) or 128ms (S - version) • 4 refresh mode : - RAS only refresh - CAS-before-RAS refresh - Hidden refresh - Self - refresh (S - version) Document : Rev. Page 1 VIS Pin configuration 26/24 - PIN 300mil Plastic SOJ VSS DQ4 DQ3 CAS OE A9 VCC DQ1 DQ2 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VG26(V) (S)17400EJ A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS Pin Description Pin Name A0 - A10 Function Address inputs - Row address - Column address - Refresh address Data - in/data - out Row address strobe Column address strobe Write enable Output enable Power (+ 5V or + 3.3V) Ground A0 - A10 A0 - A10 A0 - A10 DQ1 ~ DQ4 RAS CAS WE OE Vcc Vss Document : Rev. Page 2 VIS Block Diagram WE CAS CONTROL LOGIC VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM DATA - IN BUFFER DQ1 DQ4 NO. 2 CLOCK GENERATOR DATA - OUT BUFFER COLUMNADDRESS BUFFERS (11) A0 A1 A2 A3 A4 A5 A6 A7 ROW DECODER COLUMN DECODER REFRESH CONTROLLER 2048 SENSE AMPLIFIERS I/O GATING REFRESH COUNTER 2048 x 4 ROW ADDRESS BUFFERS (11) 2048 A8 A9 A10 2048 x 2048 x 4 MEMORY ARRAY RAS NO. 1 CLOCK GENERATOR Vcc Vss Document : Rev. Page 3 VIS Truth Table ADDRESSES FUNCTION STANDBY READ WRITE : (EARLY WRITE) READ WRITE PAGE MODE READ 1st Cycle 2st Cycle RAS H L L L L L L L L L L→H→L L→H→L VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM CAS H→X WE X H L H→L OE X L X L→H L L X X L→H L→H ROW X ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW ROW ROW X COL X High - Z DQS Notes L L L H→L H→L H→L H→L H→L H→L COL Data - Out COL Data - In COL Data - Out, Data - In COL Data - Out COL Data - Out COL Data - In COL Data - In COL Data - Out, Data - In COL Data - Out, Data - In COL Data - Out COL Data - In n/a X High - Z High - Z 1 H H L L H→L H→L PAGE 1st Cycle MODE WRITE 2st Cycle PAGE - MODE 1st Cycle READ - WRITE 2st Cycle HIDDEN REFRESH READ WRITE L L H L H L X H L X X X RAS - ONLY REFRESH CBR REFRESH Notes : 1. EARLY WRITE only. L H→L Document : Rev. Page 4 VIS Absolute Maximum Rating Parameter Voltage on any pin relative to Vss Supply voltage relative to Vss Short circuit output current Power dissipation Operating temperature Storage temperature 5V 3.3V 5V 3.3V Symbol VT Vcc IOUT PD TOPT TSTG Value -1.0 to + 7.0 -0.5 to + 4.6 -1.0 to + 7.0 -0.5 to + 4.6 50 1.0 0 to + 70 -55 to + 125 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM Unit V V mA W °C °C Recommended DC Operating Conditions Parameter/Condition Supply Voltage Input High Voltage, all inputs Input Low Voltage, all inputs Symbol Vcc VIH VIL Min 4.5 2.4 -1.0 5 Volt Version Typ Max 5.0 5.5 VCC + 1.0 0.8 3.3 Volt Version Min Typ Max 3.15 3.3 3.6 2.0 -0.3 VCC + 0.3 0.8 Unit V V V Capacitance Ta = 25°C, VCC = 5V ± 10% or 3.3V(+10%,-5%), f = 1MHz Parameter Input capacitance (Address) Input capacitance (RAS , CAS, OE, WE) Symbol Cl1 Cl2 Typ Max 5 7 Unit pF pF pF Note 1 1 1,2 Output capacitance CI/O 7 (Data - in, Data - out) Note : 1. Capacitance measured with effective capacitance measuring method. 2. CAS = VIH to disable Dout. Document : Rev. Page 5 VIS DC Characteristics; 5 - Volt verion (Ta= 0 to 70°C, VCC = + 5V±10%, Vss = 0V) VG26 (V) (S) 17400E Parameter Operating current Low power S - version Symbol Test Conditions RAS cycling CAS cycling tRC = min. TTL interface RAS, CAS = VIH Dout = high - Z CMOS interface RAS, CAS Standby Standard Current power version ICC2 -5 Min Max 145 2 Min -6 Max VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM Unit Notes ICC1 135 mA 2 mA 1, 2 - 0.25 - 0.25 mA ≥ V CC - 0.2V 2 2 Dout = high - Z TTL interface RAS, CAS = VIH Dout = high - Z CMOS interface RAS, CAS RAS - only refresh current Fast page mode current CAS - before - RAS refresh current Self - refresh currant (S - Version) CAS - before - RAS long refresh current (S - Version) ICC3 ICC4 tPC = min. ICC5 ICC8 ICC9 tRC = min. RAS, CAS cycling tRASS ≥ 100µ S Standby : VCC - 0.2V ≤ RAS CAS before RAS refresh : 2048 cycles/128ms RAS, RAS : 0V ≤ V IL ≤ 0.2V VCC - 0.2V ≤ V IH ≤ V IH (Max) Dout = high - Z, tRAS ≤ 300ns 145 350 500 135 mA 350 µ A 500 µ A mA 1 1 mA ≥ V CC - 0.2V 145 100 135 Dout = high - Z RAS cycling, CAS = VIH tRC = min. 1, 2 mA 90 mA 1, 2 1,3 Document : Rev. Page 6 VIS DC Characteristics ; 5 - Volt Version (cont.) (Ta = 0 to 70°C, VCC = + 5V ± 10%, Vss = 0V) Parameter lnput leakage current Output leakage current Symbol ILI ILO Test Conditions 0V ≤ Vin ≤ V CC + 0.5V 0V ≤ Vout ≤ VC C + 0.5V Dout = Disable VG26 (V) (S) 17400E -5 -6 Min Max Min Max -5 -5 5 5 -5 -5 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM Unit Notes 5 µA 5 µA Output high VOH lOH = -5mA 2.4 - 2.4 -V voltage Output low VOL lOL = + 4.2mA 0.4 0.4 V voltage Notes : 1. lCC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. lCC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For lCC4, address can be changed once or less within one Fast page mode cycle time. Document : Rev. Page 7 VIS DC Characteristics ; 3.3 - Volt Verion (Ta = 0 to 70°C, VCC = + 3.3V(+10%,-5%), Vss = 0V) VG26 (V) (S) 17400E Parameter Symbol Test Conditions Min Operating current Low power S - version ICC1 RAS cycling CAS cycling tRC = min. LVTTL interface RAS , CAS = VIH Dout = high - Z CMOS interface RAS, CAS ≥ VCC - 0.2V Dout = high - Z Standby Standard Current power version ICC2 LVTTL interface RAS, CAS = VIH Dout = high - Z CMOS interface RAS, CAS ≥ VCC - 0.2V Dout = high - Z RAS - only refresh current Fast page mode current CAS - before - RAS refresh current Self - refresh currant (S - Version) CAS - before - RAS long refresh current (S - Version) ICC3 ICC4 tPC = min. ICC5 ICC8 ICC9 tRC = min. RAS, CAS cycling t RASS ≥ 100µ S Standby : VCC - 0.2V ≤ RAS CAS before RAS refresh : 2048 cycles/128ms RAS, RAS : 0V ≤ V I L ≤ 0.2V VCC - 0.2V ≤ V IH ≤ V IH (Max) Dout = high - Z, t RAS ≤ 300ns 145 250 300 135 RAS cycling, CAS = VIH tRC = min. 145 100 135 2 2 -5 Max 145 0.5 Min -6 Max VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM Unit Notes 135 mA 0.5 mA 1, 2 - 0.15 - 0.15 mA mA 0.5 0.5 mA 1, 2 mA 90 mA 1, 2 mA 250 µ A 300 µ A 1,3 Document : Rev. Page 8 VIS DC Characteristics ; 3.3 - Volt Version (cont.) (Ta = 0 to 70°C, VCC = + 3.3V(+10%,-5%), VSS= 0V) Parameter Input leakage current Output leakage current Symbol ILI ILO Test Conditions 0V ≤ Vin ≤ V CC + 0.3V 0V ≤ Vout ≤ VC C + 0.3V Dout = Disable lOH = -2mA VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM VG26 (V) (S) 17400E Unit Notes -5 -6 Min Max Min Max -5 5 -5 5 µA -5 5 -5 5 µA Output high VOH 2.4 - 2.4 -V voltage Output low VOL lOL = + 2mA 0.4 0.4 V voltage Notes : 1. lCC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. lCC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For lCC4, address can be changed once or less within one Fast page mode cycle time. Document : Rev. Page 9 VIS AC Characteristics (Ta = 0 to + 70°C, VCC = 5V ± 10% or 3.3V ± 10%, V SS = 0V) * 1, * 2, * 3, * 4 Test conditions • Output load : two TTL Loads and 50pF(VCC = 5.0V ± 10%) one TTL Load and 30pF(V CC = 3.3V(+10%,-5%) • Input timing reference levels : VIH = 2.4V, VlL = 0.8V (VCC = 5.0V ± 10%); V IH = 2.0V, VlL = 0.8V (VCC=3.3V(+10%,-5%)) • Output timing reference levels : VOH = 2.0V, VOL = 0.8V (VCC = 5V ± 10%, 3.3V(+10%,-5%)) VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM Read, Write, Read - Modify - Write and Refresh Cycles (Common Parameters) VG26 (V) (S) 17400E -5 Parameter Random read or write cycle time RAS precharge time CAS precharge time in normal mode RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time Column address to RAS lead time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time Transition time (rise and fall) Refresh period Refresh period (S - Version) CAS to output in Low-Z CAS delay time from Din OE delay time from Din Symbol tRC tRP tCPN tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRAL tRSH tCSH tCRP tOED tT tREF tREF tCLZ tDZC tDZO Min 84 30 10 50 8 0 8 0 8 12 10 25 8 38 5 12 1 0 0 0 Max 10000 10000 37 25 50 32 128 Min 104 40 10 60 10 0 10 0 10 14 12 30 10 60 5 15 1 0 0 0 -6 Max 10000 10000 45 30 50 32 128 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns 11 10 8 9 7 5 6 Notes Document : Rev. Page 10 VIS Read Cycle VG26 (V) (S) 17400E -5 Parameter Access time from RAS Access time from CAS Access time from column address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Output buffer turn-off time Output buffer turn-off time from OE Write Cycle Symbol tRAC tCAC tAA tOEA tRCS tRCH tRRH tOFF tOEZ Min 0 0 10 0 0 Max 50 13 25 12 12 12 Min 0 0 10 0 0 -6 Max 60 15 30 15 15 15 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM Unit ns ns ns ns ns ns ns ns ns Notes 12 13,14 14,15 7 10,16 16 17 17 VG26 (V) (S) 17400E -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time -6 Max Min 0 10 10 15 10 0 10 Max - Symbol tWCS tWCH tWP tRWL tCWL tDS tDH Min 0 8 8 13 8 0 8 Unit ns ns ns ns ns ns ns Notes 7,18 19 19 Read - Modigy - Write Cycle VG26 (V) (S) 17400E -5 Parameter Read - modify - write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol tRWC tRWD tCWD tAWD tOEH Min 108 64 26 39 8 Max Min 133 77 32 47 10 -6 Max Unit ns ns ns ns ns 18 18 18 Notes Document : Rev. Page 11 VIS Refresh Cycle VG26 (V) (S) 17400E -5 Parameter CAS setup time (CBR refresh) CAS hold time (CBR refresh) RAS precharge to CAS hold time RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (CBR self refresh) WE setup time WE hold time Fast Page Mode Cycle Symbol tCSR tCHR tRPC tRASS tRPS tCHS tWSR tWHR Min 5 8 5 100 90 -50 0 10 Max Min 10 10 5 100 110 -50 0 10 -6 Max - VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM Unit ns ns ns µs ns ns ns ns Notes 10 7 VG26 (V) (S) 17400E -5 Parameter Fast page mode cycle time Fast page mode CAS Precharge time Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge -6 Max 105 30 Min 25 10 60 Symbol tPC tCP tRASP tCPA tCPRH Min 20 10 50 30 Max 105 35 - Unit ns ns ns ns ns Notes 20 10,14 35 Fast Page Mode Read Modify Write Cycle VG26 (V) (S) 17400E -5 Parameter Fast page mode read - modify - write cycle CAS precharge to WE delay time Fast page mode read - modify - write cycle time Symbol tCPW tPRWC Min 45 56 Max Min 55 68 -6 Max Unit ns ns Notes 11 Document : Rev. Page 12 VIS Notes : 1. AC measurements assume tT = 5ns. used, a minimum of eight CAS-before-RAS refresh cycles are required. VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM 2. An initial pause of 100 µ s is required after power up, and it followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. All the V CC and V SS pins shall be supplied with the same voltage. 5. tRAS(min) = t RWD(min) + tRWL (min) + tT in read - modify-write cycle. 6. tCAS(min) = t CWD(min) + tCWL (min) + tT in read - modify-write cycle. 7. tASC(min), tRCS(min), tWCS(min) and tRPC are determined by the falling edge of CAS. 8. t RCD(max) is specified as a reference point only, and tRAC (max) can be met with the tRCD(max) limit. Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified t RCD(max) limit. 9. t RAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit. Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 10. tCRP, tCHR , tRCH, tCPA and tCPW are determined by the rising edge of CAS . 11. V IH(min) and V IL(max) are reference levels for measuring timing or input signals. Therefore, transition time is measured between VIH and VIL. 12. Assumes that t RCD ≤ ≥ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 13. Assumes that tRCD tRCD(max) and tRAD ≤ ≥ tRAD(max). 14. Access time is determined by the maximum among tAA, tCAC, tCPA. 15. Assumes that tRCD ≤ tRCD(max) and tRAD tRAD(max). 16. Either t RCH or tRRH must be satisfied for a read cycle. 17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition ( high impedance). 18. tWCS, tRWD , tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and the data output will remain open circuit (high impedance) throughout the entire cycle. If t RWD ≥ tRWD(min), tCWD ≥ tCWD(min), t AWD ≥ tAWD(min), and tCPW ≥ tCPW(min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate. 19. These parameters are referenced to CAS in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 20. tRASP defines RAS pulse width in Fast page mode cycles. Document : Rev. Page 13 VIS Timing Waveforms • Read Cycle t RC t RAS t RP VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS t CRP t CSH t RCD t T t RSH t CAS t CPN CAS t RAD t RAL t ASR t RAH t ASC t CAH ADDRESS Row Column t RRH t RCS t RCH WE OE t OEA t CAC t AA t RAC t OEZ t OFF DQ1 ~ DQ4 t CLZ DOUT Note : = don’t care = Invalid Dout Document : Rev. Page 14 VIS •Early Write Cycle t RC t RAS t RP VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS t CSH t RCD t T t RSH t CRP t CPN t CAS CAS t RAD t ASR t RAH Row t ASC t CAH t RAL ADDRESS Column t RAL t WCS t WCH WE t DS t DH DQ1 ~ DQ4 DIN Document : Rev. Page 15 VIS • Delayed Write Cycle t RC t RAS t RP VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS t CSH t RCD t T t RSH t CAS t CRP t CPN CAS t ASR t RAH t ASC t CAH ADDRESS Row Column t CWL t RCS t RWL t WP WE t OED t OEH OE t DS t DS t DH DQ1 ~ DQ4 OPEN DIN Document : Rev. Page 16 VIS • Read - Modify - Write Cycle t RWC t RAS t RP VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS t T t RCD t CAS t CRP t CPN CAS t RAD t ASR t RAH t ASC t CAH ADDRESS Row Column t RCS t CWD t AWD t RWD t CWL t RWL t WP WE t DZC t DS t DH DQ1 ~ DQ4 OPEN DIN t DZO t OED t OEH OE t OEA t CAC t AA t OEZ t RAC DQ1 ~ DQ4 DOUT Document : Rev. Page 17 VIS • Fast Page Mode Read Cycle t RASP t CPRH VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM t RP RAS t CRP t CSH t CRP t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CPN CAS t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t RAL t CAH ADDRESS Row Column 1 Column 2 Column N Row t RCS t RRH t RCH WE WE t OEA t OEA t OEA OE OE t RAC t AA t CPA t AA t OEZ t OFF t CAC t CLZ t OFF t CLZ t CAC t OFF t CPA t AA t OEZ t CAC t CLZ t OEZ DQ1 ~ DQ4 DOUT 1 DOUT 2 DOUT N OPEN Document : Rev. Page 18 VIS • Fast Page Mode Early Write Cycle t RASP VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM t RP RAS tT t CSH t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t CPN CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ADDRESS Row Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE WE t DS t DH t DS t DH t DS t DH DQ1 ~ DQ4 DIN 1 DIN 2 DIN N Document : Rev. Page 19 VIS • Fast Page Mode Delayed Write Cycle t RASP VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM tCPRH t RP RAS t T t RCD t CP t CAS t PC t CAS t CP t RSH t CAS t CSH t CRP CAS t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ADDRESS Row Column 1 Column 1 t CWL Column 2 t CWL t RCS Column N t CWL t RWL t RCS t RCS WE WE t WP t DS t DZC t DH t DZC t WP t DS t DH t WP t DZC t DS t DH OPEN DQ1 ~ DQ4 t DZO OPEN DIN 1 t DZO OPEN DIN 2 t DZO DIN N t OED t OEH t OED t OEH t OED t OEH OE Document : Rev. Page 20 VIS • Fast Page Mode Read - Modify - Write Cycle t RASP VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM tCPRH t RP RAS t T t RCD t CAS t CP t PRWC t CAS t CP t CAS t CRP CAS t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ADDRESS Row Column 1 Column 1 t RWD t AWD t CWD t CWL Column 2 t CPW t AWD t CWD t CWL Column N t CWL t CPW t AWD t CWD t RWL t RCS t RCS WE WE t RCS t DZC t WP t DS t DH t DZC t WP t DS t DH t DZC t WP t DS t DH DQ1 ~ DQ4 OPEN DIN 1 OPEN DIN 2 DIN N t DZO t OED t OEA t CPA t OEH t DZO t OED t OEH t DZO t CPA t OED t OEA t OEH t OEA OE t AA t RAC t CLZ t OEZ t CLZ t OEZ t CLZ t CAC t CAC t AA t OEA t CAC t AA t OEZ DQ1 ~ DQ4 DOUT 1 DOUT 2 DOUT N Document : Rev. Page 21 VIS RAS - Only Refresh Cycle t RC t RAS t RP VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS tT t CRP tRPC tCRP CAS tASR tRAH ADDRESS Row tOFF OPEN DQ1 ~ DQ4 CAS - Before - RAS Refresh Cycle tRC tRP tRAS tRP t RAS tRC t RP RAS tRPC tT t CSR t CHR tRPC tCSR t CHR tCRP CAS tWSR tWHR tWSR tWHR WE tOFF OPEN DQ1 ~ DQ4 Document : Rev. Page 22 VIS CBR Self - Refesh Cycle ( S - Version Only ) t RASS t RPS VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS t RPC tCSR tCHS CAS tOFF High lmpedance DQ1 - DQ4 tWSR tWHR WE OPEN Document : Rev. Page 23 VIS • Hidden Refresh Cycle t RC tRAS (READ) VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM t RC t RP tRAS (REFRESH) t RC t RP tRAS (REFRESH) t RP RAS tT t CHR t RSH t RCD tCAS tCRP CAS t RAD t ASR t RAH tASC t RAL tCAH ADDRESS Row Column tRRH t RCS tRCH WE OE t OEA t CAC t AA t RAC t OEZ t OFF DQ1 ~ DQ4 D OUT Document : Rev. Page 24 VIS Ordering information Part Number VG26 (V) (S) 17400FJ - 5 VG26 (V) (S) 17400FJ - 6 VG26(V)(S)17400FJ 4,194,304 x 4 - Bit CMOS Dynamic RAM Access Time 50 ns 60 ns Package 300mil 26/24 - Pin Plastic SOJ VG26 (V) (S) 17400FJ - 5 • VG • 26 •V •S • 17400 •F •J •5 • VIS Memory Product • Technology • 3.3V version • Self refresh • Device Type and Configuration • Revision • Package Type (J : SOJ , T : TSOJ II) • Speed (5 : 50 ns, 6 : 60 ns) Packaging information • 300 mil, 26/24-Pin Plastic SOJ D DIM A A1 A2 b b1 b2 c c1 D E E1 E2 e R1 INCHES MILLIMETERS NOM. MAX. MIN. NOM. MAX. MIN. 3.25 3.51 3.76 0.128 0.138 0.148 ----2.08 ----0.082 2.54 REF. 0.100 REF. 0.41 0.41 0.66 0.18 0.18 17.02 --0.46 --0.51 0.48 0.81 0.016 0.016 0.026 0.007 0.007 0.670 --0.018 --0.020 0.019 0.032 1 6 8 13 b 26 21 19 14 b1 c1 c E1 E BASE METAL WITH PLATING --0.30 --0.28 17.15 17.27 8.51 BASIC 7.49 7.62 7.75 6.78 BASIC 1.27 BASIC 0.76 --1.02 --0.012 0.011 --0.675 0.680 0.335 BASIC 0.295 0.300 0.305 0.267 BASIC 0.050 BASIC 0.030 --0.040 SECTION B-B C L A2 0.025" MIN. A A1 B B E2 NOTE: 1. CONTROLLING DIMENSION : INCHES 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15mm) PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25mm) PER SIDE. 3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127mm) DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH TO LESS THAN 0.001"(0.025mm) BELOW b2 MIN. e b2 b 0.007" M 4-e 0.004" RAD R1 SEATING PLANE Document : Rev. Page 25