VG26V18165CJ-6

VIS Description VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM The device CMOS Dynamic RAM organized as 1,048,576 words x 16 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. A new refresh feature called “self-refresh” is supported and very slow CBR cycles are being performed. lt is packaged in JEDEC standard 42-pin plastic SOJ. Features • Single 5V( ± 10 %) or 3.3V( ± 10 %) only power supply • High speed tRAC acess time: 50/60ns • Low power dissipation - Active wode : 5V version 660/605 mW (Mas) 3.3V version 432/396 mW (Mas) - Standby mode: 5V version 1.375 mW (Mas) 3.3V version 0.54 mW (Mas) • Extended - data - out(EDO) page mode access • I/O level: TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V) • 1024 refresh cycle in 16 ms(Std.) or 128 ms(S-version) • 4 refresh modes: - RAS only refresh - CAS - before - RAS refresh - Hidden refresh - Self-refresh(S-version) Document:1G5-0147 Rev.1 Page 1 VIS Pin Configuration 42-Pin 400mil Plastic SOJ VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 NC NC WE RAS NC NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS VG26(V)(S)18165CJ 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin Description Pin Name A0-A9 Function Address inputs - Row address - Column address - Refresh address Data-in / data-out Row address strobe Column address strobe Write enable Output enable Power (+5 V or + 3.3V) Ground A0-A9 A0-A9 A0-A9 DQ1~DQ16 RAS UCAS, LCAS WE OE Vcc Vss Document:1G5-0147 Rev.1 Page 2 VIS VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM Block Diagram WE LCAS UCAS CAS CONTROL LOGIC DATA - IN BUFFER DQ1 . . DQ16 NO.2 CLOCK GENERATOR DATA - OUT BUFFER OE COLUMNADDRESS BUFFERS (10) A0 A1 A2 A3 A4 A5 A6 A7 ROW DECODER COLUMN DECODER REFRESH CONTROLLER 1024 SENSE AMPLIFIERS I/0 GATING REFRESH COUNTER 1024x16 A8 A9 ROW ADDRESS BUFFERS (10) 1024 x 1024 x 16 MEMORY ARRAY 1024 RAS NO.1 CLOCK GENERATOR Vcc Vss Document:1G5-0147 Rev.1 Page 3 VIS TRUTH TABLE ADDRESSES FUNCTION RAS STANDBY READ : WORD READ : LOWER BYTE H L L LCAS H→X L L UCAS H→X L H WE X H H OE X L L ROW X ROW ROW COL X COL COL VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM DQS High-Z Data-Out Lower Byte: Data-Out Upper Byte: High-Z Lower Byte: High-Z Upper Byte: Data-Out Data-In Notes READ: UPPER BYTE L H L H L ROW COL WRITE: WORD (EARLY WRITE) WRITE: LOWER BYTE (EARLY) WRITE : UPPER BYTE (EARLY) READ WRITE PAGE-MODE READ 1st Cycle 2nd Cycle PAGE-MODE WRITE 1st Cycle 2nd Cycle PAGE-MODE READWRITE HIDDEN REFRESH 1st Cycle 2nd Cycle READ WRITE RAS-ONLY REFRESH CBR REFRESH L L L L X ROW COL L L H L X ROW COL Lower Byte: Data-In Upper Byte: High-Z Lower Byte: High-Z Upper Byte: Data-In Data-Out, Data-In Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z 4 1,2 2 2 1 1 1,2 1,2 2 1,3 L H L L X ROW COL L L L L L L L L→H→L L→H→L L H→L L H→L H→L H→L H→L H→L H→L L L H L L H→L H→L H→L H→L H→L H→L L L H L H→L H H L L H→L H→L H L X H L→H L L X X L→H L→H L X X X ROW ROW n/a ROW n/a ROW n/a ROW ROW ROW X COL COL COL COL COL COL COL COL COL n/a X Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active (LCAS or UCAS ). Document:1G5-0147 Rev.1 Page 4 VIS Absolute Maximum Ratings VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM Parameter 5V Voltage on any pin relative to Vss 3.3V 5V Supply voltage relative to Vss 3.3V Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT Value -1.0 to + 7.0 -0.5 to + 4.6 -1.0 to + 7.0 Unit V V VCC -0.5 to + 4.6 IOUT PD TOPT TSTG 50 1.0 0 to + 70 -55 to + 125 mA W ¢J ¢J Recommended DC Operating Conditions Parameter/Condition Symbol Min 5 Volt Version Typ 5.0 Max 5.5 Min 3.3 Volt Version Typ 3.3 Max 3.6 Unit Supply Voltage Input High Voltage, all inputs Input Low Voltage, all inputs VCC VIH VIL 4.5 2.4 -1.0 3.0 2.0 -0.3 V V V - VCC + 1.0 0.8 - VCC + 0.3 0.8 Capacitance Ta = 25°C, VCC = 5V ± 10 % or 3.3V ± 10 %, f = 1MHz Parameter Input capacitance (Address) Input capacitance (RAS , LCAS , UCAS, OE, WE) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ - Max 5 7 7 Unit pF pF pF Note 1 1 1, 2 Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, LCAS and UCAS = VIH to disable Dout. Document:1G5-0147 Rev.1 Page 5 VIS DC Characteristics; 5- Volt Verion (Ta = 0 to + 70 °C, VCC= + 5V ± 10 %,VSS = 0V) Parameter Symbol Test Conditions -5 Min Operating current ICC1 RAS cycling LCAS / UCAS cycling tRC = min TTL interface RAS, LCAS / UCAS = VIH Dout = High-Z CMOS interface Standby Current ICC2 Standard power version RAS, CAS ≥ Vcc -0.2V Dout = High-Z TTL interface RAS,LCAS / UCAS = VIH Dout = High-Z CMOS interface RAS, CAS ≥ Vcc -0.2V Dout = High-Z RAS-only refresh current ICC3 RAS cycling, LCAS / UCAS = VIH tRC = min tRC = min tRC = min RAS, LCAS / UCAS cycling tRAS ≥ 100 µ s Standby: VCC- 0.2V ≤ RAS CAS before RAS refresh: 2048 cycles / 128ms RAS,LCAS / UCAS: 0V ≤ V IL ≤ 0.2V VCC- 0.2V ≤ V IH ≤ V IH (Max) Dout = High-Z, t RAS ≤ 300ns 120 2 Max 120 Min -6 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VG26(V)(S)18165C Unit Notes Max 110 mA 1, 2 Low power S-version - 2 - 2 mA - 0.25 - 0.25 mA 2 mA 1 - 1 mA 110 mA 1, 2 EDO page mode current CAS-before-RAS refresh current Self-refresh current (S - Version) CAS- before- RAS long refresh current (S-Version) ICC4 ICC5 ICC8 ICC9 - 90 120 350 500 - 80 110 350 500 mA mA µA µA 1, 3 1, 2 Document:1G5-0147 Rev.1 Page 6 VIS DC Characteristics ; 5-Volt Version (Cont.) (Ta = 0 to + 70°C, VCC = + 5V ± 10 %,VSS = 0V) VG26(V)(S)18165C -5 Parameter Input leakage current Output leakage current Symbol ILI ILO VOH VOL Test Conditions 0V ≤ V I N ≤ V C C + 0.5V 0V ≤ V OUT ≤ V CC + 0.5V Dout = Disable Output high Voltage Output low voltage IOH = - 5mA IOL = + 4.2mA 2.4 0.4 2.4 Min -5 -5 Max 5 5 Min -5 -5 -6 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM Max 5 5 Unit µA µA V V Notes 0.4 Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For ICC4, address can be changed once or less within one EDO page mode cycle time. Document:1G5-0147 Rev.1 Page 7 VIS DC Characteristics ; 3.3 - Volt Version (Ta = 0 to 70°C , VCC = + 3.3V ± 10 %, VSS = 0V) VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM Parameter Symbol Test Conditions VG26(V)(S)18165C -5 Min Max 120 Min -6 Max 110 Unit Notes Operating current ICC1 RAS cycling LCAS / UCAS cycling tRC = min LVTTL interface RAS, LCAS / UCAS = VIH Dout = High-Z CMOS interface RAS, CAS ≥ V C C -0.2V Dout = High-Z - mA 1, 2 Low power S-version ICC2 - 0.5 - 0.5 mA - 0.15 - 0.15 mA Standby Current Standard power version LVTTL interface RAS, LCAS / UCAS = VIH Dout = High-Z CMOS interface RAS, CAS ≥ V C C -0.2V Dout = High-Z - 2 - 2 mA - 0.5 - 0.5 mA RAS- only refresh current ICC3 RAS cycling LCAS / UCAS = VIH tRC = min tPC = min tRC = min RAS, LCAS / UCAS cycling t RASS ≥ 100 µ s Standby: VCC- 0.2V ≤ RAS CAS before RAS refresh: 2048 cycles / 128ms RAS, LCAS / UCAS : 0V ≤ V IL ≤ 0.2V VCC- 0.2V ≤ V IH ≤ V IH (max) Dout = High-Z, tRAS ≤ 300ns - 120 - 110 mA 1, 2 EDO page mode current CAS- before- RAS refresh current Self- refresh current (S-Version) CAS- before- RAS long refresh current (S-Version) ICC4 ICC5 ICC8 ICC9 - 90 120 250 300 - 80 110 250 300 mA mA µA µA 1, 3 1, 2 Document:1G5-0147 Rev.1 Page 8 VIS DC Characteristics ; 3.3 - Volt Version (Cont.) (Ta = 0 to 70°C, VCC= +3.3V ± 10 %, VSS= 0V) VG26(V)(S)18165C -5 Parameter Input leakage current Output leakage current Symbol ILI ILO VOH VOL Test Conditions 0V ≤ Vin ≤ V C C + 0.3V 0V ≤ Vout ≤ V CC + 0.3V Dout = Disable Output high Voltage Output low voltage IOH = -2mA IOL = +2mA 2.4 0.4 2.4 Min -5 -5 Max 5 5 Min -5 -5 -6 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM Unit Max 5 5 µA µA V V Notes 0.4 Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For I CC4, address can be changed once or less within one EDO page mode cycle time. Document:1G5-0147 Rev.1 Page 9 VIS AC Characteristics (Ta = 0 to + 70°C, Vcc = 5V ± 10 % or 3.3V ± 10 %, Vss = 0V) *1, *2, *3, *4, *5 VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM Test conditions • Output load: two TTL Loads and 50pF (VCC = 5.0V ± 10 %) one TTL Load and 50pF (VCC = 3.3V ± 10 %) • Input timing reference levels: VIH = 2.4V, VIL = 0.8V (VCC = 5.0V ± 10 %); VIH = 2.0V, VIL = 0.8V (VCC = 3.3V ± 10 %) • Output timing reference levels: VOH = 2.0V, VOL = 0.8V (VCC = 5V ± 10 %, 3.3V ± 10 %) Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters) VG26(V)(S) 18165C -5 Parameter Random read or write cycle time RAS precharge time LCAS / UCAS precharge time in normal mode RAS pulse width LCAS / UCAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to LCAS / UCAS delay time RAS to column address delay time Column address to RAS lead time RAS hold time LCAS / UCAS hold time LCAS / UCAS to RAS precharge time OE to Din delay time Transition time (rise and fall) Refresh period Refresh period (S- Version) LCAS / UCAS to output in Low- Z LCAS / UCAS delay time from Din OE delay time from Din Document:1G5-0147 Unit Notes -6 Max Min 104 40 10 Max ns ns ns Symbol tRC tRP tCPN tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRAL tRSH tCSH tCRP tOED tT tREF tREF tCLZ tDZC tDZO Min 84 30 10 50 8 0 8 0 8 12 10 25 8 38 5 12 1 0 0 0 Rev.1 10000 10000 37 25 50 16 128 - 60 10 0 10 0 10 14 12 30 10 40 5 15 1 0 0 0 10000 10000 45 30 50 16 128 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns 6 7 8 9 10 11 12 Page 10 VIS Read Cycle VG26(V)(S)18165C -5 Parameter Access time from RAS Access time from LCAS / UCAS Access time from column address Access time from OE Read command setup time Read command hold time to LCAS / UCAS Read command hold time to RAS Output buffer turn-off time Output buffer turn-off time from OE Symbol tRAC tCAC tAA tOEA tRCS tRCH tRRH tOFF tOEZ Min 0 0 10 0 0 Max 50 13 25 12 12 12 Min 0 0 10 0 0 -6 Max VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM Unit Notes 60 15 30 15 15 15 ns ns ns ns ns ns ns ns ns 13 14, 15 15, 16 8 11, 17 17 18 18 Write Cycle VG26(V)(S)18165C -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to LCAS / UCAS lead time Data-in setup time Data-in hold time WE to Data-in delay Symbol tWCS tWCH tWP tRWL tCWL tDS tDH tWED Min 0 8 8 13 8 0 8 10 Max Min 0 10 10 15 10 0 10 10 -6 Max ns ns ns ns ns ns ns ns 20 21 21 8, 19 Unit Notes Read- Modify- Write Cycle VG26(V)(S) 18165C -5 Parameter Read-modify- write cycle time RAS to WE delay time LCAS / UCAS to WE dealy time Column address to WE delay time OE hold time from WE Symbol tRWC tRWD tCWD tAWD tOEH Min 108 64 26 39 8 Max Min 133 77 32 47 10 -6 Max ns ns ns ns ns 19 19 19 Unit Notes Document:1G5-0147 Rev.1 Page 11 VIS Refresh Cycle VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VG26(V)(S)18165C -5 Parameter LCAS / UCAS setup time (CBR refresh) LCAS / UCAS hold time (CBR refresh) RAS precharge to CAS hold time RAS pulse width (self refresh) RAS precharge time (self refresh) LCAS / UCAS hold time (CBR self refresh) WE setup time WE hold time tWSR tWHR 0 10 0 10 ns ns Symbol tCSR tCHR tRPC tRASS tRPS tCHS Min 5 8 5 100 90 -50 Max Min 5 10 5 100 110 -50 -6 Max Unit ns ns ns µs ns ns 11 8 Notes EDO Page Mode Cycle VG26(V)(S)18165C -5 Parameter EDO page mode cycle time EDO page mode LCAS / UCAS precharge time EDO page mode RAS pulse width Access time from LCAS / UCAS precharge RAS hold time from LCAS / UCAS precharge OE high hold time from LCAS / UCAS high OE high pulse width Data output hold time after LCAS / UCAS low Output disable delay from WE WE pulse width for output disable when LCAS / UCAS high Symbol tPC tCP tRASP tCPA tCPRH tOEHC tOEP tCOH tWHZ tWPZ Min 20 10 50 30 5 10 5 3 7 Max 105 30 10 Min 25 10 60 35 5 10 5 3 7 -6 Max 105 35 10 Unit ns ns ns ns ns ns ns ns ns ns 22 11, 15 Notes Document:1G5-0147 Rev.1 Page 12 VIS EDO Page Mode Read Modify Write Cycle VG26(V)(S)18165C -5 Parameter EDO page mode read- modify- write cycle LCAS / UCAS precharge to WE delay time EDO page mode read- modify- write cycle time Symbol tCPW tPRWC Min 45 56 Max Min 55 68 -6 Max - VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM Unit ns ns Notes 11 Document:1G5-0147 Rev.1 Page 13 VIS Notes : 1. AC measurements assume t T = 2ns. VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM 2. An initial pause of 100 µ s is required after power up, and it followed by a minimum of eight initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required. 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. All the VCC and VSS pins shall be supplied with the same voltages. 5. When both LCAS and UCAS go low at the same time, all 16-bits data are witten into the device. LCAS and UCAS cannot be staggered within the same write/read cycles. 6. tRAS(min) = tRWD(min)+t RWL(min)+tT in read-modify-write cycle. 7. tCAS (min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle. 8. tASC(min), tRCS (min), tWCS(min), and tRPC are determined by the falling edge of CAS . 9. t RCD(max) is specified as a reference point only, and tRAC (max) can be met with the tRCD(max) limit. Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit. 10. t RAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit. Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 11. tCRP, tCHR , tRCH, tCPA and tCPW are determined by the rising edge of CAS . 12. V IH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition time is measured between VIH and VIL. 13. Assumes that t RCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If t RCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 14. Assumes that tRCD ≥ t RCD (max) and tRAD ≤ t RAD (max). ≥ tRAD (max). 15. Access time is determined by the maximum of tAA , tCAC, tCPA. 16. Assumes that t RCD ≤ tRCD (max) and t RAD 17. Either tRCH or tRRH must be satisfied for a read cycle. 18. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high impedance). t OFF is determined by the later rising edge of RAS or CAS. 19. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ t WCS (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tRWD tCWD ≥ tRWD (min), ≥ t CWD (min), t AWD ≥ t AWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate. 20. tCWL shall be satisfied by both LCAS and UCAS. 21. These parameters are referenced to LCAS or LCAS separately in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 22. tRASP defines RAS pulse width in EDO page mode cycles. Document:1G5-0147 Rev.1 Page 14 VIS Timing Waveforms • Word Read Cycle VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RC t RAS t RP RAS t CRP t CSH t RCD t T t RSH t CAS t CPN UCAS LCAS t RAD t RAL t ASR t RAH t ASC t CAH ADDRESS Row Column t RRH t RCS t RCH WE OE t OEA t CAC t AA t RAC t OEZ t OFF DQ1~DQ16 t CLZ DOUT Document:1G5-0147 Rev.1 Page 15 VIS • Byte Read Cycle t RC t RAS t RP VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM RAS t CSH t RCD t T t RSH t CAS t CRP UCAS (or LCAS) LCAS (or UCAS) t RAD t ASR t RAH Row t ASC Column t RAL t CAH ADDRESS tRRH t RCS t RCH WE OE t OEA t CAC t AA t RAC t OEZ t OFF DQ9~DQ16 (or DQ1~DQ8) DOUT t CLZ DQ1~DQ8 (or DQ9~DQ16) High-Z Document:1G5-0147 Rev.1 Page 16 VIS • Word Early Write Cycle VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RC t RAS t RP RAS t CSH t RCD t T t RSH t CAS t CRP UCAS LCAS t RAD t RAL t ASR t RAH Row t ASC t CAH Column ADDRESS t WCS t WCH WE t DS t DH DQ1~DQ16 DIN Document:1G5-0147 Rev.1 Page 17 VIS • Byte Early Write Cycle VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RC t RAS t RP RAS t CSH t RCD t T t RSH t CAS t CRP LCAS (or UCAS) LCAS (or UCAS) t RAD t ASR t RAH Row t ASC t RAL t CAH Column ADDRESS t WCS t WCH WE t DS t DH DQ9~DQ16 DIN DQ1~DQ8 Document:1G5-0147 Rev.1 Page 18 VIS • Word Delayed Write Cycle t RC t RAS t RP VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM RAS t CSH t RCD t T t RSH t CAS t CRP t CPN UCAS LCAS t ASR t RAH t ASC t CAH ADDRESS Row Column t CWL t RWL t RCS t WP WE t OED t OEH OE t DS t DH DQ1~DQ16 OPEN DIN Document:1G5-0147 Rev.1 Page 19 VIS • Byte Delayed Write Cycle t RC t RAS t RP VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM RAS t CSH t RCD t T t RSH t CAS t CRP LCAS (or UCAS) LCAS (or UCAS) t ASR t RAH t ASC t CAH ADDRESS Row Column tCWL t RCS t RWL t WP WE t OEH tOED OE t DS t DH DQ9~DQ16 (or DQ1~DQ8) OPEN DIN DQ1~DQ8 (or DQ9~DQ16) Document:1G5-0147 Rev.1 Page 20 VIS • Word Read-Modify-Write Cycle t RWC t RAS VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RP RAS t T t RCD t CAS t CRP t CPN UCAS LCAS t RAD t ASR t ASC t CAH t RAH ADDRESS Row Column t CWD t AWD t RWD t RCS t CWL t RWL t WP WE t DS t DH DQ1~DQ16 OPEN D in t OED t OEH OE t OEA t CAC t AA t RAC t OEZ DQ1~DQ16 DOUT Document:1G5-0147 Rev.1 Page 21 VIS • EDO Page Mode Word Read-Modify-Write Cycle t RASP tCPRH VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RP RAS t T t RCD t CAS t CP t PRWC t CAS t CP t CAS t CRP UCAS LCAS t RAD t ASR t RAH t ASC t CAH t ASC t CAH t RAL t ASC t CAH ADDRESS Row Column 1 Column 1 t RWD t AWD t CWD t CWL Column 2 t CPW t AWD t CWD t CWL Column N t t CWL CPW t AWD t CWD t RWL t RCS WE WE t RCS tWP tDS t DH t WP t DS t DH tWP tDS t DH OPEN DQ1~DQ16 OPEN Din 1 OPEN Din 2 Din N t DZO t OED t OEH t OED t OEH t OED t OEH OE t OEA t CAC t RAC t AA tOEZ t CAC t AA t CPA t OEZ t OEA t CAC t AA t CPA t OEZ t OEA DQ1~DQ16 DOUT 1 DOUT 2 DOUT N Document:1G5-0147 Rev.1 Page 22 VIS • EDO Page Mode Word Read-Early-Write Cycle t RASP t CPRH VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RP RAS t CRP t CSH t CRP t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CPN UCAS LCAS t CSH t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAL t RAL t CAH ADDRESS Row Column 1 Column 2 Column N Row t RCS t RCH t WCS t WCH WE WE tOEA t WED OE OE tRAC t AA tCAC t CPA tAA tCAC tCOH OPEN Data Output 1 Data Output 2 Data Intput N tWHZ t DH tDS DQ1~DQ16 Document:1G5-0147 Rev.1 Page 23 VIS • Read Cycle with WE Controlled Disable RAS VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t CSH t RCD t T t CAS UCAS LCAS t RAD t ASR t RAH t ASC t CAH ADDRESS Row Column t RCS t RCH t WPZ WE t WHZ t OED OE t DS tOEA tCAC tAA tRAC tOEZ DQ1~DQ16 tCLZ DOUT Document:1G5-0147 Rev.1 Page 24 VIS RAS - Only Refresh Cycle t RC t RAS tRP VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM RAS tT t CRP tRPC tCRP UCAS LCAS tASR tRAH ADDRESS Row tOFF OPEN DQ1~DQ16 CAS-Before-RAS Refresh Cycle tRC tRP tRC tRP t RAS t RP RAS tRAS tT tRPC t CSR t CHR tRPC tCSR tCHR tCRP UCAS LCAS tWSR tWHR tWSR tWHR WE tOFF OPEN DQ1~DQ16 Document:1G5-0147 Rev.1 Page 25 VIS • Hidden Refresh Cycle tRC tRAS (READ) VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM tRC tRP tRAS (REFRESH) tRC tRP tRAS (REFRESH) tRP RAS tT t CHR t RSH tRCD tCAS tCRP UCAS LCAS t RAD t ASR t RAH tASC t RAL tCAH ADDRESS Row Column tRRH t RCS tRCH WE OE tORD t OEA t CAC t AA t RAC t OEZ t OFF t OFF DQ1~DQ16 D OUT Document:1G5-0147 Rev.1 Page 26 VIS Ordering information Part Number VG26(V)(S)18165CJ-5 VG26(V)(S)18165CJ-6 Access time 50 ns 60 ns Package 400mil 42-Pin Plastic SOJ VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VG26(V)(S)18165CJ-5 • VG • 26 •V •S • 18165 •C • VIS Memory Product • Technology • 3.3V Version • Self refresh • Device Type and Configuation • Revision • Package Type (J : SOJ, T : TSOP II) • Speed (5 : 50 ns, 6 : 60 ns) •J •5 Document:1G5-0147 Rev.1 Page 27