VG3617801BT-10

VIS Description VG3617801CT 16Mb CMOS Synchronous Dynamic RAM The VG3617801CT is CMOS Synchronous Dynamic RAMs organized as 1,048,576-word X 8-bit X 2bank. It is fabricated with an advanced submicron CMOS technology and is designed to operate from a single 3.3V power supply. This is packaged using JEDEC standard pinouts and standard plastic TSOP. Features • Single 3.3V( ± 0.3V ) power supply • Clock Frequency:100MHz • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) • Programmable wrap sequence (Sequential/Interleave) • Automatic precharge and controlled precharge • Auto refresh and self refresh modes • Dual Internal banks controlled by A11(Bank select) • Simultaneous and independent two bank operation • I/O level : LVTTL interface • Random column access in every cycle • X8 organization • Input/output control by DQM • 2048 refresh cycles/32ms • Burst termination by burst stop and precharge command • Burst read single write option Document:1G5-0133 Rev.1 Page 1 VIS Pin Configuration VDD DQ0 VG3617801CT 16Mb CMOS Synchronous Dynamic RAM 44-Pin Plastic TSOP(II)(400 mil) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 VSS DQ7 VSSQ DQ1 VSSQ DQ6 VDDQ DQ2 VDDQ DQ5 VSSQ DQ3 VSSQ DQ4 VG3617801CT 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VDDQ NC NC WE CAS RAS CS VDDQ NC NC DQM CLK CKE NC (BS)A11 A10 A0 A1 A2 A3 VDD A9 A8 A7 A6 A5 A4 VSS Pin Description (VG3617801CT) Pin Name A0-A11 Function Address inputs - Row address A0-A10 - Column address A0-A8 A11:Bank select Data-in/data-out Row address strobe Column address strobe Write enable Ground Power Pin Name DQM Function DQ mask enable DQ0~DQ7 RAS CAS WE VSS VDD CLK CKE CS VDDQ VSSQ Clock input Clock enable Chip select Supply voltage for DQ Ground for DQ Document:1G5-0133 Rev.1 Page 2 VIS VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Block Diagram CLK CKE Clock Generator Address Mode Register Row Decoder Row Address Buffer & Refresh Counter Bank B Bank A Sense Amplifier RAS CAS WE Control Logic CS Command Decoder Data Control Circuit Input & Output Buffer Latch Circuit Column Address Buffer & Burst Counter Column Decoder & Latch Circuit DQM DQ Document:1G5-0133 Rev.1 Page 3 VIS Absolute Maximum Ratings VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Parameter Voltage on any pin relative to Vss Supply voltage relative to Vss Short circuit output current Power dissipation Operating temperature Operating temperature Symbol VIN,VOUT VDD,VDDQ IOUT PD TOPT TSTG Value -1.0 to +4.6 -1.0 to +4.6 50 1.0 0 to + 70 -55 to + 125 Unit V V mA W ¢J ¢J Recommended DC Operating Conditions Parameter Supply Voltage Input High Voltage, all inputs Input Low Voltage, all inputs Symbol VDD VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 °– °– Max 3.6 VDD+0.3 0.8 Unit V V V Note 1 2 Note 1.Overshoot limit : VIH(MAX.)=VDDQ+2.0V with a pulse width < 3ns 2.Undershoot limit : VIL=VSSQ-2.0V with a pulse < 3ns and -1.5V with a pulse < 5ns Capacitance (Ta=25¢J,f=1MHZ) Parameter Input capacitance(CLK) Input capacitance(all input pins except data pins) Data input/output capacitance Symbol C11 C12 CI/O Min 2.5 2.5 4.0 Max 4 5 6.5 Unit pF pF pF Document:1G5-0133 Rev.1 Page 4 VIS Parameter Operating current Symbol ICC1 Test Conditions Burst length=1 t RC ≥t RC (MIN.) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM DC Characteristics(Recommended Operating Conditions unless otherwise noted) CL=3 VG3617801CT -8H -8L -10 Min Max Min Max Min Max 90 90 85 85 3 2 30 85 3 2 30 80 3 2 30 Unit mA Notes 1,2 ,Io=0mA CL=2 One bank active Precharge standby current in power down mode Precharge standby current in Nonpower down mode ICC2 P CKE ≤ V IL(MAX.)tCK=15ns ≤ V IL(MAX)tCK= ∞ ≥ V IH(MIN.)tCK=15ns mA ICC2 PS CKE ICC2 N CKE CS mA ≥ V IH(MIN.) 6 6 6 Input signals are changed. one time during 30ns. ICC2 NS CKE ≥ V IH(MIN.), tCK= ∞ CLK ≤ V IL(MAX.) CKE CKE CKE CS Input signals are stable. Active standby current Icc3 P in power down mode Icc3 PS Active standby current Icc3 N in nonpower down mode ≤ V IL(MAX.),tCK=15ns ≤ V IL(MAX.),tCK= ∞ ≥ V IL(MAX.),tCK=15ns 3 2 30 3 2 30 3 2 30 mA mA ≥ V IL(MIN.) 15 15 15 Input signals are changed one time during 30ns Icc3 NS ≥ V IH(MIN.) tCK= ∞ CLE ≤ V IL(MAX.) CKE Input signals are stable. Operating current (Burst mode) Refresh current Self refresh current Input leakage current Icc4 t CK ≥ tCK (MIN.),Io=0mA CL=3 120 115 110 105 2 -5 -5 5 5 0.4 2.4 2.4 -5 -5 120 105 110 105 2 5 5 0.4 2.4 -5 -5 105 100 100 95 2 5 5 0.4 mA 1,2 Burst length=4 Icc5 Icc6 ILI t RC ≥t RC (MIN.) CL=2 CL=3 CL=2 mA mA uA uA V V 2 CKE ≤ 0.2V V in ≥ 0 , V in ≤ V DD +0.3V Pins not under test=0V Output leakage current ILO Output Low Voltage Output High Voltage VOL VOH V OUT ≥0, V OUT ≤V DD +0.3V DQ# in H-Z., Dout disabled IOL=2mA IOH =2mA Notes 1.Icc depends on output loading and cycle rates. Specified values are obtained with the output open. 2.Icc is measured on condition that addresses are changed only one time during tCK(MIN.). Document:1G5-0133 Rev.1 Page 5 VIS A.C Characteristics: Test Conditions: (Ta=0 to 70°C VDD=3.3V ± 0.3V ,VSS=0V) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM AC input Levels(V IH/VIL) Input rise and fall time Parameter CAS Latency 3 2 3 2 2.0/0.8V 1ns Input timing reference level/ Output timing reference level Output load condition 1.4V 50pF Unit symbol tCk3 tCk2 tAC3 tAC2 tCH tCL tCKS tCKH tAS tAH tDS tDH tCMS tCMH tOH tLZ tHZ tRRD tRCD tRP tRAS tRC tBDL tDAL tDPL tT tRSC tPDE tSRX tREF Min 10 10 -8H CLK cycle time CLK to valid output delay CLK high pulse width CLK low pulse width CKE setup time CKE hold time Address setup time Address hold time Data input setup time Data input hold time Command setup time Command hold time Output data hold time CLK to output in low-Z CLK to output in Hi-Z Row active to active delay RAS to CAS delay Row precharge time ROW active time ROW cycle time Last data in to burst stop Data-in to ACT(REF) Command (Auto Precharge) Data-in to precharge Transition time Mode reg. set cycle Power down exit setup time Self refresh exit time Refresh time 3 3 3 1 2 1 2 1 2 1 3 0 3 20 20 20 50 70 1 CLK 1CLK+tRP 1 CLK 1 2 CLK 8 8 VG3617801CT -8L -10 Max Min Max Min Max 10 10 13 15 6 6 8 6 7 8 3 4 3 4 3 3 1 1 2 3 1 1 2 3 1 1 2 3 1 1 3 3 0 0 8 3 8 3 8 20 20 20 26 20 26 120,000 50 120,000 60 120,000 70 86 1 CLK 1 CLK 1CLK+tRP 1CLK+tRP 1 CLK 1 2 CLK 8 8 1 CLK 1 2 CLK 8 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 10 10 10 32 32 32 Document:1G5-0133 Rev.1 Page 6 VIS Basic Features and Function description 1.simplified State diagram VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Self Refresh try en LF SE Mode Register Set MRS IDLE LF SE it ex REF AUTO Refresh CK E E CK ROW ACTIVE BS T ACT Power Down CKE CKE T BS Active Power Down ad Re W rit e Au Write to p red with har ge h wit rge ad cha Re Pre to Au Write Read PRE WRITE SUSPEND CKE CKE WRITE Read READ CKE CKE READ SUSPEND Write Write with Auto Precharge AutoRead w Prec ith harg e E(P PR ith e d w arg Rea Prech o Aut ter min atio n ) Read with Auto Precharge WRITE A SUSPEND CKE CKE WRITE A CKE READ A CKE READ A SUSPEND POWER ON Precharge Precharge Automatic sequence Manual input Note: After the AUTO refresh operation, precharge operation is performed automatically and enter the IDLE state Document:1G5-0133 Rev.1 PR E(P rec h arg e n) rec rge ha m ter tio ina Page 7 VIS 2.Truth Table 2.1 Command Truth Table VG3617801CT 16Mb CMOS Synchronous Dynamic RAM FUNCTION Device deselect No operation Mode register set Bank activate Read Read with auto precharge Write Write with auto precharge Precharge select bank Precharge all banks Burst stop Auto refresh (CBR) Symbol DESL NOP MRS ACT READ READA WRIT WRITA PRE PALL BST CBR CKE n-1 H H H H H H H H H H H H n X X X X X X X X X X X H CS H L L L L L L L L L L L RAS X H L L H H H H L L H L CAS X H L H L L L L H H H L WE X H L H H H L L L L L H A11 X X L V V V V V V X X X A10 X X X V L H L H L H X X A9A0 X X V V V V V V X X X X 2.2 DQM Truth Table CKE FUNCTION Data write/output enable Data mask/output disable Upper byte write enable/output enable Lower byte write enable/output enable Upper byte write inhibit/output disable Lower byte inhibit/output disable Symbol ENB MASK ENBU ENBL MASKU MASKL n-1 H H H H H H n-1 X X X X X X U DQM L L H L X H X X L X H 2.3 CKE Truth Table Current State Activating Any Clock suspend Idle Idle Self refresh Idle Power down Function Clock suspend mode entry Clock suspend Clock suspend mode exit CBR refresh command Self refresh entry Self refresh exit Power down entry Power down exit Symbol REF SELF CKE n-1 n H L L L L H H H H L L H L H H L L H CS X X X L L L H X X RAS X X X L L H X X X CAS X X X L L H X X X WE X X X H H H X X X Address X X X X X X X X X H : High level, L : Low level X : high or Low level(Don’t care), V : Valid Data input Document:1G5-0133 Rev.1 Page 8 VIS 2.4 Operative Command Table Notes 1 Current state Idle CS H L L L L L L L Row active H L L L L L L L Read H L L L L L L L L Write H L L L L L L L L RAS X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L CAS X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L WE X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L X X BA,CA,A10 BA,CA,A10 BR,RA BA,A10 X Op-Code X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code Address Command DESL NOP or BST VG3617801CT 16Mb CMOS Synchronous Dynamic RAM (1/3) Action Nop or Power down Nop or Power down ILLEGAL ILLEGAL Row active Nop Refresh or Self refresh Mode register access Nop Nop Begin read:Determine AP Begin write:Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end → Row active Continue burst to end → Row active Burst stop → Row active Term burst, new read:Determine AP Term burst, start write:Determine AP ILLEGAL Term burst,precharging ILLEGAL ILLEGAL Continue burst to end → write recovering Continue burst to end → Write recovering Burst stop → Row active Term burst, start read: determine AP Term burst, new write:Determine AP ILLEGAL Term burst precharging ILLEGAL ILLEGAL Notes 2 2 3 3 READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MPS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS 4 5 5 3 6 7 7,8 3 7,8 7 3 9 Document:1G5-0133 Rev.1 Page 9 VIS Current state Read with auto precharge CS H L L L L L L L L Write with auto precharge H RAS X H H H H L L L L X CA X H H L L H H L L X WE X H L H L H L H L X Address X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code X VG3617801CT 16Mb CMOS Synchronous Dynamic RAM (2/3) Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL PEF/SELF MRS DESL Action Continue burst to end → Prech arg ing Continue burst to end → Prech arg ing ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end → Write recovering with auto precharge Continue burst to end → Write recovering with auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP Nop → Enter idle after tRP Nop → Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP ILLEGAL ILLEGAL Nop → Enter row active after tRCD Nop → Enter row active after tRCD Nop → Enter row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes 3 3 L H H H X NOP L L L L L L L Precharging H L L L L L L L L Row activating H L L L L L L L L H H H L L L L X H H H H L L L L X H H H H L L L L H L L H H L L X H H L L H H L L X H H L L H H L L L H L H L H L X H L H L H L H L X H L H L H L H L X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-code X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS 3 3 3 3 3 3 3 3,10 3 Document:1G5-0133 Rev.1 Page 10 VIS Current state Write recovering CS H L L L L L L L L Write recovering with auto precharge H L L L L L L L L Refreshing H L L L L Mode register accessing H L L L L RAS X H H H H L L L L X H H H H L L L L X H H L L X H H H L CA X H H L L H H L L X H H L L H H L L X H L H L X H H L X WE X H L H L H L H L X H L H L H L H L X X X X X X H L X X Address X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code X X X X X X X X X X DESL NOP BST VG3617801CT 16Mb CMOS Synchronous Dynamic RAM (3/3) Command Action Nop → Enter row active after tDPL Nop → Enter row active after tDPL Nop → Enter row active after tDPL Notes READ/READA WRIT/WRITA ACT PRE/PALL PEF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT REF/PALL REF/SELF MRS DESL NOP/BST READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRITE ACT/PRE/PALL/ REF/SELF/MRS Start read, Determine AP New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter precharge after tDPL Nop → Enter precharge after tDPL Nop → Enter precharge after tDPL 8 3 3 ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRC Nop → Enter idle after tRC 3,8 3 3 3 ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after 2 Clocks Nop → Enter idle after 2 Clocks ILLEGAL ILLEGAL ILLEGAL Note 1. All entries assume that CKE was active (High level)during the preceding clock cycle. 2. If both banks are idle, and CKE is inactive(Low level), the device will enter Power down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If both banks are idle, and CKE is inactive(Low level), the device will enter Self refresh mode. All input buffers except CKE will be disabled. 5. IIIegal if tRCD is not satisfied. 6. IIIegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data if tDPL is not satisfied. 10. IIIegal if tRRD is not satisfied. Document:1G5-0133 Rev.1 Page 11 VIS 2.5 Command Truth Table for CKE Note 1 Current state Self refresh (S.R.) CKE n-1 H L L L L L H H H H H H H H L L H L L H H H H H H H H H H L H H L L RAS n X H H H H L H H H H L L L L H L X H L H H H H H L L L L L X H L H L CS X H L L L X H L L L H L L L X X X X X H L L L L H L L L L X X X X X RAS X X H H L X X H H L X H H L X X X X X X H L L L X H L L L X X X X X VG3617801CT 16Mb CMOS Synchronous Dynamic RAM CAS X X H L X X X H L X X H L X X X X X X X X H L L X X H L L X X X X X WE X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X Address X X X X X X X X X X X X X X X X X X Action INVALID,CLK(n-1)would exit S.R. S.R. Recovery S.R. Recovery ILLEGAL ILLEGAL Maintain S.R. Idle after tRC Idle after tRC ILLEGAL ILLEGAL Begin clock suspend next cycle Begin clock suspend next cycle ILLEGAL ILLEGAL Exit clock suspend next cycle Maintain clock suspend INVALID, CLK(n-1) would exit P.D. EXIT P · D · → Idle Maintain power down mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operation in Operative Command Table Refresh Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Self refresh Refer to operations in Operative Command Table Power down Refer to operations in Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend Notes 2 2 2 2 Self refresh recovery 5 5 2 Power down (P.D.) 2 Both banks idle X OpCode X OpCode X X X X X 3 3 Any state other than listed above 4 Note 1. H : Hight level, L : low level, X : High or low level(Don't care). 2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 3. Power down and Self refresh can be entered only from the both banks idle state. 4. Must be legal command as defined in Operative Command Table. 5.IIIegal if tSREX is not satisfied. Document:1G5-0133 Rev.1 Page 12 VIS VG3617801CT 16Mb CMOS Synchronous Dynamic RAM 3.Initiallization The synchronous DRAM is initialized in the power on sequence. Once power has been applied, a 100us minimum delay is needed in which stable power and input signals are maintained. During this delay, CKE and DQM recommend to be held high. After the 100us delay, both banks must be precharged using the precharge command. Once precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. Minimum two CBR refresh commands must be performed before or after the mode register set command. 4.Programming the Mode Register The mode register is programmed by the mode register set command using address bits A11 through A0 as data inputs. The register retains data until it is reprogrammed or until the device loses power. The mode register has four fields; Options CAS latency Wrap type Burst length : A11 through A7 : A6 through A4 : A3 : A2 through A0 Following mode register programming, no command can be asserted befor at least two clock cycles have elapsed. CAS Latency CAS latency is the most critical parameter to be set. It tells the device how many clocks must elapse before the data will be available. The SDRAM is capable of reconfiguring its internal architecture based on the value of CAS latency. The value is determined by the frequency of the clock and the speed grade of the device. The value can be programmed as 2 or 3. Burst Length Burst Length is the number of words that will be output or input in read or write cycle. After a read burst is completed, the output bus will become high impedance. The burst length is programmable as 1,2,4,8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. The order is programmable as either “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. Both sequences support bursts of 1,2,4 and 8. Only the sequential burst. supports the full-page length. Document:1G5-0133 Rev.1 Page 13 VIS 5.Mode Register VG3617801CT 16Mb CMOS Synchronous Dynamic RAM 11 0 11 x 11 x 10 0 10 x 10 x 9 0 9 1 9 0 8 0 8 0 8 0 7 1 7 0 7 0 6 6 6 5 4 3 2 1 1 BL 1 BL 0 Reserved Test Set 0 0 Burst Read and Single Write X=Don’t care Mode Register Set Bits2-0 000 001 010 Burst length 011 100 101 110 111 Wrap type 0 1 WT=1 1 2 4 8 R R R R 5 4 LTMODE 5 4 LTMODE 3 2 WT 3 2 WT WT=0 1 2 4 8 R R R Full page Sequential Interleave Bits6-4 000 001 010 Latency mode 011 100 101 110 111 Remark R:Reserved CAS Iatency R R 2 3 R R R R Document:1G5-0133 Rev.1 Page 14 VIS 5.1 Burst Length and Sequence (Burst of Two) Starting Address (column address A0, binary) 0 1 (Burst of Four) Starting Address (column address A1-A0, binary) 00 01 10 11 (Burst of Eight) Starting Address (column address A2-A0, binary) 000 001 010 011 100 101 110 111 Sequential Addressing Sequence (decimal) 0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 2,3,4,5,6,7,0,1 3,4,5,6,7,0,1,2 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 6,7,0,1,2,3,4,5 7,0,1,2,3,4,5,6 Sequential Addressing Sequence (decimal) 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 Sequential Addressing Sequence (decimal) 0,1 1,0 VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Interleave Addressing Sequence(decimal) 0,1 1,0 Interleave Addressing Sequence(decimal) 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0 Interl eave Addressing Sequence(decimal) 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 Full page burst is an extension of the above tables of sequential addressing, with the length being 512/ 256 words for 2Mx8/1Mx16 devices, respectively. Document:1G5-0133 Rev.1 Page 15 VIS 6.Address Bits of Bank-Select and Precharge Row A0 A1 A2 A3 A4 A5 A6 (Activate command) 0 A7 A8 A9 A10 A11 VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Select Bank A ”Activate” command 1 Select Bank B ”Activate” command Row A0 A1 A2 A3 A4 A5 A6 (Precharge) A7 A8 A9 A10 A11 A10 A11 Result 0 0 1 0 1 x Precharge Bank A Precharge Bank B Precharge All Banks x:Don’t care 0 1 Disables Auto-Precharge (End of Burst) Enables Auto-Precharge (End of Burst) Col. A0 A1 A2 A3 A4 A5 A6 (CAS strobes) A7 A8 A9 A10 A11 0 Enable Read/Write commands for Bank A 1 Enable Read/Write commands for Bank B Document:1G5-0133 Rev.1 Page 16 VIS 7.PRECHARGE VG3617801CT 16Mb CMOS Synchronous Dynamic RAM The PRECHARGE command can be asserted anytime after tRAS(min) is satisfied. Soon after the PRECHARGE command is asserted, PRECHARGE operation is performed. The synchronous DRAM enters the idle state after tRP(min) is satisfied. The parameter t RP is the time required to perform the PRECHARGE. The earliest timing in a READ cycle that a PRECHARGE command can be asserted without losing any data in the burst is as followed. PRECHARGE Burst lengh=4 T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Read PRE CAS latency=2 DQ Hi-Z_ Q0 Q1 Q2 Q3 Command CAS latency=3 DQ Read PRE Hi-Z Q0 Q1 Q2 Q3 CAS latency= 2: One clock earlier than the last output data. 3: Two clocks earlier than the last output data. (tRAS is satisfied) In order to write all data to the memory cell correctly, the asynchronous parameter”tDPL” must be satisfied. The tDPL(MIN.) specification defines the earliest time that a PRECHARGE command can be asserted after a WRITE cycle. The minimum number of clocks are calculated by dividing tDPL(min.) by the clock cycle time. In summary, the PRECHARGE command can be asserted relative to the reference clock of the last valid data. In the following table, minus means clocks before the reference, plus means time after the reference. CAS latency 2 3 READ -1 -2 WRITE +tDPL(min.) +tDPL(min) Document:1G5-0133 Rev.1 Page 17 VIS 8.AUTO PRECHARGE VG3617801CT 16Mb CMOS Synchronous Dynamic RAM During a READ or WRITE command cycle, A10 controls whether AUTO PRECHARGE is selected. If A10 is high in the READ or WRITE command (READ with AUTO PRECHARGE command or WRITE with AUTO PRECHARGE command), AUTO PRECHARGE is selected and precharging begins automatically after the burst access. In the WRITE cycle, tDAL(min.) must be satisfied to assert the next active command to the bank being precharged. When using AUTO PRECHARGE in the READ cycle, knowing when the PRECHARGE starts is important because the tRAS must be satisfied. Once AUTO PRECHARGE has started, an active command to the bank can be asserted after tRP(min.) has been satisfied. The timing at which the AUTO PRECHARGE cycle begins depends both on the CAS Iatency programmed into the mode register and on whether the cycle is READ or WRITE. 8.1 READ with AUTO PRECHARGE During a READA cycle, the AUTO PRECHARGE begins one clock earlier(CAS Iatency of 2) or two clocks earlier(CAS Iatency of 3) than the last data word output. READ with AUTO PRECHARGE Burst lengh=4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command READA B Auto precharge starts CAS latency=2 DQ Hi-Z QB0 QB1 QB2 QB3 Auto precharge starts Command READA B CAS latency=3 DQ QB0 QB1 QB2 QB3 Hi-Z Remark READA means READ with AUTO PRECHARGE Document:1G5-0133 Rev.1 Page 18 VIS 8.2 WRITE with AUTO PRECHARGE the device WRITE with AUTO PRECHRGE VG3617801CT 16Mb CMOS Synchronous Dynamic RAM During a WRITA cycle, the AUTO PRECHARGE starts at tDPL(min.) after the last data word input to Burst lengh=4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command WRITA B AUTO PRECHARGE starts tDPL CAS latency=2 DQ DB0 DB1 DB2 DB3 Hi-Z_ AUTO PRECHARGE starts Command CAS latency=3 Hi-Z WRITA B tDPL DQ DB0 DB1 DB2 DB3 Remark WRITA means WRITE with AUTO PRECHARGE In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means clocks after the reference. CAS latency 2 3 READ -1 -2 WRITE +tDPL(min.) +tDPL(min) Document:1G5-0133 Rev.1 Page 19 VIS 9.READ/WRITE Command Interval 9.1 READ to READ command interval VG3617801CT 16Mb CMOS Synchronous Dynamic RAM When a new READ command is asserted during a READ cycle, it will be effective after the CAS latency, even if the previous READ operation has not completed. READ will be interrupted by another READ. A READ command can be asserted in every clock without restriction. READ to READ Command Interval Burst lengh=4, CAS latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Read A Read B Command DQ QA0 QB0 QB1 QB2 QB3 Hi-Z_ 1 cycle 9.2 WRITE to WRITE Command Interval When a new WRITE command is asserted during a WRITE cycle, the previous burst will be terminated and the new burst will begin with the new WRITE command. WRITE will be interrupted by another WRITE. A WRITE command can be asserted in every clock without restriction. WRITE to WRITE Command Interval Burst lengh=4, CAS latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Write A Write B Command DQ QA0 QB0 QB1 QB2 QB3 Hi-Z_ 1 cycle Document:1G5-0133 Rev.1 Page 20 VIS WRITE to READ Command Interval VG3617801CT 16Mb CMOS Synchronous Dynamic RAM 9.3 WRITE to READ Command Interval The WRITE command to READ command interval is a minimum of 1 cycle. Only the WRITE data preceding the READ command will be written. The data bus must be in high-impedance at least one cycle prior to the first DOUT. Burst lengh=4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK 1 cycle Command CAS latency=2 Hi-Z WRITE A Read B DQ DA0 QB0 QB1 QB2 QB3 Command Write A Read B CAS latency=3 DQ DA0 Hi-Z QB0 QB1 QB2 QB3 9.4 READ to WRITE Command Interval During READ cycle, READ can be interrupted by WRITE. The data bus must be in high-impedance using DQM before the WRITE command. DQM must be high at least 3 clocks prior to the WRITE command. This restriction is necessary to avoid a data bus conflict. Document:1G5-0133 Rev.1 Page 21 VIS READ to WRITE Command Interval T0 T1 T2 T3 VG3617801CT 16Mb CMOS Synchronous Dynamic RAM T4 T5 T6 T7 CAS latency=2 T8 CLK Command Read Write DQM DQ Hi-Z D0 D1 D2 D3 1 cycle T0 T1 T2 T3 T4 T5 T6 T7 Burst length=8, CAS latency=2 T8 T9 CLK Command Read Write DQM DQ Q0 Q1 Q2 Hi-Z is necessary D0 D1 D2 example: Burst length=4, CAS latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command Read Write DQM DQ Q2 Hi-Z is necessary The minimum command interval = (4+1) cycles D0 D1 D2 Document:1G5-0133 Rev.1 Page 22 VIS 10.1 BURST STOP Command VG3617801CT 16Mb CMOS Synchronous Dynamic RAM 10.BURST TERMINATION There are two methods to terminate a BURST operation other than using a READ or a WRITE command. One is the BURST STOP command and the other is the PRECHARGE command. During a READ BURST. when the BURST STOP command is asserted, the BURST READ outputs are terminated and the data bus goes to high-impedance after the CAS latency from the BURST STOP command. During a WRITE BURST. when the BURST STOP command is asserted, any data provided at that cycle will not be written. The BURST WRITE is effectively terminated and no further data can be written until a new WRITE command is asserted. Burst Termination T0 T1 T2 T3 T4 T5 Burst lengh=X, CAS Intency=2,3 T7 T6 CLK BST Command Read CAS latency=2 DQ Q0 Q1 Q2 Hi-Z CAS latency=3 DQ Q0 Q1 Q2 Hi-Z Remark BST: Burst stop command Burst lengh=X, CAS latency=2,3 T7 T6 T0 T1 T2 T3 T4 T5 CLK BST Command Write CAS latency=2,3 Q0 DQ Q0 Q1 Q2 Hi-Z_ Remark BST: Burst stop command Document:1G5-0133 Rev.1 Page 23 VIS 10.2 PRECHARGE TERMINATION 10.2.1 PRECHARGE TERMINATION in READ Cycle VG3617801CT 16Mb CMOS Synchronous Dynamic RAM During a READ cycle, the BURST READ operation can be terminated by a PRECHARGE command. When the PRECHARGE command is asserted, the BURST READ operation is terminated and PRECHARGE starts. Read data will remain valid until one clock(CAS latency of 2)or two clocks(CAS latency of 3) after the PRECHARGE command and the same bank can be activated again after tRP(min) from the PRECHARGE command. PRECHARGE TERMINATION in READ Cycle Burst lengh= X T8 T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Read PRE ACT CAS latency=2 DQ Q0 Q1 Q2 Q3 tRP command Read PRE tRP Hi-Z ACT Hi-Z CAS latency=3 DQ Q0 Q1 Q2 Q3 Document:1G5-0133 Rev.1 Page 24 VIS 10.2.2 PRECHARGE TERMINATION in WRITE Cycle VG3617801CT 16Mb CMOS Synchronous Dynamic RAM During a WRITE cycle, the BURST WRITE operation can be terminated by a PRECHARGE command. when the PRECHARGE command is asserted, the BURST WRITE operation in immediately terminated and PRECHARGE starts. The same bank can be activated again after tRP(min.) from the PRECHARGE command. The DQM must be high to mask invalid data in. When CAS latency is 2 or 3, the data written prior to the PRECHARGE command will be correctly stored. However, invalid data may be written at the same clock as the PRECHARGE command. To prevent this from happening, DQM must be high at the same clock as the PRECHARGE command. This will mask the invalid data. PRECHARGE TERMINATION in WRITE Cycle33 T0 T1 T2 T3 T4 T5 T6 T7 Burst lengh = X T8 CLK Command Write PRE ACT CAS latency=2 DQM DQ D0 D1 D2 D3 D4 tRP command Write PRE ACT Hi-Z CAS latency=3 DQM Hi-Z DQ D0 D1 D2 D3 D4 tRP Document:1G5-0133 Rev.1 Page 25 VIS VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Timing Diagram Document:1G5-0133 Rev.1 Page 26 VIS Mode Register Set T0 T1 T2 T3 T4 T5 VG3617801CT 16Mb CMOS Synchronous Dynamic RAM T6 T7 T8 T9 T10 CLK CKE t RSC CS RAS CAS WE A11(BS) A10 A0-A9 Key DQM t DQ Hi-Z RP Precharge Command All Banks Mode Register Set Command Command Document:1G5-0133 Rev.1 Page 27 VIS AC Parameters for Write Timing (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CL t CH t CK2 Begin Auto Precharge Begin Auto Precharge Bank A Bank B CKE t CKS t CMS t CMH t CKH CS RAS CAS WE A11(BS) A10 t AS RAa RBa RAb RAc RBb t AH CAa RBa A0~A9 RAa CBa RAb CAb RAc RBb DDM DQ t RCD t RRD t RC t DAL t DS t DH t DPL t RP DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBa2 DBa3 DAb0 DAb1 DAb2 DAb3 Activate Write with Command Auto Precharge Command Bank A Bank A Write with Activate Command Auto Precharge Command Bank B Bank B Activate Command Bank A Write with Auto Precharge Command Bank A Precharge Command Bank A Activate Command Bank A Activate Command Bank B Document:1G5-0133 Rev.1 Page 28 VIS AC Parameters for Write Timing (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 CLK t CL t CH t CKS t CMS t CMH t CK3 Begin Auto Precharge Bank A Begin Auto Precharge Bank B t CKH CKE CS RAS CAS WE A11(BS) A10 t AS RAa tAH RBa RAb RAc A0~A9 RAa CAa RBa CBa RAb CAb RAc DDM tRCD DQ t RRD tRC t DAL tDS t DH t DPL t RP DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBa2 DBa3 DAb0 DAb1 DAb2 DAb3 Activate Command Bank A Write with Auto Precharge Command Bank A Activate Command Bank B Write with Auto Precharge Command Bank B Activate Command Bank A Write without Auto Precharge Command Bank A Precharge Command Bank A Activate Command Bank A Document:1G5-0133 Rev.1 Page 29 VIS AC Parameters for Read Timing (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=2, CAS Latency=2 T0 CLK tCH tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 tCK2 tCMS t CMH Begin Auto Precharge Bank B t CKH CKE tCKS CS RAS CAS WE A11(BS) A10 RAa tAS tAH RBa RAb A0-A9 RAa CAa tRRD RBa CBa RAb tRAS tRC DQM t AC2 tLZ tAC2 tOH QAa0 t RCD tHZ tOH QAa1 QBa0 tRP tHZ QBa1 DQ Hi-Z Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Bank B Precharge Command Bank A Activate Command Bank A Document:1G5-0133 Rev.1 Page 30 VIS AC Parameters for Read Timing (2 of 2) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=2, CAS Latency=3 T9 T10 T11 T12 T13 T14 T15 t CH tCL t CK3 t CMS t CMH Begin Auto Precharge Bank B CKE tCKS t CKH CS RAS CAS WE A11(BS) A10 RAa t AH t AS RBa RAb A0-A9 RAa t RRD CAa RBa CBa RAb t RAS t RC t RP DQM t RCD tAC3 tLZ tAC3 tOH tHZ tOH QAa1 QBa0 t HZ DQ Hi-Z QAa0 QBa1 Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Precharge Command Bank A Activate Command Bank A Document:1G5-0133 Rev.1 Page 31 VIS Power on Sequence and Auto Refresh (CBR) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK High level is required t RSC Minimum of 2 Refresh Cycles are required CKE CS RAS CAS WE A11(BS) A10 Address Key A0~A9 DDM High Level is Necessary t RP t RC DQ Inputs Precharge 1st Auto must Command Refresh be stable All Banks Command for 100us 2nd Auto Refresh Command Mode Command Register Set Command Document:1G5-0133 Rev.1 Page 32 VIS Clock Suspension During Burst Read (Using CKE) (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE A11(BS) A10 RAa A0~A9 RAa CAa DDM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 t HZ Activate Command Bank A Read Command Bank A Clock Suspended 1 Cycle Clock Suspended 2 Cycles Clock Suspended 3 Cycles Document:1G5-0133 Rev.1 Page 33 VIS Clock Suspension During Burst Read (Using CKE) (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE A11(BS) A10 RAa A0~A9 RAa CAa DDM t HZ DQ Hi-Z QAa0 QAa1 QAa2 QAa3 Activate Command Bank A Read Command Bank A Clock Suspended 1 Cycle Clock Suspended 2 Cycles Clock Suspended 3 Cycles Document:1G5-0133 Rev.1 Page 34 VIS Clock Suspension During burst Write (Using CKE) (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE A11(BS) A10 RAa A0~A9 RAa CAa DDM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 Activate Command Bank A Clock Suspended 1 Cycle Write Command Bank A Clock Suspended 2 Cycles Clock Suspended 3 Cycles Document:1G5-0133 Rev.1 Page 35 VIS Clock suspension during Burst write (Using CKE) (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE A11(BS) A10 RAa A0~A9 RAa CAa DDM t DQ Hi-Z QAa0 QAa1 QAa2 QAa3 Activate Command Bank A Clock Suspended 1 Cycle Write Command Bank A Clock Suspended 2 Cycles Clock Suspended 3 Cycles Document:1G5-0133 Rev.1 Page 36 VIS Power Down Mode and Clock Mask VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 t CKS t CKH t CKS CKE VALID CS RAS CAS WE A11(BS) A10 RAa A0~A9 RAa CAa DDM DQ Hi-Z QAa0 QAa1 QAa2 t HZ QAa3 Activate Command Bank A ACTIVE STANDBY Read Command Bank A Clock Mask Start Clock Mask End Precharge Command Power Down Mode Entry Precharge Standby Power Down Mode Entry Power Down Mode Exit Power Down Mode Exit Command Document:1G5-0133 Rev.1 Page 37 VIS Auto Refresh (CBR) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE A11(BS) A10 RAa A0~A9 RAa CAa DDM t RP t RC t RC Q0 Q1 Q2 Q3 DQ Hi-Z Precharge CBR Refresh Command Command All Banks CBR Refresh Command Activate Read Command Command Document:1G5-0133 Rev.1 Page 38 VIS Self Refresh (Entry and Exit) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t SRX t CKS t SRX t PDE CKE CS RAS CAS WE A11(BS) A10 A0~A9 t RC t RC DDM DQ Hi-Z All Banks must be idle Self refresh Entry Self Refresh Exit Self Refresh Exit Self Refresh Exit Activate Command Document:1G5-0133 Rev.1 Page 39 VIS Random Column Read (Page Within same Bank)(1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE A11(BS) A10 RAa RAd RAa A0~A9 RAa CAa CAb CAc RAd CAd DDM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3 QAd0 QAd1 QAd2 QAd3 Precharge Command Bank A Read Command Bank A Read Read Command Command Bank A Bank A Precharge Activate Read Command Command Command Bank A Bank A Bank A Document:1G5-0133 Rev.1 Page 40 VIS Random Column Read (Page Within same Bank)(2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE A11(BS) A10 RAa RAd A0~A9 RAa CAa CAb CAc RAd CAd DDM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3 Activate Command Bank A Read Command Bank A Read Read Command Command Bank A Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A Document:1G5-0133 Rev.1 Page 41 VIS Random Column Write (Page Within same Bank) (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE A11(BS) A10 RAa RAd A0~A9 RBa CBa CBb CBc RBd CBd DDM DQ Hi-Z DBa0 DBa1 DBa2 DBa3 DBb0 DBb1 DBc0 DBc1 DBc2 DBc3 DBd0 DBd1 DBd2 DBd3 Activate Command Bank B Write Command Bank B Write Write Command Command Bank B Bank B Precharge Activate Write Command Command Command Bank B Bank B Bank B Document:1G5-0133 Rev.1 Page 42 VIS Random Column Write (Page Within same Bank) (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE A11(BS) A10 RBa RBd A0~A9 RBa CBa CBb CBc CBd RBd DDM DQ Hi-Z DBa0 DBa1 DBa2 DBa3 DBb0 DBb1 DBc0 DBc1 DBc2 DBc3 DBd0 DBd1 DBd2 Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank B Precharge Command Bank B Activate Command Bank B Write Command Bank B Document:1G5-0133 Rev.1 Page 43 VIS Random Row Read (Interleaving Banks) (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=8, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS RAS CAS WE A11(BS) A10 RBa RAa RBb A0~A9 RBa CBa RAa CAa RBb CBb t RCD t AC2 t RP DDM DQ Hi-Z QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0 QBb1 Activate Command Bank B Read Command Bank B Activate Command Bank A Precharge Active Command Command Bank B Bank B Read Command Bank A Read Command Bank B Document:1G5-0133 Rev.1 Page 44 VIS Random Row Read (Interleaving Banks) (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=8, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS RAS CAS WE A11(BS) A10 RBa RAa RBb A0~A9 RBa CBa RAa CAa RBb CBb t t RCD AC3 t RP DDM DQ Hi-Z QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0 Activate Command Bank B Read Command Bank B Activate Command Bank A Read Command Bank A Precharge Command Bank B Activate Command Bank B Read Precharge Command Command Bank B Bank B Document:1G5-0133 Rev.1 Page 45 VIS Random Row Write (Interleaving Banks) (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=8, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS RAS CAS WE A11(BS) A10 RAa RBa RAb A0~A9 RAa CAa RBa CBa RAb CAb DDM DQ Hi-Z t RCD t DPL t RP t DPL QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 DAb0 DAb1 DAb2 DAb3 DAb4 Activate Command Bank A Write Command Bank A Activate Command Bank B Precharge Active Command Command Bank A Bank A Write Command Bank B Write Command Bank A Precharge Command Bank B Document:1G5-0133 Rev.1 Page 46 VIS Random Row Write (Interleaving Banks) (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=8, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS RAS CAS WE A11(BS) A10 RAa RBa R Ab A0~A9 RAa CAa RBa R Ba CBa RAb CAb DDM DQ Hi-Z t RCD t DPL t RP t DPL DAa0 DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DBa0 DBa1 DBa2 DBa3 DBa4 QBa5 DBa6 DBb7 DAb0 DAb1 DAb2 DAb3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Precharge Write Command Command Bank B Bank A Document:1G5-0133 Rev.1 Page 47 VIS Read and Write Cycle (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE A11(BS) A10 RAa A0~A9 RAa C Aa C Ab CAc DQM Hi-Z DQ QAa0 QAa1 QAa2 QAa3 DAb0 DAb1 DAb3 QAc0 QAc1 QAc3 Activate Command Bank A Write Command Bank A The Write Data Write Command is Masked with a Bank A Zero Clock latency Read Command Bank A The Read Data is Masked with Two Clocks Latency Document:1G5-0133 Rev.1 Page 48 VIS Read and Write Cycle (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE A11(BS) A10 RAa A0~A9 RAa C Aa CAb CAc DQM Hi-Z QAa0 QAa1 QAa2 QAa3 DQ DAb0 DAb1 DAb3 QAc0 QAc1 QAc3 Activate Command Bank A Read Command Bank A Write The Write Data Read Command is Masked with a Command Bank A Bank A Zero Clock latency The Read Data is Masked with Two Clock Latency Document:1G5-0133 Rev.1 Page 49 VIS Interleaved Column Read Cycle (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE A11(BS) A10 RAa RBa A0~A9 R Aa CAb R Ba C Ba CBb C Bc C Ab CBd DQM t RCD t AC2 DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3 Activate Command Bank A Read Read Read Activate Read Read Read Command Command Command Command Command Command Command Bank A Bank A Bank B Bank B Bank B Bank B Bank B Precharge Command Bank A Precharge Command Bank B Document:1G5-0133 Rev.1 Page 50 VIS Interleaved Column Read Cycle (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE A11(BS) A10 RAa RBa A0~A9 R Aa C Aa R Ba CBa CBb CBc C Ab DQM t RCD t RRD t AC3 DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QAb2 QAb3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Read Read Read Precharge Precharge Command Command Command Command Command Command Bank A Bank B Bank B Bank B Bank B Bank A Document:1G5-0133 Rev.1 Page 51 VIS Interleaved Column Write Cycle (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE A11(BS) A10 RAa RBa A0~A9 R Aa CAa R Ba C Ba CBb CBc CAb CBb t RCD t RP t DPL DQM t Hi-Z DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DBd0 DBd1 DBd2 DBd3 RRD DQ Activate Write Write Write Write Write Activate Command Command Command Command Command Command Command Bank B Bank B Bank A Bank A Bank B Bank B Bank A Precharge Command Bank A Write Command Bank B Precharge Command Bank B Document:1G5-0133 Rev.1 Page 52 VIS Interleaved Column Write Cycle (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE A11(BS) A10 RAa RBa A0~A9 R Aa C Aa R Ba CBa CBb CBc C Ab CBd t RCD t DPL t RP t DPL DQM t Hi-Z DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DAd0 QAd1 QAd2 QAd3 RRD DQ Activate Command Bank A Write Command Bank A Activate Command Bank B Write Write Write Write Write Command Command Command Command Command Bank A Bank B Bank B Bank B Bank B Precharge Command Bank A Precharge Command Bank B Document:1G5-0133 Rev.1 Page 53 VIS Auto Precharge after Read Burst (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK High t CK2 Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B CKE CS RAS CAS WE A11(BS) A10 RAa R Ba RBb RAc A0~A9 RAa CAa R Ba CBa CAb R Bb CBb RAc C Ac DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 Activate Read Activate Read with Command Command Command Auto Precharge Bank A Bank A Bank B Command Bank A Read with Activate Activate Auto Precharge Command Command Command Bank B Read with Bank A Bank A Auto Precharge Command Read with Bank B Auto Precharge Command Bank A Document:1G5-0133 Rev.1 Page 54 VIS Auto Precharge after Read Burst (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK High t CK3 Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B CKE CS RAS CAS WE A11(BS) A10 RAa R Ba RBb A0~A9 R Aa CAa RBa CBa CAb RBb CBb DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Read with Read with Auto Precharge Auto Precharge Command Command Bank A Bank B Activate Command Bank B Document:1G5-0133 Rev.1 Page 55 VIS Auto Precharge after Write Burst (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK High t CK2 Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B CKE CS RAS CAS WE A11(BS) A10 RAa R Ba RBb RAc A0~A9 R Aa CAa RBa CBa CAb RBb C Bb RAc CAc DQM DQ Hi-Z DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBa2 DBa3 DAb0 DAb1 DAb2 DAb3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DAc2 DAc3 Activate Write Write with Activate Command Command Command Auto Precharge Command Bank A Bank B Bank A Bank B Activate Write with Activate Command Auto Precharge Command Bank A Command Bank B Write with Bank A Write with Auto Precharge Auto Precharge Bank A Command Bank B Start Auto Precharge Bank A Document:1G5-0133 Rev.1 Page 56 VIS Auto Precharge after Write Burst (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK High t CK3 Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B CKE CS RAS CAS WE A11(BS) A10 RAa R Ba RBb A0~A9 R Aa CAa RBa C Ba C Ab RBb CBb DQM DQ Hi-Z DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBa2 DBa3 DAb0 DAb1 DAb2 DAb3 DBb0 DBb1 DBb2 DBb3 Activate Command Bank A Activate Command Bank B Write Command Bank A Write with Auto Precharge Command Bank B Write with Auto Precharge Command Bank A Activate Command Bank B Write with Auto precharge Command Bank B Document:1G5-0133 Rev.1 Page 57 VIS Full Page Read Cycle (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS RAS CAS WE A11(BS) A10 RAa RBa R Bb A0~A9 RAa CAa RBa C Ba RBb DDM DQ Hi-Z QAa Q Aa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+51QBa+6 t RP Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address Precharge Command Bank B Burst Stop Command Activate Command Bank B Document:1G5-0133 Rev.1 Page 58 VIS Full Page Read Cycle (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=Full Page, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS RAS CAS WE A11(BS) A10 RAa RBa R Bb A0~A9 RAa CAa RBa CBa RBb DDM DQ Hi-Z QAa QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa0 t RP QBa+1 QBa+2 QBa+3 QBa+4 QBa+5 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Full page burst operation does not teminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address Precharge Command Bank B Burst Stop Command Activate Command Bank B Document:1G5-0133 Rev.1 Page 59 VIS Full Page Write Cycle (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS RAS CAS WE A11(BS) A10 RAa RBa RBb A0~A9 RAa CAa RBa CBa RBb DDM DQ Hi-Z DAa DAa+1 DAa+2 DAa+3 DAa-1 DAa DAa+1 DBa DBa+1 DBa+2 DBa+3 DBa+4 DBa+5 DBa+6 t BDL Activate Command Bank A Write Command Bank A Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Write Command Bank B Data is ignored Precharge Command Bank B Burst Stop Command Activate Command Bank B Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address Document:1G5-0133 Rev.1 Page 60 VIS Full Page Write Cycle (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=Full Page, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS RAS CAS WE A11(BS) A10 RAa RBa R Bb A0~A9 RAa CAa R Ba CBa RBb DDM DQ Hi-Z DAa D Aa+1 DAa+2 DAa+3 DAa-1 DAa DAa+1 DBa tBDL DBa+1 DBa+2 DBa+3 DBa+4 DBa+5 Data is ignored. Activate Command Bank A Write Command Bank A Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Write Command Bank B Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address Precharge Command Bank B Burst Stop Command Activate Command Bank B Document:1G5-0133 Rev.1 Page 61 VIS Byte Write Operation VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS RAS CAS WE A11(BS) A10 RAa A0~A9 R Aa CAa C Ab CAz LDQM UDQM Hi-Z DQ0~DQ7 Hi-Z DQ8~DQ15 Activate Command Bank A Read Command Bank A Upper Byte is masked Lower Byte is masked Write Command Bank A Read Write Upper Command is masked Bank A Lower Byte is masked Lower Byte is masked Document:1G5-0133 Rev.1 Page 62 VIS Burst Read and Single Write Operation VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS RAS CAS WE A11(BS) A10 RAa A0~A9 R Aa CAa C Ab CAc CAd CAe LDQM UDQM Hi-Z DQ0~DQ7 Hi-Z DQ8~DQ15 Activate Command Bank A Read Command Bank A Read Single Write Single Write Command Command Command Bank A Bank A Bank A Lower Byte is masked Upper Byte is masked Single Write Command Bank A Lower Byte is masked Document:1G5-0133 Rev.1 Page 63 VIS Full Page Random Column Read VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE A11(BS) A10 RAa R Ba RBb A0~A9 RAa RBa CAa CBa C Ab CBb CAc CBc RBb t RP DQM DQ Hi-Z QAa0 QBa0 QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2 Activate Command Bank A Activate Command Bank B Read Command Bank B Read Command Bank A Read Command Bank B Read Command Bank A Read Command Bank B Precharge Command Bank B (Precharge Termination) Activate Command Bank B Read Command Bank A Document:1G5-0133 Rev.1 Page 64 VIS Full Page Random Column Write VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE A11(BS) A10 RAa R Ba RBb A0~A9 RAa RBa CAa CBa C Ab CBb CAc CBc RBb t RP DQM DQ Hi-Z QAa0 QBa0 QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2 Activate Command Bank A Activate Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank B (Precharge Termination) Write Data is masked Activate Command Bank B Write Command Bank A Document:1G5-0133 Rev.1 Page 65 VIS Precharge Termination of a Burst (1 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4,8 or Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK High t CK2 CKE CS RAS CAS WE A11(BS) A10 RAa RAb RAc A0~A9 RAa CAa RAb CAb RAc CAc t DPL t RP t RP t RP DQM DQ Hi-Z QAa0 QAa1 QAa2 Da3 QAb0 QAb1 QAb2 QAc0 QAc1 QAc2 Activate Command Bank A Write Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Command Bank A Precharge Termination of a Write Burst. Write data is masked. Precharge Termination of a Read Burst. Document:1G5-0133 Rev.1 Page 66 VIS Precharge Termination of a Burst (2 of 2) VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Burst Length=4,8 or Full Page, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK High t CK3 CKE CS RAS CAS WE A11(BS) A10 RAa RAb RAc A0~A9 RAa CAa RAb CAb RAc t DPL t RP t RAS t RP DQM t RCD DQ Hi-Z DAa0 DAa1 QAb0 QAb1 QAb2 QAb3 Activate Command Bank A Write Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A Activate Command Bank A Activate Command Bank A Write Data is masked Precharge Termination of a Write Burst. Precharge Termination of a Read Burst. Document:1G5-0133 Rev.1 Page 67 VIS Ordering information Part Number VG3617801BT-8H VG3617801BT-8L VG3617801BT-10 VG3617801BT-10 • VG • 36 • 17801 •B •T • 10 VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Cycle time 10ns 10ns 10ns Package 400mil 44-Pin Plastic TSOP • VIS Memory Product • Technology/Design Rule • Device Type/Configuration • Mask/Design Version • Package Type, T: TSOP • Cycle time, 10: 10ns, CL=2,tRP=2,tRCD=2 for PC 66 8L: 10ns, CL=3,tRP=2,tRCD=2 for PC 100 8H: 10ns, CL=2,tRP=2,tRCD=2 for PC 100 Packaging Information • 400mil, 44-Pin Plastic TSOP RAD R1 DIM A A1 A2 b b1 c c1 D ZD e E E1 L R R1 11.56 10.03 0.40 0.10 0.10 MILLIMETERS MIN. --0.05 0.95 0.30 0.30 0.12 0.10 18.28 NOM. ----1.00 --------18.41 0.805 REF. 0.80 BASIC 11.76 10.16 0.50 ----11.96 10.29 0.60 0.25 --0.455 0.395 0.016 0.004 0.004 MAX. 1.27 0.15 1.06 0.45 0.40 0.21 0.16 18.54 MIN. --0.002 0.037 0.012 0.012 0.005 0.004 0.720 INCHES NOM. ----0.039 --------0.725 0.0317 REF. 0.0315 BASIC 0.463 0.400 0.020 ----0.471 0.405 0.024 0.010 --DETAIL A ZD NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm. DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm. A MAX. 0.050 0.006 0.042 0.018 0.016 0.008 0.006 0.730 A1 E1 L 44 23 A2 RAD R B B c DETAIL A b b1 0¢X~5¢X SECTION B-B c1 c 1 D 22 BASE METAL WITH PLATING b e SEATING PLANE 0.100(0.004) E Document:1G5-0133 Rev.1 Page 68