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EDI88128LPSXTI

EDI88128LPSXTI

  • 厂商:

    WEDC

  • 封装:

  • 描述:

    EDI88128LPSXTI - 128Kx8 Monolithic SRAM, SMD 5962-89598 - White Electronic Designs Corporation

  • 数据手册
  • 价格&库存
EDI88128LPSXTI 数据手册
White Electronic Designs 128Kx8 Monolithic SRAM, SMD 5962-89598 FEATURES Access Times of 15*, 17, 20, 25, 35, 45, 55ns CS# and OE# Functions for Bus Control 2V Data Retention (EDI88128LPS) TTL Compatible Inputs and Outputs Fully Static, No Clocks Organized as 128Kx8 Commercial, Industrial and Military Temperature Ranges Thru-hole and Surface Mount Packages JEDEC Pinout • 32 pin Ceramic DIP, 400 mil (Package 102) • 32 pin Ceramic DIP, 600 mil (Package 9) • 32 lead Ceramic ZIP (Package 100) • 32 lead Ceramic SOJ (Package 140) EDI88128CS • 32 pad Ceramic LCC (Package 141) • 32 lead Ceramic Flatpack (Package 142) Single +5V (±10%) Supply OperationThe EDI88128CS is a high speed, high performance, 128Kx8 megabit density Monolithic CMOS Static RAM. The device has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. A Low Power version with 2V Data Retention (EDI88128LPS) is also available for battery back-up opperation. Military product is available compliant to MIL-PRF-38535. * 15ns access time is advanced information, contact factory for availability. This product is subject to change without notice. FIGURE 1 – PIN CONFIGURATION 32 32 32 32 DIP SOJ LCC FLATPACK PIN DESCRIPTION I/O0-7 A0-16 WE# CS# OE# VCC VSS NC Data Inputs/Outputs Address Inputs Write Enable Chip Select Output Enable Power (+5V ±10%) Ground Not Connected 32 ZIP TOP VIEW NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 VCC 31 A15 30 NC 29 WE# 28 A13 27 A8 26 A9 25 A11 24 OE# 23 A10 22 CS# 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS TOP VIEW 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 VCC 4 A15 6 NC 8 WE# 10 A13 12 A8 14 A9 16 A11 18 OE# 20 A10 22 CS# 24 I/O7 26 I/O6 28 I/O5 30 I/O4 32 I/O3 BLOCK DIAGRAM Memory Array A0-16 Address Buffer Address Decoder I/O Circuits I/O0-7 WE# CS# OE# White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2000 Rev. 10 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Military Storage Temperature, Plastic Power Dissipation Output Current Junction Temperature, TJ -0.5 to 7.0 0 to +70 -40 to +85 -55 to +125 -65 to +150 1.5 20 175 Unit V °C °C °C °C W mA °C OE# X H L X CS# H L L L WE# X H H L Mode Standby Output Deselect Read Write EDI88128CS TRUTH TABLE Output High Z High Z Data Out Data In Power Icc2, Icc3 Icc1 Icc1 Icc1 Recommended Operating Conditions Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 — — Max 5.5 0 VCC +0.5 +0.8 Unit V V V V NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE TA = +25°C Parameter Symbol Condition Max LLC Address Lines Data Lines CI CO VIN = VCC or VSS, f = 1.0MHz VOUT = VCC or VSS, f = 1.0MHz 12 14 CSOJ, ZIP, DIP, Flatpack Unit pF pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS VCC = 5.0V, -55°C ≤ TA ≤ +125°C Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Standby (TTL) Power Supply Current Symbol ILI ILO Icc1 Icc2 Conditions VIN = 0V to VCC VI/O = 0V to VCC WE#, CS# = VIL, II/O = 0mA, CS2 = VIH CS# ≥ VIH, VIN ≤ VIH or ≥ VIL CS# ≥ VCC -0.2V VIN ≥ VCC -0.2V or VIN ≤ 0.2V IOL = 8.0mA IOH = -4.0mA (15-17ns) (20ns) (25-55ns) (17-55ns) (15ns) CS (17-55ns) CS (15ns) LPS Min — — — — — — — — — — — 2.4 Typ — — Max ±5 ±10 300 225 200 25 60 10 15 5 0.4 — Units µA µA mA mA mA mA mA mA mA mA V V Full Standby Power Supply Current Output Low Voltage Output High Voltage NOTE: DC test conditions : VIL = 0.3V, VIH = VCC -0.3V Icc3 VOL VOH 3 — — — — White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2000 Rev. 10 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC CHARACTERISTICS – READ CYCLE (15 to 20ns) VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C 15ns* Alt. tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ tPU tPD 0 15 0 6 0 17 0 6 0 6 0 3 8 0 6 0 Min 15 15 15 3 8 0 Max Min 17 17 17 3 Parameter EDI88128CS Symbol JEDEC tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ tELICCH tEHICCL 17ns Max Min 20 20ns Max Units Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Chip Enable to Power Up (1) Chip Enable to Power Down (1) 1. This parameter is guaranteed by design but not tested. ns 20 20 10 8 8 20 ns ns ns ns ns ns ns ns ns ns AC CHARACTERISTICS – READ CYCLE (25 to 55ns) VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C 25ns Alt. tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ tPU tPD 0 25 0 10 0 35 0 10 0 15 0 45 3 12 0 15 0 20 0 55 Min 25 25 25 3 20 0 20 0 20 Max Min 35 35 35 3 20 0 25 Symbol Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Chip Enable to Power Up (1) Chip Enable to Power Down (1) 1. This parameter is guaranteed by design but not tested. JEDEC tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ tELICCH tEHICCL 35ns Max Min 45 45ns Max 45 45 3 Min 55 55ns Max 55 55 20 Units ns ns ns ns ns ns ns ns ns ns ns AC TEST CONDITIONS Figure 1 Vcc Figure 2 Vcc Input Pulse Levels 480Ω 480Ω VSS to 3.0V 5ns 1.5V Figure 1 Q 255Ω 30pF Q 255Ω 5pF Input Rise and Fall Times Input and Output Timing Levels Output Load NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2 White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2000 Rev. 10 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC CHARACTERISTICS – WRITE CYCLE (15 to 20ns) VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C 15ns* Min 15 12 12 0 0 12 12 12 12 0 0 0 0 0 7 7 3 Max Min 17 13 13 0 0 13 13 13 13 0 0 0 0 0 8 8 3 Symbol JEDEC Alt. tWC tAVAV tELWH tCW tELEH tCW tAVWL tAS tAVEL tAS tAW tAVWH tAVEH tAW tWLWH tWP tWLEH tWP tWHAX tWR tEHAX tWR tWHDX tDH tEHDX tDH tWHZ tWLQZ tDVWH tDW tDVEH tDW tWHQX tWLZ 17ns Max EDI88128CS 20ns Min 20 15 15 0 0 15 15 15 15 0 0 0 0 0 10 10 3 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) 1. This parameter is guaranteed by design but not tested. 7 8 8 AC CHARACTERISTICS – WRITE CYCLE (25 to 55ns) VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C Min 25 20 20 0 0 20 20 20 20 0 0 0 0 0 15 15 3 25ns Max Min 35 25 25 0 0 25 25 30 30 0 0 0 0 0 20 20 3 Symbol JEDEC Alt. tAVAV tWC tCW tE1LWH tELEH tCW tAVWL tAS tAVEL tAS tAVWH tAW tAVEH tAW tWLWH tWP tWLEH tWP tWR tWHAX tEHAX tWR tWHDX tDH tEHDX tDH tWLQZ tWHZ tDVWH tDW tDVEH tDW tWHQX tWLZ 35ns Max 45ns Max 55ns Max Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) 1. This parameter is guaranteed by design but not tested. 10 13 Min 45 35 35 0 0 35 35 30 30 5 5 0 0 0 20 20 3 15 Min 55 45 45 0 0 45 45 35 35 5 5 0 0 0 25 25 3 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2000 Rev. 10 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 2 – TIMING WAVEFORM - READ CYCLE tAVAV ADDRESS EDI88128CS tAVAV ADDRESS tAVQV CS# ADDRESS 2 ADDRESS 1 tAVQV DATA I/O tAVQX Icc DATA 1 DATA 2 tELQV tELQX tELICCH tEHQZ tEHICCL OE# READ CYCLE 1 (WE# HIGH; OE#, CS# LOW) tGLQV tGLQX DATA I/O READ CYCLE 2 (WE# HIGH) tGHQZ FIGURE 3 – WRITE CYCLE - WE# CONTROLLED tAVAV ADDRESS tAVWH tELWH CS# tWHAX tAVWL WE# tWLWH tDVWH tWHDX DATA IN DATA VALID tWLQZ DATA OUT HIGH Z tWHQX WRITE CYCLE 1, WE# CONTROLLED FIGURE 4 – WRITE CYCLE - CS# CONTROLLED tAVAV ADDRESS tAVEH tELEH CS# tEHAX tAVEL WE# tWLEH tDVEH tEHDX DATA IN DATA OUT HIGH Z DATA VALID WRITE CYCLE 2, CS# CONTROLLED White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2000 Rev. 10 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DATA RETENTION CHARACTERISTICS (EDI88128LPA only) -55°C ≤ TA ≤ +125°C Conditions VCC = 2.0V CS# ≥ VCC -0.2V VIN ≥ VCC -0.2V or VIN ≤ 0.2V Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time (1) Operation Recovery Time (1) NOTE: 1. Parameter guaranteed by design, but not tested. * Read Cycle Time EDI88128CS Sym VCC ICCDR TCDR TR Min 2 – 0 TAVAV* Typ – 0.5 – – Max – 2 – – Units V mA ns ns FIGURE 5 – DATA RETENTION - CS# CONTROLLED Data Retention Mode Vcc 4.5V VCC 4.5V tCDR CS# CS# = VCC -0.2V tR DATA RETENTION, CS# CONTROLLED White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2000 Rev. 10 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88128CS PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600mils wide) 1.616 1.584 Pin 1 Indicator 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500 0.060 0.040 0.620 0.600 0.100 TYP 0.155 0.115 0.600 NOM ALL DIMENSIONS ARE IN INCHES PACKAGE 100: 32 LEAD CERAMIC ZIP 1.65 MAX 0.125 MAX 0.500 MAX 0.155 0.125 0.050 31 x 0.050 = 1.550 0.040 MIN 0.040 0.020 0.100 NOM ALL DIMENSIONS ARE IN INCHES PACKAGE 102: 32 PIN SIDEBRAZED CERAMIC DIP (400mils wide) 1.616 1.584 Pin 1 Indicator 0.175 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500 0.060 0.040 0.420 0.400 0.100 TYP 0.155 0.115 0.400 NOM ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2000 Rev. 10 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PACKAGE 140: 32 LEAD CERAMIC SOJ 0.010 0.006 0.019 0.015 EDI88128CS 0.840 0.820 0.444 0.430 0.379 0.155 0.106 0.050 TYP ALL DIMENSIONS ARE IN INCHES PACKAGE 141: 32 PAD CERAMIC LCC 0.096 0.080 0.028 0.022 0.840 0.820 0.405 0.395 0.050 TYP ALL DIMENSIONS ARE IN INCHES PACKAGE 142: 32 PIN CERAMIC FLATPACK 0.830 0.810 0.007 0.003 0.370 0.250 1.00 REF 0.290 0.270 0.040 0.030 0.019 0.015 0.116 0.100 0.420 0.400 Pin 1 0.045 0.020 0.050 TYP ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2000 Rev. 10 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ORDERING INFORMATION EDI88128CS EDI 8 8 128 CS X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 128Kx8 TECHNOLOGY: CS = CMOS Standard Power LPS = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) F = 32 lead Ceramic Flatpack (Package 142) L = 32 pad Ceramic LCC (Package 141) N = 32 lead Ceramic SOJ (Package 140) T = 32 lead Sidebrazed DIP, 400 mil (Package 102) Z = 32 lead Ceramic ZIP (Package 100) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2000 Rev. 10 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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