EDI88130CXNB

White Electronic Designs 128Kx8 MONOLITHIC SRAM, SMD 5962-89598 FEATURES Access Times of 70, 85, 100ns Available with Single Chip Selects (EDI88128) or Dual Chip Selects (EDI88130) 2V Data Retention (LP Versions) CS# and OE# Functions for Bus Control TTL Compatible Inputs and Outputs Fully Static, No Clocks Organized as 128Kx8 Industrial, Military and Commercial Temperature Ranges Thru-hole and Surface Mount Packages JEDEC Pinout • 32 pin Ceramic DIP, 0.6 mils wide (Package 9) • 32 lead Ceramic SOJ (Package 140) Single +5V (±10%) Supply Operation EDI88128C The EDI88128C is a high speed, high performance, Monolithic CMOS Static RAM organized as 128Kx8. The device is also available as EDI88130C with an additional chip select line (CS2) which will automatically power down the device when proper logic levels are applied. The second chip select line (CS2) can be used to provide system memory security during power down in non-battery backed up systems and simplifiy decoding schemes in memory banking where large multiple pages of memory are required. The EDI88128C and the EDI88130C have eight bidirectional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. Low power versions, EDI88128LP and EDI88130LP, offer a 2V data retention function for battery back-up opperation. Military product is available compliant to Appendix A of MIL-PRF-38535. FIGURE 1 – PIN CONFIGURATION 32 DIP 32 SOJ PIN DESCRIPTION I/O0-7 A0-16 WE# CS1#, CS2 OE# VCC VSS NC Data Inputs/Outputs Address Inputs Write Enable Chip Selects Output Enable Power (+5V ±10%) Ground Not Connected Top View NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ I/OØ I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 VCC 31 A15 30 NC/CS2* 29 WE# 28 A13 27 A8 26 A9 25 A11 24 OE# 23 A10 22 CS1# 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 BLOCK DIAGRAM * Pin 30 is NC for 88128 or CS2 for 88130. April 2005 Rev. 17 WE# CS1# CS2 OE# White Electronic Designs Corp. reserves the right to change products or specifications without notice. 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Military Storage Temperature, Plastic Power Dissipation Output Current Junction Temperature, TJ -0.5 to 7.0 0 to +70 -40 to +85 -55 to +125 -65 to +150 1 20 175 Unit V °C °C °C °C W mA °C OE# CS1# CS2# WE# Mode X H X X Standby X X L X Standby X X L X Output Deselect H L H H Output Deselect L L H H Read X L H L Write EDI88128C TRUTH TABLE Output High Z High Z High Z High Z Data Out Data In Power Icc2, Icc3 Icc2, Icc3 Icc1 Icc1 Icc1 Icc1 NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 — — Max 5.5 0 VCC +0.5 +0.8 Unit V V V V CAPACITANCE TA = +25°C Symbol Parameter Address Lines CI Input/Output Lines CO Condition VIN = VCC or VSS, f = 1.0MHz VOUT = VCC or VSS, f = 1.0MHz Max Unit 12 pF 14 pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS VCC = 5V, -55°C ≤ TA ≤ +125°C Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current Output Low Voltage Output High Voltage Symbol Conditions VIN = 0V to VCC ILI ILO VI/O = 0V to VCC, CS1# ≥ VIH and/or CS2# ≤ VIL WE#, CS1# = VIL, II/O = 0mA, Min Cycle (70-85ns) ICC1 CS2# = VIH (100ns) ICC2 CS1# ≥ VIH and/or CS2# ≤ VIL, VIN ≥ VIH or ≤ VIL CS1# ≥ VCC -0.2V and/or CS2# ≤ VCC+0.2V C ICC3 VIN ≥ VCC -0.2V or VIN ≤ 0.2V LP VOL IOL = 2.1mA VOH IOH = -1.0mA Min -5 -10 — — — — — — 2.4 Typ — — Max +5 +10 120 110 10 5 1 0.4 — Units µA µA mA mA mA mA mA V V 1 — — — NOTE: DC test conditions : VIL = 0.3V, VIH = VCC -0.3V White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 17 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC Characteristics – Read Cycle VCC = 5V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z (1) 1. This parameter is guaranteed by design but not tested. EDI88128C Symbol JEDEC tAVAV tAVQV tELQV tSHQV tELQX tSHQX tEHQZ tSLQZ tAVQX tGLQV tGLQX tGHQZ Alt. tRC tAA tACS tACS tCLZ tCLZ tCHZ tCHZ tOH tOE tOLZ tOHZ Min 70 70ns Max 70 70 70 3 3 30 30 3 25 0 0 30 0 0 3 3 3 Min 85 85ns Max 85 85 85 3 3 30 30 3 30 30 0 0 Min 100 100ns Max 100 100 100 Units ns ns ns ns ns ns ns ns ns ns ns ns 30 30 50 30 AC Test Conditions Figure 1 Figure 2 Vcc Vcc 480Ω 480Ω Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V Figure 1 Q 255Ω 30pF Q 255Ω 5pF NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2 White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 17 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC CHARACTERISTICS – WRITE CYCLE VCC = 5V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Write Cycle Time Chip Select to End of Write Symbol JEDEC tAVAV tELWH tELEH tSHWH tSHSL tAVWL tAVEL tAVSH tAVWH tWLWH tWLEH tWLSL tWHAX tEHAX tSLAX tWHDX tEHDX tSLDX tWLQZ tDVWH tDVEH tDVSL tWHQX Alt. tWC tCW tCW tCW tCW tAS tAS tAS tAW tWP tWP tWP tWR tWR tWR tDH tDH tDH tWHZ tDW tDW tDW tWLZ Min 70 60 60 60 60 0 0 0 60 35 35 35 5 5 5 0 0 0 0 35 35 35 5 30 70ns Max Min 85 75 75 75 75 0 0 0 75 70 70 70 5 5 5 0 0 0 0 40 40 40 5 35 85ns Max Min 100 85 85 85 85 0 0 0 85 80 80 80 5 5 5 0 0 0 0 40 40 40 5 EDI88128C 100ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time 40 ns ns ns ns ns Output Active from End of Write (1) 1. This parameter is guaranteed by design but not tested. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 17 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 2 – TIMING WAVEFORM — READ CYCLE tAVAV ADDRESS EDI88128C tAVQV CS1# tAVAV ADDRESS ADDRESS 1 ADDRESS 2 tELQV tELQX CS2 tEHQZ tAVQV DATA I/O tAVQX DATA 1 DATA 2 tSHQV tSHQX OE# tSLQZ tGLQV tGLQX DATA I/O READ CYCLE 2 (WE# HIGH) tGHQZ READ CYCLE 1 (WE# HIGH; OE#, CS# LOW) FIGURE 3 – WRITE CYCLE 1 tAVAV ADDRESS tAVWL WE# tAVWH tWLWH tWHAX CS1# tELWH CS2 tSHWH DATA IN tDVWH DATA VALID tWHQX tWHDX tWLQZ DATA OUT HIGH Z WRITE CYCLE 1 - LATE WRITE, WE# CONTROLLED FIGURE 4 – WRITE CYCLE 2 tAVAV ADDRESS WRITE CYCLE 3 tAVAV ADDRESS tAVEL WE# tWLEH tEHAX WE# tAVSH tWLSL tSLAX tELEH CS1# tSHSL CS1# CS2 CS2 tDVEH DATA IN DATA VALID tEHDX DATA IN tDVSL DATA VALID tSLDX WRITE CYCLE 2 - EARLY WRITE, CS1# CONTROLLED WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 17 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs -55°C ≤ TA ≤ +125°C Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time (1) Operation Recovery Time (1) NOTE: 1. Parameter guaranteed by design, but not tested. * Read Cycle Time EDI88128C DATA RETENTION CHARACTERISTICS (EDI88128LP & EDI88130LP ONLY) Symbol VDD ICCDR TCDR TR Conditions VDD = 2.0V CS1# ≥ VDD -0.2V VIN ≥ VDD -0.2V or VIN ≤ 0.2V Min 2 – 0 TAVAV* Typ – – – – Max – 400 – – Units V µA ns ns FIGURE 5 – DATA RETENTION – CS1# CONTROLLED Data Retention Mode Vcc 4.5V VDD 4.5V tCDR CS1# CS1# VDD -0.2V tR DATA RETENTION, CS1# CONTROLLED FIGURE 6 – DATA RETENTION — CS2 CONTROLLED Data Retention Mode Vcc 4.5V VDD 4.5V tCDR CS2 CS2 ≤ 0.2V tR DATA RETENTION, CS2 CONTROLLED White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 17 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88128C PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600MILS WIDE) 1.616 1.584 Pin 1 Indicator 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500 0.060 0.040 0.620 0.600 0.155 0.100 0.115 TYP 0.600 NOM ALL DIMENSIONS ARE IN INCHES PACKAGE 140: 32 LEAD CERAMIC SOJ 0.010 0.006 0.019 0.015 0.840 0.820 0.444 0.430 0.379 0.155 0.106 0.050 TYP ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 17 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ORDERING INFORMATION EDI88128C EDI 8 8 128 C X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 128Kx8 8 130 = Dual Chip Select TECHNOLOGY: C = CMOS Standard Power LP = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) N = 32 lead Ceramic SOJ (Package 140) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 2005 Rev. 17 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com