EDI88512CAXCC

White Electronic Designs 512Kx8 Monolithic SRAM, SMD 5962-95600 FEATURES Access Times of 15, 17, 20, 25, 35, 45, 55ns Data Retention Function (LPA version) TTL Compatible Inputs and Outputs Fully Static, No Clocks Organized as 512Kx8 Commercial, Industrial and Military Temperature Ranges 32 lead JEDEC Approved Evolutionary Pinout • Ceramic Sidebrazed 600 mil DIP (Package 9) • Ceramic Sidebrazed 400 mil DIP (Package 326) • Ceramic 32 pin Flatpack (Package 344) • Ceramic Thin Flatpack (Package 321) • Ceramic SOJ (Package 140) 36 lead JEDEC Approved Revolutionary Pinout • Ceramic Flatpack (Package 316) • Ceramic SOJ (Package 327) • Ceramic LCC (Package 502) Single +5V (±10%) Supply Operation *This product is subject to change without notice. EDI88512CA The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. All 32 pin packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128CS. Pins 1 and 30 become the higher order addresses. The 36 pin revolutionary pinout also adheres to the JEDEC standard for the four megabit device. The center pin power and ground pins help to reduce noise in high performance systems. The 36 pin pinout also allows the user an upgrade path to the future 2Mx8. A Low Power version with Data Retention (EDI88512LPA) is also available for battery backed applications. Military product is available compliant to Appendix A of MILPRF-38535. FIG. 1 PIN CONFIGURATION 32 PIN TOP VIEW 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE# I/O7 I/O6 Vss Vcc I/O5 I/O4 A14 A13 A12 A11 A10 NC PIN DESCRIPTION I/O0-7 A0-18 36 PIN TOP VIEW A0 A1 A2 A3 A4 CS# I/O0 I/O1 Vcc Vss I/O2 I/O3 WE# A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 36 pin 9 Revolutionary 10 11 12 13 14 15 16 17 18 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 pin Evolutionary 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 A17 WE# A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 WE# CS# OE# VCC VSS NC Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power (+5V ±10%) Ground Not Connected BLOCK DIAGRAM Memory Array A0-18 Address Buffer Address Decoder I/O Circuits I/O0-7 WE# CS# OE# White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Commercial Industrial Military Storage Temperature, Plastic Power Dissipation Output Current Junction Temperature, TJ 0 ≤ TA ≤ +70 -40 ≤ TA ≤ +85 -55 ≤ TA ≤ +125 -65 ≤ TA ≤ +150 1.5 20 175 °C °C °C °C W mA °C Value -0.5 ≤ TA ≤ 7.0 Unit V OE# X H L X CS# H L L L WE# X H H L EDI88512CA TRUTH TABLE Mode Standby Output Deselect Read Write Output High Z High Z Data Out Data In Power Icc2, Icc3 Icc1 Icc1 Icc1 RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 — — Max 5.5 0 3.0 +0.8 Unit V V V V NOTE: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C) Parameter Address Lines Data Lines Symbol CI CO Condition VIN = Vcc or Vss, f = 1.0MHz VOUT = Vcc or Vss, f = 1.0MHz Max 12 14 Unit pF pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS (VCC = 5V, TA = -55°C to +125°C) Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current Output Low Voltage Output High Voltage NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V Symbol ILI ILO ICC1 ICC2 ICC3 VOL VOH VIN = 0V to VCC VI/O = 0V to VCC Conditions Min -10 -10 (17ns) (20 -55ns) — — — CA LPA — — — 2.4 Max 10 10 250 225 60 25 20 0.4 — Units A A mA mA mA mA mA V V WE#, CS# = VIL, II/O = 0mA, Min Cycle CS# ≥ VIH, VIN ≤ VIL, VIN ≥ VIH CS# ≥ VCC -0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V IOL = 6.0mA IOH = -4.0mA AC TEST CONDITIONS Figure 1 Vcc Figure 2 Input Pulse Levels Vcc VSS to 3.0V 5ns 1.5V Figure 1 Input Rise and Fall Times Input and Output Timing Levels 480 Ω 480 Ω Output Load NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2) Q 255 Ω 30pF Q 255 Ω 5pF White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC CHARACTERISTICS – READ CYCLE (VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C) 15ns Min 15 15 15 2 0 0 8 0 0 7 0 0 7 7 3 0 0 8 0 0 8 7 Max 17ns Min 17 17 17 3 0 0 10 0 0 10 8 Max 20ns Min 20 20 20 3 0 0 12 0 0 15 10 Max Symbol Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) JEDEC tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ Alt. tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ 25ns Min 25 25 25 3 0 0 15 15 Max 35ns Min 35 35 35 Max EDI88512CA 45ns Min 45 45 45 3 0 0 25 0 0 20 0 0 20 3 0 0 Max 55ns Min 55 55 55 20 30 20 Max Units ns ns ns ns ns ns ns ns ns 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS – WRITE CYCLE (VCC = 5.0V, VSS = 0V, -55°C≤ TA ≤ +125°C) 15ns Min 15 13 13 0 0 13 13 13 13 0 0 0 0 0 8 8 0 8 Max 17ns Min 17 14 14 0 0 14 14 14 14 0 0 0 0 0 8 8 0 8 Max 20ns Min 20 15 15 0 0 15 15 15 15 0 0 0 0 0 10 10 0 8 Max Symbol Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) JEDEC tAVAV tELWH tELEH tAVWL tAVEL tAVWH tAVEH tWLWH tWLEH tWHAX tEHAX tWHDX tEHDX tWLQZ tDVWH tDVEH tWHQX Alt. tWC tCW tCW tAS tAS tAW tAW tWP tWP tWR tWR tDH tDH tWHZ tDW tDW tWLZ 25ns Min Max 25 17 17 0 0 17 17 17 17 0 0 0 0 0 12 12 0 10 35ns Min 35 25 25 0 0 25 25 25 25 0 0 0 0 0 20 20 0 25 Max 45ns Min 45 30 30 0 0 30 30 30 30 0 0 0 0 0 25 25 0 30 Max 55ns Min 55 50 50 0 0 50 50 45 45 0 0 0 0 0 40 30 0 30 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1. This parameter is guaranteed by design but not tested. White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIG. 2 TIMING WAVEFORM - READ CYCLE tAVAV ADDRESS EDI88512CA tAVQV tAVAV ADDRESS ADDRESS 1 ADDRESS 2 CS# tELQV tELQX OE# tEHQZ tAVQV DATA I/O tAVQX DATA 1 DATA 2 tGLQV tGLQX DATA OUT tGHQZ READ CYCLE 1 (WE# HIGH; OE#, CS# LOW) READ CYCLE 2 (WE# HIGH) FIG. 3 WRITE CYCLE - WE# CONTROLLED tAVAV ADDRESS tAVWH tELWH CS# tWHAX tAVWL WE# tWLWH tDVWH tWHDX DATA IN DATA VALID tWLQZ DATA OUT HIGH Z tWHQX WRITE CYCLE 1, WE# CONTROLLED FIG. 4 WRITE CYCLE - CS# CONTROLLED tAVAV ADDRESS tAVEH tELEH CS# tEHAX tAVEL WE# tWLEH tDVEH tEHDX DATA IN DATA OUT HIGH Z DATA VALID WRITE CYCLE 2, CS# CONTROLLED White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DATA RETENTION CHARACTERISTICS (EDI88512LPA ONLY) (-55°C ≤ TA ≤ +125°C) Conditions VCC = 2.0V CS# ≥ VCC -0.2V VIN ≥ VCC -0.2V or VIN ≤ 0.2V Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time Operation Recovery Time Sym VCC ICCDR tCDR TR Min 2 – 0 tAVAV Typ – – – – Max – 2 – – EDI88512CA Units V mA ns ns FIG. 5 DATA RETENTION - CS# CONTROLLED DATA RETENTION MODE VCC tCDR CS# CS# = VCC -0.2V 4.5V VCC WS32K32-XHX 4.5V tR DATA RETENTION, CS# CONTROLLED White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA PACKAGE 9: 32 LEAD SIDEBRAZED CERAMIC DIP, SMD 5962-95600XXMXA 1.616 1.584 Pin 1 Indicator 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500 0.060 0.040 0.155 0.115 0.620 0.600 0.100 TYP 0.600 NOM ALL DIMENSIONS ARE IN INCHES PACKAGE 326: 32 LEAD SIDEBRAZED CERAMIC DIP 1.616 1.584 Pin 1 Indicator 1 0.420 0.400 1 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500 0.100 TYP 0.155 0.115 0.400 NOM ALL DIMENSIONS ARE IN INCHES PACKAGE 140: 32 LEAD CERAMIC SOJ, SMD 5962-95600XXMUA 0.010 0.006 0.019 0.015 0.840 0.820 0.444 0.430 0.379 0.155 0.106 0.050 TYP ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PACKAGE 316: 36 PIN CERAMIC FLATPACK, SMD 5962-95600XXMTA 0.920 ± 0.010 0.007 0.003 0.370 0.250 1.00 REF 0.395 0.385 EDI88512CA 0.515 0.505 Pin 1 0.040 0.030 0.019 0.015 0.125 0.100 0.045 0.020 0.050 TYP ALL DIMENSIONS ARE IN INCHES PACKAGE 321: 32 PIN THINPACK™ FLATPACK, SMD 5962-95600XXMYA 0.838 MAX 0.567 0.427 0.559 0.429 0.050 TYP 0.016 ± 0.008 0.008 0.005 0.020 0.030 0.118 MAX. ALL DIMENSIONS ARE IN INCHES PACKAGE 344: 32 PIN CERAMIC FLATPACK, SMD 5962-95600XXM9A +0.002 0.006 -0.001 0.423 ± 0.004 0.024 REF. 0.112 MAX. 0.838 MAX. 0.016 ± 0.008 0.050 ± 0.002 TYP. 0.300 ± 0.010 ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PACKAGE 327: 36 LEAD CERAMIC SOJ, SMD 5962-95600XXMMA 0.010 0.006 0.019 0.015 EDI88512CA 0.920 0.940 0.050 TYP 0.444 0.434 0.379 0.155 0.106 ALL DIMENSIONS ARE IN INCHES PACKAGE 502: 36 LEAD CERAMIC LCC, SMD 5962-95600XXMNA (PENDING) 0.100 0.080 0.135 0.115 36 1 0.100 TYP 0.009 TYP 0.028 0.022 0.930 0.910 0.860 0.840 0.050 BSC 0.460 0.445 0.066 0.054 ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ORDERING INFORMATION EDI 8 8 512 WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 512Kx8 TECHNOLOGY: CA = CMOS Standard Power LPA = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) K = 36 lead Ceramic LCC (Package 502) N = 32 lead Ceramic SOJ (Package 140) T = 32 lead Sidebrazed DIP, 400 mil (Package 326) B32 = 32 pin Ceramic Thinpack™ Flatpack (Package 321) F32 = 32 pin Ceramic Flatpack (Package 344) F36 = 36 pin Ceramic Flatpack (Package 316) N36 = 36 lead Ceramic SOJ (Package 327) DEVICE GRADE: B = MIL-STD-883 Compliant M I C = Military Screened = Industrial = Commercial -55°C ≤ TA ≤ +125°C -40°C ≤ TA ≤ +85°C 0°C ≤ TA ≤ +70°C EDI88512CA CA X X X White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com