EDI88512LPXNC

White Electronic Designs 512Kx8 Monolithic SRAM, CMOS FEATURES 512Kx8 bit CMOS Static Random Access Memory • Access Times of 70, 85, 100ns • Data Retention Function (LP version) • TTL Compatible Inputs and Outputs • Fully Static, No Clocks 32 lead JEDEC Approved Evolutionary Pinout • Ceramic Sidebrazed 600 mil DIP (Package 9) • Ceramic SOJ (Package 140) Single +5V (±10%) Supply Operation * This product is subject to change without notice. EDI88512C The EDI88512C is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. Both the DIP and CSOJ packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128C. Pins 1 and 30 become the higher order addresses. A Low Power version with Data Retention (EDI88512LP) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL-PRF38535. FIGURE 1 – PIN CONFIGURATION 32 PIN TOP VIEW PIN DESCRIPTION I/O0-7 A0-18 WE# CS# OE# VCC VSS NC Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power (+5V ±10%) Ground Not Connected A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 pin Evolutionary 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 A17 WE# A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 A0-18 BLOCK DIAGRAM Memory Array Address Buffer Address Decoder I/O Circuits I/O0-7 WE# CS# OE# White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2001 Rev. 11 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Commercial Industrial Military Storage Temperature, Plastic Power Dissipation Output Current Junction Temperature, TJ Value -0.5 to 7.0 0 to +70 -40 to +85 -55 to +125 -65 to +150 1 20 175 Unit V °C °C °C °C W mA °C OE# X H L X CS# H L L L WE# X H H L Mode Standby Output Deselect Read Write EDI88512C TRUTH TABLE Output High Z High Z Data Out Data In Power ICC2, ICC3 ICC1 ICC1 ICC1 RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 — — Max 5.5 0 VCC +0.5 +0.8 Unit V V V V NOTE: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE TA = +25°C Parameter Address Lines Data Lines Symbol CI CO Condition VIN = Vcc or Vss, f = 1.0MHz VOUT = Vcc or Vss, f = 1.0MHz Max 12 14 Unit pF pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS VCC = 5V, -55°C ≤ *TA ≤ +125°C Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current Output Low Voltage Output High Voltage NOTE: DC test conditions: Vil = 0.3V, Vih = Vcc -0.3V Symbol ILI ILO ICC1 ICC2 ICC3 VOL VOH Conditions VIN = 0V to VCC VI/O = 0V to VCC WE#, CS# = VIL, II/O = 0mA, Min Cycle (70-100ns) CS# ≥ VIH, VIN ≤ VIL, VIN ≥ VIH CS# ≥ VCC -0.2V C VIN ≥ Vcc -0.2V or VIN ≤ 0.2V LP IOL = 2.1mA IOH = -1.0mA Min — — — — — — — 2.4 Typ* — — 45 3 — — — — Max ±10 ±10 75 10 5 2 0.4 — Units µA µA mA mA mA mA V V AC TEST CONDITIONS Figure 1 Vcc Figure 2 Input Pulse Levels Vcc VSS to 3.0V 5ns 1.5V Figure 1 Input Rise and Fall Times 480Ω 480Ω Input and Output Timing Levels Output Load Q 255Ω 30pF Q 255Ω 5pF NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2 White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2001 Rev. 11 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC CHARACTERISTICS – READ CYCLE VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C 70ns Alt. tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ Min 70 Max 70 70 10 25 10 35 5 0 25 5 0 10 45 30 5 0 10 30 10 Min 85 Symbol Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) 1. This parameter is guaranteed by design but not tested. EDI88512C 85ns Max 85 85 10 Min 100 100ns Max 100 100 30 50 30 Units ns ns ns ns ns ns ns ns ns JEDEC tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ AC CHARACTERISTICS – WRITE CYCLE VCC = 5.0V, VSS = 0V, -55°C≤ TA ≤ +125°C 70ns Alt. tWC tCW tCW tAS tAS tAW tAW tWP tWP tWR tWR tDH tDH tWHZ tDW tDW tWLZ Min 70 60 60 0 0 65 65 50 50 0 0 0 0 0 40 30 5 Max Min 85 70 70 0 0 70 70 55 55 0 0 0 0 0 40 35 0 Symbol Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) 1. This parameter is guaranteed by design but not tested. 85ns Max Min 100 80 80 0 0 80 80 60 60 0 0 0 0 0 40 40 0 100ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns JEDEC tAVAV tELWH tELEH tAVWL tAVEL tAVWH tAVEH tWLWH tWLEH tWHAX tEHAX tWHDX tEHDX tWLQZ tDVWH tDVEH tWHQX 25 30 30 White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2001 Rev. 11 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 2 – TIMING WAVEFORM - READ CYCLE tAVAV ADDRESS EDI88512C tAVQV CS# tAVAV ADDRESS ADDRESS 1 ADDRESS 2 tELQV tELQX OE# tEHQZ tAVQV DATA I/O tAVQX DATA 1 DATA 2 tGLQV tGLQX DATA OUT tGHQZ READ CYCLE 1 (WE# HIGH; OE#, CS# LOW) READ CYCLE 2 (WE# HIGH) FIGURE 3 – WRITE CYCLE - WE# CONTROLLED tAVAV ADDRESS tAVWH tELWH CS# tWHAX tAVWL WE# tWLWH tDVWH tWHDX DATA IN DATA VALID tWLQZ DATA OUT HIGH Z tWHQX WRITE CYCLE 1, WE# CONTROLLED FIGURE 4 – WRITE CYCLE - CS# CONTROLLED tAVAV ADDRESS tAVEH tELEH CS# tEHAX tAVEL WE# tWLEH tDVEH tEHDX DATA IN DATA OUT HIGH Z DATA VALID WRITE CYCLE 2, CS# CONTROLLED White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2001 Rev. 11 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DATA RETENTION CHARACTERISTICS (EDI88512LP ONLY) -55°C ≤ TA ≤ +125°C Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time Operation Recovery Time Sym VCC ICCDR tCDR TR Conditions VCC = 2.0V CS# ≥ VCC -0.2V VIN ≥ VCC -0.2V or VIN ≤ 0.2V Min 2 – 0 tAVAV Typ – – – – EDI88512C Max – 185 – – Units V µA ns ns FIGURE 5 – DATA RETENTION - CS# CONTROLLED DATA RETENTION MODE VCC tCDR CS# CS# = VCC -0.2V 4.5V VCC 4.5V tR DATA RETENTION, CS# CONTROLLED White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2001 Rev. 11 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PACKAGE 9: 32 LEAD SIDEBRAZED CERAMIC DIP 1.616 1.584 EDI88512C Pin 1 Indicator 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500 0.060 0.040 0.620 0.600 0.100 TYP 0.155 0.115 0.600 NOM ALL DIMENSIONS ARE IN INCHES PACKAGE 140: 32 LEAD CERAMIC SOJ 0.010 0.006 0.019 0.015 0.840 0.820 0.444 0.430 0.379 0.155 0.106 0.050 TYP ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2001 Rev. 11 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ORDERING INFORMATION EDI88512C EDI 8 8 512 C X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 512Kx8 TECHNOLOGY: C = CMOS Standard Power LP = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) N = 32 lead Ceramic SOJ (Package 140) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2001 Rev. 11 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com