EDI8F81024C100BSC

White Electronic Designs 1Mx8 Static RAM CMOS, Module FEATURES 1024Kx8 bit CMOS Static Random Access Memory • • • • Access Times 70 thru 100ns Data Retention Function (EDI8F81024LP) TTL Compatible Inputs and Outputs Fully Static, No Clocks EDI8F81024C DESCRIPTION The EDI8F81024C is a 8Mb CMOS Static RAM based on eight 128Kx8 Static RAMs mounted on a multi-layered epoxy laminate (FR4) substrate. A version featuring Low Power with Data Retention (EDI8F81024LP) is also available. The EDI8F81024C is offered in a double sided, 36 pin single-in-line Package (SIP). Surface mount SIP technology is a cost effective solution to very high packing density requirements. All inputs and outputs are TTL compatible and operate from a single 5V supply. Fully asynchronous, the EDI8F81024C requires no clocks or refreshing for operation. High Density Packaging • 36 Pin SIP, No. 62 Single +5V (±10%) Supply Operation *This product is subject to change without notice. PIN CONFIGURATIONS AND BLOCK DIAGRAM NC VCC W# DQ2 DQ3 DQ0 A1 A2 A3 A4 VSS DQ5 A10 A11 A5 A13 A14 A19 E# A15 A16 A12 A18 A6 DQ1 VSS A0 A7 A8 A9 DQ7 DQ4 DQ6 A17 VCC G# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AØ-A19 E# W# G# DQØ-DQ7 VCC VSS NC A19 A18 A17 E# PIN NAMES Address Inputs Chip Enable Write Enable Output Enable Common Data Input/Output Power (+5V±10%) Ground No Connection DEC A0-A16 W# G# DQ0-DQ7 128K X8 128K X8 128K X8 128K X8 128K X8 128K X8 128K X8 128K X8 PIN OUT White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2002 Rev. 8 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Storage Temperature Plastic Power Dissipation Output Current -0.5V to 7.0V 0°C to +70°C -40°C to +85°C -55°C to +125°C 1 Watt 20 mA EDI8F81024C RECOMMENDED DC OPERATING CONDITIONS Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Sym VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 – – Max 5.5 0 6.0 0.8 Units V V V V AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF) *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VSS to 3.0V 5ns 1.5V 1TTL, CL = 100pF DC ELECTRICAL CHARACTERISTICS Parameter Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current (CMOS) Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage *Typical: TA = 25°C, VCC = 5.0V Sym ICC1 ICC2 ICC3 ILI ILO VOH VOL Conditions W#, E# = VIL, II/O = 0mA, Min Cycle E# ≥ VIH, VIN ≤ VIL or VIN ≥ VIH E# ≥ VCC-0.2V VIN ≥ VCC-0.2V or VIN ≤ 0.2V VIN = 0V to VCC V I/O = 0V to VCC IOH = -1.0mA IOL = 2.1mA C LP Min Typ* 80 40 10 400 Max 130 90 20 950 ±10 ±10 – 0.4 Units mA mA mA µA µA µA V V – – 2.4 – – – – – CAPACITANCE TRUTH TABLE G# X H L X E# H L L L W# X H H L Mode Standby Output Deselect Read Write Output HIGH Z HIGH Z DOUT DIN Power ICC2/ICC3 ICC1 ICC1 ICC1 Parameter Input Capacitance (Except DQ Pins) (f=1.0MHz, VIN=VCC or VSS) Sym CI CD/Q CC CW Max 58 43 10 60 Unit pF pF pF pF Capacitance (DQ Pins) Input (E#) Control Lines Input (W#) Line (G#) These parameters are sampled, not 100% tested. White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2002 Rev. 8 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC CHARACTERISTICS READ CYCLE Symbol Parameter Read Cycle Time Address Access Time Chip Enable Access Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Note 1: Parameter guaranteed, but not tested. EDI8F81024C 70ns Min 70 Max 70 70 5 30 3 40 0 30 0 3 5 Min 85 85ns Max 85 85 5 35 3 45 0 35 100ns Min 100 Max 100 100 40 50 40 Units ns ns ns ns ns ns ns ns ns JEDEC TAVAV TAVQV TELQV TELQX TEHQZ TAVQX TGLQV TGLQX TGHQZ Alt. TRC TAA TACS TCLZ TCHZ TOH TOE TOLZ TOHZ READ CYCLE 1 - W# HIGH, G#, E# LOW TAVAV A ADDRESS 1 TAVQV Q ADDRESS 2 TAVQX DATA 1 DATA 2 READ CYCLE 2 - W# HIGH TAVAV A TAVQV E# TELQV TELQX G# TGLQV TGLQX Q TGHQZ TEHQZ White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2002 Rev. 8 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC CHARACTERISTICS WRITE CYCLE Symbol Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Note 1: Parameter guaranteed, but not tested. EDI8F81024C 70ns Min 70 65 65 0 0 65 65 65 65 0 0 0 0 0 30 30 5 30 Max Min 85 70 70 0 0 70 70 70 70 0 0 0 0 0 35 35 5 85ns Max Min 100 80 80 0 0 80 80 80 80 0 0 0 0 35 0 40 40 5 100ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns 40 ns ns ns ns JEDEC TAVAV TELWH TELEH TAVWL TAVEL TAVWH TAVEH TWLWH TWLEH TWHAX TEHAX TWHDX TEHDX TWLQZ TDVWH TDVEH TWHQX Alt. TWC TCW TCW TAS TAS TAW TAW TWP TWP TWR TWR TDH TDH TWHZ TDW TDW TWLZ WRITE CYCLE 1 - W# CONTROLLED TAVAV A E# TELWH TAVWH TWLWH W# D TWLQZ Q HIGH Z TAVWL TDVWH TWHDX TWHQX DATA VALID TWHAX White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2002 Rev. 8 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WRITE CYCLE 2 - E# CONTROLLED TAVAV A TAVEL E# TAVEH TWLEH W# TDVEH D Q HIGH Z TEHDX DATA VALID EDI8F81024C TELEH TEHAX Characteristic Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time (1) Operation Recovery Time (1) Note 1: Parameter guaranteed, but not tested. * Read Cycle Time Sym VCC ICCDR TCDR TR Test Conditions VCC = 0.2V E# ≥ VCC -0.2V VIN ≥ VCC -0.2V or VIN ≤ 0.2V VCC Min 2 – – 0 TAVAV* Typ – 25 50 – – 70°C – 300 450 – – Max 85°C – 400 550 – – Unit V µA µA ns ns 2V 3V DATA RETENTION E# CONTROLLED DATA RETENTION MODE VCC TCDR 4.5V VCC 4.5V TR E# E#≥VDD-0.2V White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2002 Rev. 8 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ORDERING INFORMATION Standard Power EDI8F81024C70BSC EDI8F81024C85BSC EDI8F81024C100BSC Low Power with Data Retention EDI8F81024LP70BSC EDI8F81024LP85BSC EDI8F81024LP100BSC Speed (ns) 70 85 100 Package No. 62 62 62 EDI8F81024C Note: To order an Industrial grade product substitute the letter C in the Suffix with the letter I, e.g. EDI8F81024C70BSC becomes EDI8F81024C70BSI. PACKAGE DESCRIPTION PACKAGE NO. 62: 36 PIN SINGLE-IN-LINE PACKAGE 4.040 MAX. .050 .050 .575 MAX. .200 MAX. .175 .125 .100 TYP. 35 X .100 3.500 REF. ALL DIMENSIONS ARE IN INCHES .270 MAX. White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2002 Rev. 8 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com