EDI8L24129V10BI

White Electronic Designs 128Kx24 SRAM 3.3 Volt FEATURES 128Kx24 bit CMOS Static Random Access Memory Array • Fast Access Times: 10, 12, and 15ns • Master Output Enable and Write Control • TTL Compatible Inputs and Outputs • Fully Static, No Clocks Surface Mount Package • 119 Lead BGA (JEDEC MO-163), No. 391 • Small Footprint, 14mm x 22mm • Multiple Ground Pins for Maximum Noise Immunity Single +3.3V (±5%) Supply Operation DSP Memory Solution Motorola DSP5630xTM Analog Devices SHARCTM EDI8L24129V DESCRIPTION The EDI8L24129VxxBC is a 3.3V, three megabit SRAM constructed with three 128Kx8 die mounted on a multilayer laminate substrate. With 10 to 15ns access times, x24 width and a 3.3V operating voltage, the EDI8L24129V is ideal for creating a single chip memory solution for the Motorola DSP5630x (Figure 3) or a two chip solution for the Analog Devices SHARCTM DSP (Figure 4). The single or dual chip memory solutions offer improved system performance by reducing the length of board traces and the number of board connections compared to using multiple monolithic devices. For example, the capacitance load on the data lines for the BGA package is 58% less than a monolithic SOJ solution. The JEDEC Standard 119 lead BGA provides a 44% space savings over using 128Kx8, 300mil wide SOJs and the BGA package has a maximum height of 100 mils compared to 148 mils for the SOJ packages. The BGA package also allows the use of the same manufacturing and inspection techniques as the Motorola DSP, which is also in a BGA package. PIN CONFIGURATION A B C D E F G H I J K L M N O P Q 1 NC NC I/012 I/013 I/014 I/015 I/016 I/017 NC I/018 I/019 I/020 I/021 I/022 I/023 NC NC 2 AO A5 NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC A9 A13 3 A1 A6 NC GND VCC GND VCC GND VCC GND VCC GND VCC GND NC A10 A14 4 A2 E# NC GND GND GND GND GND GND GND GND GND GND GND NC W# G# 5 A3 A7 NC GND VCC GND VCC GND VCC GND VCC GND VCC GND NC A11 A15 6 A4 A8 NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC A12 A16 7 NC NC I/00 I/01 I/02 I/03 I/04 I/05 NC I/06 I/07 I/08 I/09 I/010 I/011 NC NC AØ-A16 E# W# G# DQØ-DQ23 VCC GND NC PIN NAMES Address Inputs Chip Enable Master Write Enable Master Output Enable Common Data Input/Output Power (3.3V±5%) Ground No Connection White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2005 Rev. 5 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs BLOCK DIAGRAM EDI8L24129V A0-A16 G# W# E# 17 128K x 24 Memory Array DQ0-DQ7 DQ8-DQ15 DQ16-DQ23 ABSOLUTE MAXIMUM RATINGS Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Storage Temperature Power Dissipation Output Current. Junction Temperature, TJ -0.5V to 4.6V 0°C to + 70°C -40°C to +85°C -55°C to +125°C 1.5 Watts 50 mA 175°C RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Sym VCC VSS VIH VIL Min 3.135 0 2.2 -0.3 Typ 3.3 0 – – Max 3.465 0 VCC+0.3 0.8 Units V V V V * Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE TRUTH TABLE G# X H L X E# H L L L W# X H H L Mode Standby Output Deselect Read Write Output High Z High Z DOUT DIN Power ICC2,ICC3 ICC1 ICC1 ICC1 f=1.0MHZ, VIN=VCC or VSS Parameter Address Lines Data Lines Write & Output Enable Lines Chip Enable Lines Sym CA CD/Q W#, G# EØ#-E2# Max 8 10 8 8 Unit pF pF pF pF These parameters are sampled, not 100% tested. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2005 Rev. 5 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DC ELECTRICAL CHARACTERISTICS Parameter Operating Power Supply Current Standby (TTL) Supply Current Full Standby CMOS Supply Current Input Leakage Current Output Leakage Current Output High Volltage Output Low Voltage Sym ICC1 ICC2 ICC3 ILI ILO VOH VOL Conditions W#= VIL, II/O = 0mA, Min Cycle E# > VIH, VIN < VIL or VIN > VIH, f=ØMHZ E# > VCC-0.2V VIN > VCC-0.2V or VIN < 0.2V VIN = 0V to VCC V I/O = 0V to VCC IOH = -4.0mA IOL = 8.0mA Min EDI8L24129V Max 10ns 420 90 10 ±10 ±10 12-15ns 360 75 10 ±10 ±10 0.4 Units mA mA mA µA µA V V 2.4 0.4 AC TEST CIRCUIT Figure 1 RL= 50Ω DOUT Z0= 50Ω 30pf VL=1.5V AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V Figure 1 (NOTE: For tEHQZ,tGHQZ and tWLQZ, Figure 2) Figure 2 +3.3V 319W DOUT 353Ω 5pf White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2005 Rev. 5 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC CHARACTERISTICS – READ CYCLE Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Note 1: Parameter guaranteed, but not tested. EDI8L24129V Symbol JEDEC tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ Alt. tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ Min 10 10ns Max 10 10 3 5 3 5 0 5 0 3 3 Min 12 12ns Max 12 12 3 6 3 6 0 6 Min 15 15ns Max 15 15 7 7 7 Units ns ns ns ns ns ns ns ns ns READ CYCLE – W# HIGH, G#, E# LOW tAVAV A ADDRESS 1 ADDRESS 2 tAVQV Q tAVQX DATA 1 DATA 2 READ CYCLE 2 – W# HIGH tAVAV A tAVQV E# tELQV tELQX G# tGLQV tGLQX Q White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2005 Rev. 5 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com tEHQZ tGHQZ White Electronic Designs AC CHARACTERISTICS – WRITE CYCLE Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Note 1: Parameter guaranteed, but not tested. EDI8L24129V Symbol JEDEC tAVAV tELWH tELEH tAVWL tAVEL tAVWH tAVEH tWLWH tWLEH tWHAX tEHAX tWHDX tEHDX tWLQZ tDVWH tDVEH tWHQX Alt. tWC tCW tCW tAS tAS tAW tAW tWP tWP tWR tWR tDH tDH tWHZ tDW tDW tWLZ Min 10 8 8 0 0 8 8 8 8 0 0 0 0 0 6 6 3 10ns Max Min 12 9 9 0 0 9 9 10 10 0 0 0 0 0 6 6 3 12ns Max Min 15 9 9 0 0 10 10 11 11 0 0 0 0 0 7 7 3 15ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 7 WRITE CYCLE – W# CONTROLLED tAVAV A E# tELWH tAVWH tWLWH W# tAVWL tDVWH tWHDX tWHAX D tWLQZ Q DATA VALID tWHQX HIGH Z White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2005 Rev. 5 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WRITE CYCLE 2 – E# CONTROLLED EDI8L24129V tAVAV A tAVEL E# tELEH tAVEH tWLEH tEHAX W# tDVEH D Q HIGH Z tEHDX DATA VALID White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2005 Rev. 5 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PACKAGE DESCRIPTION Package No. 391 119 Lead BGA JEDEC MO-163 0.866 BSC EDI8L24129V PIN 1 INDEX 0.551 BSC 0.060 NOM./0.110 MAX. 0.800 BSC 0.050 TYP 0.300 BSC 0.028 MAX. ORDERING INFORMATION Commercial (0°C to +70°C) Part Number EDI8L24129V10BC EDI8L24129V12BC EDI8L24129V15BC Speed (ns) 10 12 15 Package No. 391 391 391 Industrial (-40°C to +85°C) Part Number EDI8L24129V10BI EDI8L24129V12BI EDI8L24129V15BI Speed (ns) 10 12 15 Package No. 391 391 391 White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2005 Rev. 5 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI8L24129V FIGURE 3 – INTERFACING THE MOTOROLA DSP5630X DSP FAMILY WITH THE EDI8L24129V (128KX24) EDI8L24129V (128K x 24) A16-0 E# Address Bus A23-0 AA0 AA1 AA2 AA3 W# G# DQ0-23 EDI8L24129V (128K x 24) Motorola DSP5630x WR# RD# A16-0 E# W# G# DQ0-23 EDI8L24129V Databus D23-0 (128K x 24) A16-0 E# W# G# DQ0-23 NOTES: 1. In this example three 128K x 24 external memory arrays are shown, one for X data, one for Y data and one for Program. Specific applications may require one, two or all three arrays. 2. Any combination of AA0-AA3 may be used as chip selects. However, each chip select may only be used to select one memory array. FIGURE 4 – INTERFACING THE 21060L OR THE 21062L TO THE EDI8L24129V, 119 BGA (CREATING A 128KX48 MEMORY ARRAY) EDI8L24129V (128K x 24) Address Bus A31-0 A16-0 E# W# G# MSX# DQ16-23 DQ8-15 DQ0-7 Analog ADSP-2106xL WR# RD# A16-0 E# W# G# EDI8L24129V (128K x 24) DQ16-23 DQ8-15 DQ0-7 Databus D47-0 White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2005 Rev. 5 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com