EDI9LC644V

EDI9LC644V 128Kx32 SSRAM/1Mx32 SDRAM EXTERNAL MEMORY SOLUTION FOR TEXAS INSTRUMENTS TMS320C6000 DSP FEATURES DESCRIPTION n Clock speeds: • SSRAM: 200, 166,150, and 133 MHz • SDRAMs: 125 and 100 MHz n n n n n n n DSP Memory Solution • Texas Instruments TMS320C6201 • Texas Instruments TMS320C6701 Packaging: • 153 pin BGA, JEDEC MO-163 3.3V Operating supply voltage Direct control interface to both the SSRAM and SDRAM ports on the “C6x” Common address and databus 65% space savings vs. monolithic solution Reduced system inductance and capacitance The EDI9LC644VxxBC is a 3.3V, 128K x 32 Synchronous Pipeline SRAM and a 1Mx32 Synchronous DRAM array constructed with one 128K x 32 SBSRAM and two 1Mx16 SDRAM die mounted on a multilayer laminate substrate. The device is packaged in a 153 lead, 14mm by 22mm, BGA. The EDI9LC644VxxBC provides a total memory solution for the Texas Instr uments TMS320C6201 and the TMS320C6701 DSPs The Synchronous Pipeline SRAM is available with clock speeds of 200, 166,150, and 133 MHz, allowing the user to develop a fast external memory for the SSRAM interface port . The SDRAM is available in clock speeds of 125 and 100 MHz, allowing the user to develop a fast external memory for the SDRAM interface port . FIG. 1 PIN CONFIGURATION BOTTOM VIEW P IN D ESCRIPTION 7 8 9 2 3 4 5 6 1 A B C D E F G H J K L M N P R T U A0-16 A B C D E F G H J K L M N P R T U Address Bus Data Bus SSRAM Clock SSRAM Address Status Control SSRAM Write Enable SSRAM Output Enable SDRAM Clock SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Write Enable SDRAM Address 10/auto precharge SSRAM Byte Write Enables SDRAM SDQM 0 - 3 Chip Enable SSRAM Device Chip Enable SDRAM Device Power Supply pins, 3.3V Data Bus Power Supply pins, 3.3V (2.5V future) Ground No Connect DQ19 DQ18 VCCQ DQ17 DQ16 VCCQ NC NC A6 NC VCCQ DQ12 DQ13 VCCQ DQ14 DQ15 1 DQ23 DQ22 VCCQ DQ21 DQ20 VCCQ NC NC A7 NC VCCQ DQ11 DQ10 VCCQ DQ9 DQ8 2 VCC VCC VCC VCC VCC VCC NC A8 A9 NC VCC VCC VCC VCC VCC 3 VSS VSS VSS VSS VSS VSS VSS VSS VSS SDCE VSS SDCLK VSS VSS VSS VSS VSS VSS NC VSS VSS VSS NC NC NC NC NC VSS VSS VSS NC NC 6 VCC VCC VCC VCC VCC VCC A2 A1 A0 NC NC VCC VCC VCC VCC VCC VCC 7 DQ24 DQ25 VCCQ DQ26 DQ27 VCCQ A4 A3 A11 A13 A15 VCCQ DQ4 DQ5 VCCQ DQ6 DQ7 8 DQ28 DQ29 VCCQ DQ30 DQ31 VCCQ A5 A10 A12 A14 A16 VCCQ DQ0 DQ1 VCCQ DQ2 DQ3 9 DQ0-31 SSCLK SSADC SSWE SSOE SDCLK SDRAS SDCAS SDWE SDA10 BWE0-3 SSCE SDCE VCC VCCQ VSS NC SDWE SDA10 SDRAS SDCAS VSS NC/A17 NC/A18 NC/A19 BWE2 BWE3 BWE0 BWE1 VSS VSS VSS VSS SSCLK VSS VCC SSADC SSWE SSOE SSCE 4 5 January 2002 Rev. 4 ECO# 14667 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI9LC644V FIG. 2 BLOCK DIAGRAM White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 2 EDI9LC644V OUTPUT FUNCTIONAL DESCRIPTIONS Symbol Type Signal Polarity Function SSCLK SSADS SSOE SSWE SSCE SDCLK SDCE SDRAS SDCAS SDWE Input Input Input Input Input Input Pulse Pulse Pulse Pulse Pulse Pulse Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock. Active Low Active Low When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation to be executed by the SSRAM. SSCE disable or enable SSRAM device operation. Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Active Low Active Low SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3. When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the operation to be executed by the SDRAM. Address bus for SSRAM and SDRAM A0 and A1 are the burst address inputs for the SSRAM During a Bank Active command cycle, A0-9, SDA10 defines the row address (RA0-10) when sampled at the rising clock edge. A0-16, SDA10 Input Level — During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge operation at the end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A11 defines the bank to be precharged (low = bank A, high = bank B). If SDA10 is low, autoprecharge is disabled. During a Precharge command cycle, SDA 10 is used in conjunction with A11 to control which bank(s) to precharge. If SDA10 is high, both bank A and Bank B will be precharged regardless of the state of A11. If SDA10 is low, then A11 is used to define which bank to precharge. DQ0-31 BWE0-3 VCC, VSS VCCQ Input Output Input Supply Supply Level Pulse — Data Input/Output are multiplexed on the same pins. BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE0 is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31. Power and ground for the input buffers and the core logic. Data base power supply pins, 3.3V (2.5V future). 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI9LC644V ABSOLUTE MAXIMUM RATINGS Voltage on Vcc Relative to Vss Vin (DQx) Storage Temperature (BGA) Junction Temperature Short Circuit Output Current -0.5V to +4.6V -0.5V to Vcc +0.5V -55°C to +125°C +175°C 100 mA RECOMMENDED DC OPERATING CONDITIONS (0°C ­ T A ­ 7 0°C; V CC = 3 .3V -5% / +10% Parameter U NLESS O THERWISE N OTED ) Min Max Units Symbol *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Supply Voltage1 Input High Voltage1,2 Input Low Voltage1,2 Input Leakage Current 0 - VIN - V c c Output Leakage (Output Disabled) 0 - VIN - V c c Output High (IOH = -4mA)1 Output Low (IOL = 8mA)1 NOTES: VCC VIH VIL ILI ILO VOH VOL 3.135 2.0 -0.3 -10 -10 2.4 — 3.6 VCC +0.3 0.8 10 10 — 0.4 V V V µA µA V V 1. All voltages referenced to Vss (GND). 2. Overshoot: VIH + 6.0V for t - tKC/2 Underershoot: VIL - 2.0V for t - tKC/2 £ ³ DC ELECTRIC AL CHARACTERISTICS Description Conditions Symbol Frequency Typ Max Units Power Supply Current: Operating (1,2,3) SSRAM Active / DRAM Auto Refresh ICC1 Power Supply Current Operating1,2,3 SSRAM Active / DRAM Idle ICC2 Power Supply Current Operating1,2,3 SDRAM Active / SSRAM Idle SSCE and SDCE VCC -0.2V, All other inputs at VSS +0.2 VIN or VIN VCC -0.2V, Clk frequency = 0 SSCE and SDCE VIH min All other inputs at VIL max VIN or VIN VCC -0.2V, Clk frequency = 0 ICC3 CMOS Standby £ 133MHz 150MHz 166MHz 200MHz 133MHz 150MHz 166MHz 200MHz 83MHz 100MHz 125MHz £ £ £ ISB1 400 450 500 TBD 300 350 400 TBD 220 235 255 20.0 550 580 625 TBD 450 480 525 TBD 240 250 280 40.0 mA mA mA mA ISB2 30.0 55.0 mA ICC5 190 250 mA TTL Standby Auto Refresh NOTES: £ £ 1. ICC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading. 2. “Device idle” means device is deselected (CE VIH) Clock is running at max frequency and Addresses are switching each cycle. 3. Typical values are measured at 3.3V, 25°C. ICC (operating) is specified at specified frequency. ³ BGA C APACITANCE Description Conditions Symbol Typ Max Units Address Input Capacitance 1 Input/Output Capacitance (DQ)1 Control Input Capacitance1 Clock Input Capacitance 1 NOTE: TA = 2 5°C; f = 1MHz TA = 2 5°C; f = 1MHz TA = 2 5°C; f = 1MHz TA = 2 5°C; f = 1MHz CI CO CA C CK 5 8 5 4 8 10 8 6 pF pF pF pF 1. This parameter is sampled. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 4 EDI9LC644V SSRAM AC CHARACTERISTICS (EDI9LC644V) Symbol Parameter 200MHz Min Max 166MHz Min Max 150MHz Min Max 133MHz Min Max Units Clock Cycle Time Clock HIGH Time Clock LOW Time Clock to output valid Clock to output invalid Clock to output on Low-Z Clock to output in High-Z Output Enable to output valid Output Enable to output in Low-Z Output Enable to output in High-Z Address, Control, Data-in Setup Time to Clock Address, Control, Data-in Hold Time to Clock t KHKH tKLKH tKHKL tKHQV tKHQX t KQLZ tKQHZ tOELQV tOELZ t OEHZ tS tH 5 1.6 1.6 2.5 1.5 0 1.5 0 3.0 1.5 0.5 6 2.4 2.4 3.5 1.5 0 1.5 0 3.5 1.5 0.5 7 2.6 2.6 3.8 1.5 0 1.5 0 3.5 1.5 0.5 8 2.8 2.8 4.0 1.5 0 1.5 0 3.8 1.5 0.5 3 2.5 3.5 3.5 3.8 3.8 4.0 4.0 ns ns ns ns ns ns ns ns ns ns ns ns SSRAM OPERATION TRUTH TABLE Operation Address Used SSCE SSADS SSWE SSOE DQ Deselected Cycle, Power Down WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Note: None External External External Current Current Current Current Current Current H L L L X X H H X H L L L L H H H H H H X L H H H H H H L L X X L H L H L H X X High-Z D Q High-Z Q High-Z Q High-Z D D 1. X means “don’t care”, H means logic HIGH. L means logic LOW. 2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK. 3. Suspending burst generates wait cycle 4. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying HIGH though out the input data hold time. 5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. SSRAM PARTIAL TRUTH TABLE Function SSWE BWE0 BWE1 BWE2 BWE3 READ WRITE one Byte (DQ0-7) WRITE all Bytes H L L X L L X H L X H L X H L 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI9LC644V FIG. 3 SSRAM READ TIMING FIG. 4 SSRAM WRITE TIMING White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 6 EDI9LC644V SDRAM AC CHARACTERISTICS Symbol Parameter 125MHz Min Max Min 100MHz Max 83MHz Min Max Units Clock Cycle Time1 CL = 3 CL = 2 Clock to valid Output delay 1,2 Output Data Hold Time2 Clock HIGH Pulse Width 3 Clock LOW Pulse Width 3 Input Setup Time 3 Input Hold Time 3 CLK to Output Low-Z 2 CLK to Output High-Z Row Active to Row Active Delay 4 RAS to CAS Delay 4 Row Precharge Time 4 Row Active Time 4 Row Cycle Time - Operation 4 Row Cycle Time - Auto Refresh 4,8 Last Data in to New Column Address Delay 5 Last Data in to Row Precharge 5 Last Data in to Burst Stop5 Column Address to Column Address Delay 6 Number of Valid Output Data7 NOTES: t CC t CC t SAC tOH tCH t CL tSS t SH t SLZ tSHZ tRRD tRCD t RP t RAS tRC t RFC t CDL t RDL t BDL tCCD 8 10 3 3 3 2 1 2 1000 1000 6 10 12 3 3 3 2 1 2 1000 1000 7 12 15 3 3 3 2 1 2 1000 1000 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK ea 7 20 20 20 50 70 70 1 1 1 1.5 2 1 20 20 20 50 80 80 1 1 1 1.5 2 2 7 24 24 24 60 90 90 1 1 1 1.5 2 1 8 10,000 10,000 10,000 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If tRISE of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter. 4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self-refresh exit. 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI9LC644V CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHZ SDRAM (U NIT = Frequency CAS Latency t N UMBER O F C LOCK ) t RC t RAS RP t RRD t RCD t CCD t CDL t RDL 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 125MHz (8.0ns) 100MHz (10.0ns) 83MHz (12.0ns) 3 3 2 9 7 6 6 5 4 3 2 2 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHZ SDRAM (U NIT = Frequency CAS Latency t N UMBER O F C LOCK ) t RC t RAS RP t RRD t RCD t CCD t CDL t RDL 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100MHz (12.0ns) 83MHz (12.0ns) 3 2 7 6 5 5 2 2 2 2 2 2 1 1 1 1 1 1 REFRESH CYCLE PARAMETERS -10 Parameter Symbol Min Max Min -12 Max Units Refresh Period 1,2 NOTES: tREF — 64 — 64 ms 1. 4096 cycles 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. SDRAM COMMAND TRUTH TABLE Function SDCE SDRAS SDCAS SDWE BWE A 11 SDA10 A 9-0 Notes Mode Register Set Auto Refresh (CBR) Precharge Single Bank Precharge all Banks Bank Activate Write Write with Auto Precharge Read Read with Auto Precharge Burst Termination No Operation Device Deselect Data Write/Output Disable Data Mask/Output Disable L L L L L L L L L L L H X X L L L L L H H H H H H X X X L L H H H L L L L H H X X X L H L L H L L L H L H X X X X X X X X X X X X X X X L H X BA X BA BA BA BA BA X X X X X OP CODE X L H Row Address L H L H X X X X X 4 4 2 2 2 2 2 3 2 NOTES: 1. All of the SDRAM operations are defined by states of SDCE, SDWE, SDRAS, SDCAS, and BWE0-3 at the positive rising edge of the clock. 2. Bank Select (BA), if A11 = 0 then bank A is selected, if BA = 1 then bank B is selected. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 4. The BWE has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. BWE also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 8 EDI9LC644V SDRAM CURRENT STATE TRUTH TABLE Current State SDCE SDRAS SDCAS Command SDWE A 11 (BA) SDA 10-A 0 Description Action Notes L L L L Idle L L L L H L L L L Row Active L L L L H L L L L Read L L L L H L L L L Write L L L L H L L L Read with Auto Precharge L L L L L H L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Set the Mode Register Start Auto No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst 1 1 2 1 1 3 1 4,5 4,5 2 5,6 5,6 2 5,6 5,6 2 2 9 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI9LC644V SDRAM CURRENT STATE TRUTH TABLE (CONT.) Current State SDCE SDRAS SDCAS Command SDWE A 11 (BA) SDA 10-A 0 Description Action Notes L L L Write with Auto Precharge L L L L L H L L L L Precharging L L L L H L L L L Row Activating L L L L H L L L L Write Recovering L L L L H L L L Write Recovering with Auto Precharge L L L L L H L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row active after tRCD No Operation; Row active after tRCD No Operation; Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row active after tDPL No Operation; Row active after tDPL No Operation; Row active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL No Operation; Precharge after tDPL 2 2 2,6 2,6 2 2 6 6 2 2 2 2 2 2 2 2 2 White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 10 EDI9LC644V SDRAM CURRENT STATE TRUTH TABLE (CONT.) Current State SDCE SDRAS SDCAS Command SDWE A 11 (BA) SDA 10-A 0 Description Action Notes L L L L Refreshing L L L L H L L L Mode Register Accessing L L L L L H L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X X X BA BA BA X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles NOTES: 1. Both Banks must be idle otherwise it is an illegal action. 2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 3. The minimum and maximum Active time (tRAS) must be satisfied. 4. The RAS to CAS Delay (tRCD) must occur before the command is given. 5. Address SDA10 is used to determine if the Auto Precharge function is activated. 6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI9LC644V SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @ CAS LATENCY = 3, BURST LENGTH = 1 FIG. 5 White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 12 EDI9LC644V FIG. 6 SDRAM POWER UP SEQUENCE 13 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI9LC644V FIG. 7 SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4 NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2 Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + C AS Latency - 1) + tSAC . 4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst) White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 14 EDI9LC644V FIG. 8 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4 NOTES: 1. To write data before burst read ends. BWE should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written. 3. BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 15 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI9LC644V FIG. 9 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 NOTES: 1. SDCE can be “don’t care” when SDRAS, SDCAS and SDWE are high at the clock going high edge. 2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 16 EDI9LC644V FIG. 10 SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 Notes: 1. To interrupt burst write by Row precharge, BWE should be asserted to mask invalid input data. 2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same. 17 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI9LC644V FIG. 11 SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 NOTES: 1. tCDL should be met to complete write. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 18 EDI9LC644V FIG. 12 SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH =4 NOTES: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length = 1 & 2 and BRSW mode) 19 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI9LC644V SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST LENGTH = FULL PAGE FIG. 13 NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is the same as the case of SDRAS interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on each of them. But at burst write, burst stop and SDRAS interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle”. 3. Burst stop is valid at every burst length. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 20 EDI9LC644V SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP @ BURST LENGTH = FULL PAGE FIG. 14 NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. BWE at write interrupt by precharge command is needed to prevent invalid write. BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. 21 White Electronic Designs Corporation • ( 602) 437-1520 • w ww.whiteedc.com EDI9LC644V FIG. 15 SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2 NOTES: 1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set). At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. White Electronic Designs Corporation • P hoenix AZ • ( 602) 437-1520 22 EDI9LC644V FIG. 16 SDRAM MODE REGISTER SET CYCLE SDRAM AUTO REFRESH CYCLE H IGH *Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle. NOTES: MODE REGISTER SET CYCLE 1. SDCE, SDRAS, SDCAS & SDWE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new SDRAS activation. 7. Please refer to Mode Register Set table. 23 White Electronic Designs Corporation • ( 602) 437-1520 • w ww.whiteedc.com EDI9LC644V PACKAGE DESCRIPTION: 153 LEAD BGA (17 X 9 BALL ARRAY) JEDEC MO-163 ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES Note: Ball attach pad for above BGA is 480 microns, in diameter. Pad is solder mask defined. ORDERING INFORMATION Part Number SSRAM Access SDRAM Access EDI9LC644V2012BC EDI9LC644V2010BC EDI9LC644V1612BC EDI9LC644V1610BC EDI9LC644V1512BC EDI9LC644V1510BC EDI9LC644V1312BC EDI9LC644V1310BC 200MHz 200MHz 166MHz 166MHz 150MHz 150MHz 133MHz 133MHz 125MHz 100MHz 125MHz 100MHz 125MHz 100MHz 125MHz 100MHz White Electronic Designs Corporation • P hoenix AZ • ( 602) 437-1520 24 EDI9LC644V FIG. 17 INTERFACING THE TEXAS INSTRUMENTS TMS320C6 X W ITH THE ED9LC644V (128K X 32 SSRAM/1M X 32 SDRAM) Address Bus EA2-21 Texas Instruments TMS320C6x DSP SSWE\ CE2\ SSOE\ SSADS\ SSCLK BE0\ BE1\ BE2\ BE3\ SDA10 CE0\ SDRAS\ SDCAS\ SDWE\ SDCLK EA2 A0 EA3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 EDI9LC644V 128K x 32 SSRAM 1M x 32 SDRAM DQ0-7 DQ8-15 DQ16-23 DQ24-31 SSWE\ SSCE\ SSOE\ SSADC\ SSCLK BWE0\ BWE1\ BWE2\ BWE3\ SDA10 SDCE\ SDRAS\ SDCAS\ SDWE\ SDCLK SSRAM Control Shared Controls Data Bus ED0-31 SDRAM Control 25 White Electronic Designs Corporation • ( 602) 437-1520 • w ww.whiteedc.com