W3EG7218S265AD4

White Electronic Designs W3EG7218S-AD4 -BD4 PRELIMINARY* 128MB – 16Mx72 DDR SDRAM UNBUFFERED w/PLL FEATURES Double-data-rate architecture DDR200 and DDR266 Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power Supply: 2.5V ± 0.20V JEDEC standard 200 pin SO-DIMM package • Package height options: AD4: 35.5mm (1.38") and BD4: 31.75mm (1.25") * This product is under development, is not qualified or characterized and is subject to change without notice. DESCRIPTION The W3EG7218S is a 16Mx72 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component. The module consists of nine 16Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 200 Pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. OPERATING FREQUENCIES DDR266 @CL=2 Clock Speed CL-tRCD-tRP 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2 November 2004 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PIN CONFIGURATION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VREF VREF VSS VSS DQ0 DQ4 DQ1 DQ5 VCC VCC DQS0 DQM0 DQ2 DQ6 VSS VSS DQ3 DQ7 DQ8 DQ12 VCC VCC DQ9 DQ13 DQS1 DQM1 VSS VSS DQ10 DQ14 DQ11 DQ15 VCC VCC CK0 VCC CK0# VSS VSS VSS DQ16 DQ20 DQ17 DQ21 VCC VCC DQS2 DQM2 DQ18 DQ22 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol VSS VSS DQ19 DQ23 DQ24 DQ28 VCC VCC DQ25 DQ29 DQS3 DQM3 VSS VSS DQ26 DQ30 DQ27 DQ31 VCC VCC CB0 CB4 CB1 CB5 VSS VSS DQS8 DQM8 CB2 CB6 VCC VCC CB3 CB7 NC NC VSS VSS NC VSS NC VCC VCC VCC NC CKE0 NC NC NC A11 Pin 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Symbol A9 AB VSS VSS A7 A6 A5 A4 A3 A2 A1 A0 VCC VCC A10/AP BA1 RA0 RAS# WE# CAS# CS0 NC NC NC VSS VSS DQ32 DQ36 DQ33 DQ37 VCC VCC DQS4 DQM4 DQ34 DQ38 VSS VSS DQ35 DQ39 DQ40 DQ44 VCC VCC DQ41 DQ45 DQS5 DQM5 VSS VSS Pin 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Symbol DQ42 DQ46 DQ43 DQ47 VCC VCC VCC NC VSS NC VSS VSS DQ48 DQ52 DQ49 DQ53 VCC VCC DQS6 DQM6 DQ50 DQ54 VSS VSS DQ51 DQ55 DQ56 DQ60 VCC VCC DQ57 DQ61 DQS7 DQM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VCC VCC SDA SA0 SCL SA1 VCCSPD SA2 VCCID NC A0-A11 BA0-BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 CK0 CK0# CKE0 CS0# RAS# CAS# WE# VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC W3EG7218S-AD4 -BD4 PRELIMINARY PIN NAMES Address input (Multiplexed) Bank Select Address Data Input/Output Check bits Data Strobe Input/Output Clock Input Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Power Supply (2.5V) Power Supply for DQS (2.5V) Ground Power Supply for Reference Serial EEPROM Power Supply (2.3V to 3.6V) Serial Data I/O Serial Clock Address in EEPROM VCC Identification Flag No Connect DQM0-DQM8 Data-In Mask November 2004 Rev. 1 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FUNCTIONAL BLOCK DIAGRAM CS0# DQS0 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ CK0 CK0# 120 PLL DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQS7 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQS6 DQM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQS5 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQS4 DQM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ W3EG7218S-AD4 -BD4 PRELIMINARY DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 1 SERIAL PD SCL WP SDA A0 A1 A2 SA0 SA1 SA2 VDDSPD VDD VREF VSS SPD/EEPROM DDR SDRAMS DDR SDRAMS DDR SDRAMS BA0, BA1 A0-A11 RAS# CAS# CKE0 WE# BA0, BA1 A0-A11 RAS# CAS# CKE0 WE# Note: All resistor values are 22Ω unless otherwise indicated November 2004 Rev. 1 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. W3EG7218S-AD4 -BD4 PRELIMINARY Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value – 0.5 ~ 3.6 –1.0 ~ 3.6 – 55 ~ +150 9 50 Units V V °C W mA 0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V Parameter Supply Voltage Supply Voltage Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Symbol VCC VCCQ VREF VTT VIH VIL VOH VOL Min 2.3 2.3 1.15 1.15 VREF + 0.15 – 0.3 VTT+ 0.76 — Max 2.7 2.7 1.35 1.35 VCCQ + 0.3 VREF – 0.15 — VTT – 0.76 Unit V V V V V V V V DC CHARACTERISTICS CAPACITANCE TA = 25°C, f = 1MHz, VCC = 2.5V Parameter Input Capacitance (A0-A11) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0,CKE1) Input Capacitance (CK0,CK0#) Input Capacitance (CS0#,CS1#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output Capacitance (DQ0-DQ63)(DQS) Data input/output Capacitance (CB0-CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT Max 29 29 29 5.5 29 8 29 8 8 Unit pF pF pF pF pF pF pF pF pF November 2004 Rev. 1 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs IDD SPECIFICATIONS AND TEST CONDITIONS DDR266 @CL=2 Parameter Operating Current Symbol Conditions IDD0 One device bank; Active - Precharge; (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. tRC=tRC(MIN); tCK=tCK One device bank; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN);tCK=tCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power-down mode; tCK=tCK(MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-down mode; tCK(MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continous burst; One device bank active;Address andcontrol inputs changing once per clock cycle; tCK=tCK(MIN); IOUT = 0mA. Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. tRC=tRC(MIN) CKE ≤ 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands Max 1125 W3EG7218S-AD4 -BD4 PRELIMINARY (Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V) DDR266 @CL=2.5 Max 990 DDR200 @CL=2 Max 990 Units mA Operating Current IDD1 1215 1080 1080 mA Precharge PowerDown Standby Current Idle Standby Current IDD2P IDD2F 27 405 27 405 27 405 mA mA Active Power-Down Standby Current Active Standby Current IDD3P IDD3N 225 450 225 450 225 450 mA mA Operating Current IDD4R 1260 1170 1170 mA Operating Current IDD4W 1260 1125 1125 mA Auto Refresh Current Self Refresh Current Operating Current IDD5 IDD6 IDD7A 2385 27 3195 1980 27 2970 1980 27 2970 mA mA mA November 2004 Rev. 1 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT : ONE BANK 1. 2. 3. Typical Case : VCC=2.5V, T=25°C Worst Case : VCC=2.7V, T=10°C Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA Timing Patterns : • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst W3EG7218S-AD4 -BD4 PRELIMINARY IDD7A : OPERATING CURRENT : FOUR BANKS 1. 2. 3. Typical Case : VCC=2.5V, T=25°C Worst Case : VCC=2.7V, T=10°C Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA Timing Patterns : • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst 4. 4. • • • • Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 November 2004 Rev. 1 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7218S-AD4 -BD4 PRELIMINARY ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time CL = 2.5 CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time SYMBOL tAC tCH tCL tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHS tISS tIPW tMRD -0.75 0.90 0.90 2.2 15 0.75 0.2 0.2 tCH, tCL +0.75 -0.75 1.1 1.1 2.2 15 MIN -0.75 0.45 0.45 7.5 7.5 0.5 0.5 1.75 -0.60 0.35 0.35 0.5 1.25 0.75 0.2 0.2 tCH, tCL +0.75 +0.75 262 MAX +0.75 0.55 0.55 13 13 MIN -0.75 0.45 0.45 7.5 10 0.5 0.5 1.75 -0.75 0.35 0.35 0.6 1.25 +0.75 265/202 MAX +0.75 0.55 0.55 13 13 UNITS ns tCK tCK ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns 30 16, 37 16, 37 12 12 22, 23 26 26 40, 45 40, 45 23, 27 23, 27 27 NOTES November 2004 Rev. 1 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7218S-AD4 -BD4 PRELIMINARY ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) AC CHARACTERISTICS PARAMETER DQ-DQS hold, DQS to first DQ to go non-valid, per access Data Hold Skew Factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window (DVW) REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command SYMBOL tQH tQHS tRAS tRAP tRC tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR na 262 MIN tHP - tQHS 0.75 40 15 60 75 15 15 0.9 0.4 15 0.25 0 0.4 15 1 tQH - tDQSQ 140.6 15.6 0 75 200 0 75 200 0.6 1.1 0.6 120,000 40 20 65 75 20 20 0.9 0.4 15 MAX MIN 265/202 MAX UNITS NOTES tHP - tQHS 0.75 120,000 ns ns ns ns ns ns ns ns 1.1 0.6 tCK tCK ns tCK ns 0.6 tCK ns tCK 22, 23 31, 48 43 38 38 0.25 0 0.4 15 1 tQH - tDQSQ 140.6 15.6 18, 19 17 ns µs µs ns ns tCK 22 21 21 tREFC tREFI tVTD tXSNR tXSRD November 2004 Rev. 1 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: W3EG7218S-AD4 -BD4 PRELIMINARY VTT Output (VOUT) 50Ω Reference Reference Point Point 30pF 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The mini-mum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on Vref may not exceed ±2 percent of the DC value. Thus, from VCCQ/2, Vref is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. IDD is dependent on output loading and cycle rates. Specified values are obtained with mini-mum cycle time at CL = 2 for -26A and -202, CL = 2.5 for -335 and -265 with the outputs open. Enables on-chip refresh and address counters. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. This parameter is sampled. VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA = 25°C, VOUT(DC) = VCCQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500 mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -335, slew rates must be 0.5 V/ns. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. tHZ and tLZ transitions occur in the same access time windows as data valid transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. The intent of the Don’t Care state after completion of the postamble is the DQSdriven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high [above VIHDC (MIN)] then it must not transition low (below VIHDC) prior to tDQSH (MIN). 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 21. The refresh period 64ms. This equates to an average refresh rate of 15.625µs 128MB. However, an AUTO REFRESH command must be asserted at least once every 140.6µs 128MB; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct porportion with the clock duty cycle and a practical data valid window can be derived, as shown in Figure 7, Derating Data Valid Window. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 23. Each byte lane has a corresponding DQS. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 26. JEDEC specifies CK and CK# input slew rate must be ≤ 1V/ns (2V/ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100 mv/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. For -335, slew rates must be ≥ 0.5 V/ns. 28. VCC must not vary more than 4 percent if CKE is not active while any bank is active. 29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(min) can be satisfied prior to the internal precharge command being issued. 32. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9V, which ever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either - 300mV or 2.2V, whichever is more positive. November 2004 Rev. 1 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs 33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V. 34. The voltage levels used are derived from a mini-mum VCC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 35. VIH overshoot: VIH(MAX) = VCCQ + 1.5V for a pulse width !5 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width !5 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 36. VCC and VCCQ must track each other. 37. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. W3EG7218S-AD4 -BD4 PRELIMINARY 38. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 39. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0Vs, provided a minimum of 42 0 of series resistance is used between the VTT supply and the input pin. 40. The part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 41. Random addressing changing and 50 percent of data changing at every transfer. 42. Random addressing changing and 100 percent of data changing at every transfer. 43. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 44. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.” 45. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. 46. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 47. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. 48. The -335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency. November 2004 Rev. 1 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ORDERING INFORMATION FOR AD4 Part Number W3EG7218S262AD4 W3EG7218S265AD4 W3EG7218S202AD4 Speed 133MHz/266Mbps, CL=2 133MHz/266Mbps, CL=2.5 100MHz/200Mbps, CL=2 Height* 35.05 (1.38") 35.05 (1.38") 35.05 (1.38") W3EG7218S-AD4 -BD4 PRELIMINARY PACKAGE DIMENSIONS FOR AD4 2.0 (0.079) 67.56 (2.66) MAX. 3.81 (0 .150) MAX. 3.98 ± 0.1 (0.157 ± 0.004) 20 (0.787) 35.05 (1.38) MAX. P1 2.31 (0.091) REF. 4.19 (0.165) 1.80 (0.071) 11.40 (0.449) 47.40 (1.866) 3.98 (0.157) MIN. 1.0 ± 0.1 (0.039 ± 0.004) * All dimensions are in MILLIMETERS AND (INCHES) November 2004 Rev. 1 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ORDERING INFORMATION FOR BD4 Part Number W3EG7218S262BD4 W3EG7218S265BD4 W3EG7218S202BD4 Speed 133MHz/266Mbps, CL=2 133MHz/266Mbps, CL=2.5 100MHz/200Mbps, CL=2 Height* 31.75 (1.25") 31.75 (1.25") 31.75 (1.25") W3EG7218S-AD4 -BD4 PRELIMINARY PACKAGE DIMENSIONS FOR BD4 67.56 (2.666) MAX 3.81 (0.150) MAX. 3.98 ± 0.1 (0.157 ± 0.004) 20 (0.787) 31.75 (1.25) 2.31 (0.091) REF. 4.19 (0.165) 1.80 (0.071) 11.40 (0.449) 47.40 (1.866) 3.98 (0.157) MIN. 1.0 ± 0.1 (0.039 ± 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) November 2004 Rev. 1 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs Document Title 128MB – 16Mx72 DDR SDRAM UNBUFFERED w/PLL W3EG7218S-AD4 -BD4 PRELIMINARY Revision History Rev # Rev A Rev 0 History Created 0.1 Data sheet spec updates 0.2 Changed datasheet from Advanced to Preliminary 0.3 Added “BD4” package optionr Release Date 7-23-03 9-04 Status Advanced Preliminary Rev 1 1.1 Updated new IDD and CAP specs 11-04 Preliminary November 2004 Rev. 1 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com