WC32P040-XP4M

White Electronic Designs 68040 FEATURES Selection of Processor Speeds: 25, 33MHz Military Temperature Range: -55°C to +125°C Packaging • 179 pin Ceramic PGA (P4) • 184 lead Ceramic Quad Flatpack, CQFP (Q4) 6-Stage Pipeline, 68030-Compatible IU 68881/68882-Compatible FPU Independent Instruction and Data MMUs Simultaneously Accessible, 4-Kbyte Physical Instruction Cache and 4-Kbyte Physical Data Cache Low-Latency Bus Acceses for Reduced Cache Miss Penalty Multimaster/Multiprocessor Support via Bus Snooping Concurrent IU, FPU, MMU, and Bus Controller Operation Maximizes Throughput WC32P040-XXM 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface User Object-Code Compatible with all Earlier 68000 Microprocessors 4-GigaByte Direct Addressing Range DESCRIPTION The WC32P040 is a 68000-compatible, high-performance, 32-bit microprocessor. The WC32P040 is a virtual memory microprocessor employing multiple concurrent execution units and a highly intergrated architecture that provides very high performance in a monolithic HCMOS device. It has a 68030-compatible integer unit (IU) and two independent caches. The WC32P040 contains dual, independent, demand-paged memory management units (MMUs) for instruction and data stream accesses and independent, 4-Kbyte instruction and data caches. The WC32P040 has a 68881/68882-compatible floating-point unit (FPU). FIGURE 1 – BLOCK DIAGRAM INSTRUCTION DATA BUS INSTRUCTION ATC INSTRUCTION CACHE INSTRUCTION ADDRESS B U S C O N T R O L L E R INSTRUCTION FETCH CONVERT DECODE EA CALCULATE EXECUTE EA FETCH EXECUTE WRITEBACK FLOATINGPOINT UNIT WRITEBACK INTEGER UNIT INSTRUCTION MMU/CACHE/SNOOP CONTROLLER INSTRUCTION MEMORY UNIT ADDRESS BUS DATA BUS DATA MEMORY UNIT DATA MMU/CACHE/SNOOP CONTROLLER DATA ADDRESS BUS CONTROL SIGNALS DATA ATC DATA CACHE OPERAND DATA BUS July 1998 July 1998 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WC32P040-XXM FIGURE 2 – PIN CONFIGURATION FOR WC32P040-XXM, CQFP (Q4) GND GND A31 A30 VCC A29 A28 GND A27 A26 VCC A25 A24 GND A23 A22 VCC A21 A20 GND A19 A18 VCC GND A17 A16 GND A15 A14 VCC A13 A12 GND A11 A10 GND VCC TT1 TT0 GND UPA1 UPA0 VCC CIOUT# IPEND# GND 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 D0 D1 VCC GND D2 D3 GND D4 GND D5 VCC D6 D7 GND D8 D9 VCC GND D10 D11 GND D12 D13 VCC D14 D15 GND D16 D17 VCC GND D18 D19 GND D20 D21 VCC D22 VCC D23 GND D24 D25 GND VCC D26 TOP VIEW 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 D27 GND D28 D29 VCC D30 D31 GND GND A9 A8 VCC A7 A6 GND A5 A4 VCC A3 A2 GND A1 A0 VCC GND TM2 TM1 GND TM0 TLN1 VCC TLN0 SIZ0 GND R/W# LOCKE# VCC GND SIZ1 LOCK# GND MI# BR# VCC TS# BB# Pin Group PLL Internal Logic Output Drivers 17, 22, 24 July 1998 RSTO# TD0 TD1 TCK GND TRST# TMS GND VCC MDIS# CDIS# RSTI# IPL2# IPL1# IPL0# GND GND BCLK VCC GND VCC GND PCLK GND GND DLE GND GND TCI# AVEC# TBI# VCC GND SC0 SC1 BG# TEA# TA# PST0 GND PST1 PST2 VCC PST3 TIP GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 GND 19, 21 Vcc 5, 8, 10, 27, 28, 33, 55, 68, 95, 108, 121, 130, 135, 162, 174 16, 20, 25, 40, 46, 52, 59, 65, 72, 78, 84, 85, 91, 98, 105, 112, 118, 125, 132, 139, 140, 146, 152, 158, 165, 171, 178, 184 9, 32, 56, 69, 81, 94, 100, 109, 122, 136, 149, 161, 175 43, 49, 62, 75, 88, 102, 115, 128, 143, 155, 168, 181 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WC32P040-XXM FIGURE 3 – PIN CONFIGURATION FOR WC32P040-XXM, PGA (P4) T TDO TRST# GND CDIS# IPL2# IPL1# IPL0# S IPEND# GND R CIOUT# VCC RTSO# GND Q UPA1 P A10 N A12 M A13 L A14 K A15 J A17 H A18 G A20 F A21 E A22 D A24 C A27 B A29 A A31 1 D3 2 D4 3 D5 4 D6 5 D7 6 D9 7 D10 8 D11 9 D12 10 D13 11 D14 12 D15 13 D17 14 D19 15 D20 16 D21 17 D24 18 GND D1 GND VCC GND D8 GND VCC GND D16 D18 GND VCC GND D22 GND D26 VCC D0 D2 VCC GND GND VCC GND VCC GND VCC GND VCC D23 D25 VCC D28 GND A30 D27 GND D31 A26 A28 D29 D30 A8 GND A25 A9 GND A7 VCC A23 A6 VCC A5 GND VCC VCC GND A4 A19 VCC A16 GND GND TM2 A2 A1 A3 GND GND VCC GND A0 VCC VCC GND VCC TM1 GND A11 R/W# GND TM0 TT1 TT0 SIZ1 SIZ0 TLN1 GND UPA0 MI# GND TLN0 VCC GND BCLK VCC PCLK GND GND VCC GND PST2 TIP# TS# VCC LOCKE# TDI TCK TMS MDIS# RSTI# VCC GND GND TBI# SC1 TEA# PST1 GND VCC GND LOCK# DLE TCI# AVEC# SC0 BG# TA# PST0 PST3 BB# BR# BOTTOM VIEW VCC Pin Group PLL Internal Logic Output Drivers S9, R6, R10 GND R8, S8 Vcc C6, C7, C9, C11, C13, K3, L3, M16, R4, R11, R13, S6, S10, T4 B2, B4, B6, B8, B10, B13, B15, B17, D2, D17, F2, F17, H2, H17, L2, L17, N2, N17, Q2, Q17, S2, S15, S17 C5, C8, C10, C12, C14, H3, H16, J3, J16, L16, M3, R5, R12 B5, B9, B14, C2, C17, G2, G17, M2, M17, R2, R17, S16 July 1998 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DATA FORMATS The WC32P040 supports the basic data formats of the 68000 family. Some data formats apply only to the IU, some only to the FPU, and some to both. In addition, the instruction set supports operations on other data formats such as memory addresses. WC32P040-XXM ADDRESSSING The WC32P040 supports the basic addressing modes of the 68000 family. The register indirect addressing modes support postincrement, predecrement, offset, and indexing. The program counter indirect mode also has indexing and offset capabilities. DATA FORMATS Operand Data Format Bit Bit Field Binary-Coded Decimal (BCD) Byte Integer Word Integer Long-Word Integer Quad-Word Integer 16-Byte Single-Precision Real Double-Precision Real Extended-Precision Real Size 1 Bit 1-32 Bits 8 Bits 8 Bits 16 Bits 32 Bits 64 Bits 128 Bits 32 Bits 64 Bits 80 Bits Supported In IU IU IU IU, FPU IU, FPU IU, FPU IU IU FPU FPU FPU Notes — Field of Consecutive Bits Packed: 2 Digits/Byte; Unpacked: 1 Digit/Byte — — — Any Two Data Registers Memory Only, Aligned to 16-Byte Boundary 1-Bit Sign, 8-Bit Exponent, 23-Bit Fraction 1-Bit Sign,11-Bit Exponent, 52-Bit Fraction 1-Bit Sign,15-Bit Exponent, 64-Bit Mantissa ADDRESSING MODES Addressing Register Direct Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Register Indirect with Index Address Register Indirect with Index (8-Bit Displacement) Address Register Indirect with Index (Base Displacement) Memory Indirect Memory Indirect Postindexed Memory Indirect Preindexed Program Counter Indirect with Displacement Program Counter Indirect with Index PC Indirect with Index (8-Bit Displacement) PC Indirect with Index (Base Displacement) Program Counter Memory Indirect PC Memory Indirect Postindexed PC Memory Indirect Preindexed Absolute Absolute Short Absolute Long Immediate Syntax Dn An (An) (An) + - (An) (d16,An) (d8,An,Xn) (bd,An,Xn) ([bd,An],Xn,od) ([bd,An,Xn],od) (d16,PC) (d8,PC,Xn) (bd,PC,Xn) ([bd,PC],Xn,od) ([bd,PC,Xn],od) (xxx).W (xxx).L # INSTRUCTION SET SUMMARY Opcode ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ANDI to CCR ANDI to SR Operation BCD Source + BCD Destination + X Source + Destination Source + Destination Destination Destination Destination Destination Destination Syntax ABCD Dy,Dx ABCD -(Ay),-(Ax) ADD ,Dn ADD Dn, ADDA ,An ADDI #, ADDQ #, ADDX Dy,Dx ADDX -(Ay),-(Ax) AND ,Dn AND Dn, ANDI #, ANDI #,CCR ANDI #,SR SR Immediate Data + Destination Immediate Data + Destination Source + Destination + X Source Λ Destination Destination Destination Destination Immediate Data Λ Destination Source Λ CCR CCR If supervisor state then Source Λ SR else TRAP July 1998 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs INSTRUCTION SET SUMMARY (contd) Opcode ASL,ASR Operation Destination Shifted by count Destination Syntax ASd Dx,Dy(1) ASd #,Dy(1) ASd (1) Bcc PC Z; (bit number) of Destination BCHG Dn, BCHG #, BCLR Dn, BCLR #, BFCHG {offset:width} BFCLR {offset:width} BFEXTS {offset:width}, Dn BFEXTU {offset:width}, Dn Dn BFFFO {offset:width}, Dn BFINS Dn, {offset:width} BFSET {offset:width} BFTST {offset:width} BKPT # BRA BSET Dn, BSET #, PC BSR BTST Dn, BTST #, cc; CAS Dc,Du, WC32P040-XXM Bcc BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST BKPT BRA BSET BSR BTST CAS It condition true then PC + dn ~(bit number of Destination) ~(bit number ot Destination) ~(bit number ot Destination) Z; 0 bit number ot Destination ~(bit field ot Destination) 0 bit field of Destination Dn Dn bit field of Destination bit field of Source bit offset of Source bit offset of Source Bit Scan Dn 1s bit field of Destination bit field of Destination bit field of Destination Run breakpoint acknowledge cycle; TRAP as illegal instruction PC+dn PC ~(bit number ot Destination) Z; 1 bit number of Destination SP - 4 SP; PC (SP); PC + dn Z –(bit number of Destination) CAS Destination – Compare Operand if Z, Update Operand Destination else Destination Compare Operand CAS2 Destination 1 – Compare 1 cc; if Z, Destination 2 – Compare cc; if Z, Update 1 Destination 1; Update 2 Destination 2 else Destination 1 Compare 1; Destination 2 Compare 2 If Dn < 0 or Dn > Source then TRAP If Rn < LB or If Rn > UB then TRAP If supervisor state then invalidate selected cache lines else TRAP 0 Destination cc CAS2 CAS2 Dc1-Dc2,Du1-Du2,(Rn1)-(Rn2) CHK CHK2 CINV CHK ,Dn CHK2 ,Rn CINVL , (An) CINVP , (An) CINVA CLR CMP ,Dn CMPA ,An CMPI #, CMPM (Ay)+,(Ax)+ CMP2 ,Rn CPUSHL , (An) CPUSHP , (An) CPUSHA CLR CMP CMPA CMPI CMPM CMP2 CPUSH Destination – Source Destination – Source Destination – Immediate Data Destination – Source cc Compare Rn < LB or Rn > UB and Set Condition Codes If supervisor state then it data cache push selected dirty data cache lines; invalidate selected cache lines else TRAP 5 July 1998 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs INSTRUCTION SET SUMMARY (contd) Opcode DBcc Operation If condition false then (Dn-1 Dn; if (Dn ≠ -1 then PC + dn PC) Destination + Source Destination Syntax DBcc Dn, WC32P040-XXM DIVS, DIVSL DIVS.W ,Dn DIVS.L ,Dq DIVS.L ,Dr:Dq DIVSL.L ,Dr:Dq DIVU.W ,Dn DIVU.L ,Dq DIVU.L ,Dr:Dq DIVUL.L ,Dr:Dq EOR Dn, EORI #, EORI #,CCR 32 + 16 32 + 32 64 + 32 32 + 32 32 + 16 32 + 32 64 + 32 32 + 32 16r:16q 32q 32r:32q 32r:32q 16r:16q 32q 32r:32q 32r:32q DIVU, DIVUL Destination + Source Destination EOR EORI EORI to CCR Source ⊕ Destination Source ⊕ CCR Destination Destination Immediate Data ⊕ Destination CCR EORI to SR If supervisor state EORI #,SR then Source SR SR else TRAP EXG Dx,Dy EXG Ax,Ay EXG Dx,Ay EXG Ay,Dx Destination EXT.W Dn EXT.L L Dn EXTB.L Dn extend byte to word extend word to long word extend byte to long word EXG Rx Ry EXT,EXTB Destination Sign – Extended FABS Absolute Value of Source FPn FABS. ,FPn FABS.X FPm,FPn FABS.X FPn FrABS. ,FPn(2) FrABS.X FPm,FPn(2) FrABS.X FPn(3) FADD.