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WD512K32NV-17H1CA

WD512K32NV-17H1CA

  • 厂商:

    WEDC

  • 封装:

  • 描述:

    WD512K32NV-17H1CA - 512Kx32 SRAM 3.3V MULTICHIP PACKAGE - White Electronic Designs Corporation

  • 详情介绍
  • 数据手册
  • 价格&库存
WD512K32NV-17H1CA 数据手册
White Electronic Designs 512Kx32 SRAM 3.3V MULTICHIP PACKAGE FEATURES Access Times of 15, 17, 20ns Low Voltage Operation Packaging • 66-pin, PGA Type, 1.075 inch square, Hermetic Ceramic HIP (Package 400) • 68 lead, 22.4mm (0.880 inch) CQFP, (G2U), 3.56mm (0.140"), (Package 510) Organized as 512Kx32; User Configurable as 2x512Kx16 or 4x512Kx8 Commercial, Industrial and Military Temperature Ranges Low Voltage Operation: • 3.3V ± 10% Power Supply Low Power CMOS WS512K32V-XXX TTL Compatible Inputs and Outputs Fully Static Operation: • No clock or refresh required. Three State Output. Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight WS512K32V-XG2UX - 8 grams typical WS512K32NV-XH1X - 13 grams typical * This product is subject to change without notice. PIN CONFIGURATION FOR WS512K32NV-XH1X Top View 1 I/O8 I/O9 I/O10 A13 A14 A15 A16 A17 I/O0 I/O1 I/O2 11 22 12 WE2# CS2# GND I/O11 A10 A11 A12 VCC CS1# NC I/O3 33 23 I/O15 I/O14 I/O13 I/O12 OE# A18 WE1# I/O7 I/O6 I/O5 I/O4 I/O24 I/O25 I/O26 A6 A7 NC A8 A9 I/O16 I/O17 I/O18 44 34 VCC CS4# WE4# I/O27 A3 A4 A5 WE3# CS3# GND I/O19 55 45 I/O31 I/O30 I/O29 I/O28 A0 A1 A2 I/O23 I/O22 I/O21 8 8 8 8 OE# A0-18 WE1# CS1# Pin Description 56 I/O0-31 A0-18 WE1-4# CS1-4# OE# VCC GND NC Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected Block Diagram WE2# CS2# WE3# CS3# WE4# CS4# 512K x 8 512K x 8 512K x 8 512K x 8 I/O20 66 I/O0-7 I/O8-15 I/O16-23 I/O24-31 March 2006 Rev. 12 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PIN CONFIGURATION FOR WS512K32V-XG2UX Top View NC A0 A1 A2 A3 A4 A5 CS3# GND CS4# WE1# A6 A7 A8 A9 A10 VCC WS512K32V-XXX Pin Description I/O0-31 A0-18 WE1-4# CS1-4# OE# VCC GND NC Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VCC A11 A12 A13 A14 A15 A16 CS1# OE# CS2# A17 WE2# WE3# WE4# A18 NC NC I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 Block Diagram WE1# CS1# WE2# CS2# WE3# CS3# WE4# CS4# OE# A0-18 512K x 8 512K x 8 512K x 8 512K x 8 8 8 8 8 I/O0-7 I/O8-15 I/O16-23 I/O24-31 March 2006 Rev. 12 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage Symbol TA TSTG VG TJ VCC Min -55 -65 -0.5 -0.5 Max +125 +150 4.6 150 4.6 Unit °C °C V °C V CS H L L L OE X L X H WE X H L H WS512K32V-XXX TRUTH TABLE Mode Standby Read Write Out Disable Data I/O High Z Data Out Data In High Z Power Standby Active Active Active RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 3.0 2.2 -0.3 Max 3.6 VCC + 0.3 +0.8 Unit V V V CAPACITANCE TA = +25°C Parameter OE# capacitance WE1-4# capacitance HIP (PGA) CQFP G2U CS1-4# capacitance Data# I/O capacitance Address input capacitance Symbol Conditions COE VIN = 0V, f = 1.0 MHz CWE VIN = 0V, f = 1.0 MHz Max Unit 50 pF pF 20 20 VIN = 0V, f = 1.0 MHz 20 pF VI/O = 0V, f = 1.0 MHz 20 pF VIN = 0V, f = 1.0 MHz 50 pF CCS CI/O CAD This parameter is guaranteed by design but not tested. DC CHARACTERISTICS VCC = 3.3V ± 0.3V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Input Leakage Current Output Leakage Current Operating Supply Current Standby Current Output Low Voltage Output High Voltage Sym ILI ILO ICC x 32 ISB VOL VOH Conditions Min VIN = GND to VCC CS# = VIH, OE# = VIH, VOUT = GND to VCC CS# = VIL, OE# = VIH, f = 5MHz, VCC = 3.6 CS# = VIH, OE# = VIH, f = 5MHz, VCC = 3.6 IOL = 4.0mA IOH = -4.0mA Units Max 10 10 400 200 0.4 2.4 µA µA mA mA V V NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V. Contact factory for low power option. March 2006 Rev. 12 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC CHARACTERISTICS VCC = 3.3V, GND = 0V, -55°C ≤ TA ≤ +125°C Parameter Read Cycle Read Cycle Time Address Access Time Output Hold from Address Change Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Symbol tRC tAA tOH tACS tOE tCLZ1 tOLZ1 tCHZ1 tOHZ1 Min 15 0 15 8 1 0 8 8 1 0 8 8 -15 Max 15 0 17 8 Min 17 -17 Max 17 WS512K32V-XXX -20 Min 20 0 20 10 1 0 10 10 Max 20 Units ns ns ns ns ns ns ns ns ns 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS VCC = 3.3V, GND = 0V, -55°C ≤ TA ≤ +125°C Parameter Write Cycle Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Address Hold Time Output Active from End of Write Write Enable to Output in High Z Data Hold Time Symbol tWC tCW tAW tDW tWP tAS tAH tOW1 tWHZ1 tDH Min 15 12 12 9 12 0 0 2 0 -15 Max Min 17 12 12 9 14 0 0 3 0 -17 Max Min 20 14 14 10 14 0 0 3 0 -20 Max ns ns ns ns ns ns ns ns ns ns Units 8 8 9 1. This parameter is guaranteed by design but not tested. AC TEST CIRCUIT AC Test Conditions IOL Current Source D.U.T. Ceff = 50 pf VZ ≈ 1.5V (Bipolar Supply) Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level Typ VIL = 0, VIH = 2.5 5 1.5 1.5 Unit V ns V V IOH Current Source Notes: V Z is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. V Z is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. March 2006 Rev. 12 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs TIMING WAVEFORM - READ CYCLE WS512K32V-XXX tRC ADDRESS tAA tRC ADDRESS CS# tAA tOH DATA I/O PREVIOUS DATA VALID DATA VALID tACS tCLZ OE# tCHZ READ CYCLE 1 (CS# = OE# = VIL, WE# = VIH) tOE tOLZ DATA I/O HIGH IMPEDANCE tOHZ DATA VALID READ CYCLE 2 (WE# = VIH) WRITE CYCLE - WE# CONTROLLED tWC ADDRESS tAW tCW CS# tAH tAS WE# tWP tOW tWHZ tDW DATA VALID tDH DATA I/O WRITE CYCLE 1, WE# CONTROLLED WRITE CYCLE - CS# CONTROLLED tWC ADDRESS WS32K32-XHX tCW tAH tAS CS# tAW tWP WE# tDW DATA I/O DATA VALID tDH WRITE CYCLE 2, CS# CONTROLLED March 2006 Rev. 12 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WS512K32V-XXX PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1) 27.3 (1.075) ± 0.25 (0.010) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 4.60 (0.181) MAX 3.81 (0.150) ± 0.13 (0.005) 2.54 (0.100) TYP 1.42 (0.056) ± 0.13 (0.005) 0.76 (0.030) ± 0.13 (0.005) 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) ± 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 510: 68 LEAD, LOW PROFILE CERAMIC QUAD FLAT PACK, CQFP (G2U) 25.15 (0.990) ± 0.25 (0.010) SQ 22.36 (0.880) ± 0.25 (0.010) SQ 3.51 (0.140) MAX 0.25 (0.010) ± 0.10 (0.002) Pin 1 0.25 (0.010) REF 24.0 (0.946) ± 0.25 (0.010) 1° / 7° 1.01 (0.040) ± 0.13 (0.005) R 0.25 (0.010) 0.53 (0.021) ± 0.18 (0.007) 23.87 (0.940) REF DETAIL A 1.27 (0.050) TYP 0.38 (0.015) ± 0.05 (0.002) 20.3 (0.800) REF SEE DETAIL "A" ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES March 2006 Rev. 12 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ORDERING INFORMATION WS512K32V-XXX W S 512K 32 X V - XXX X X X WHITE ELECTRONIC DESIGNS CORP. SRAM ORGANIZATION, 512Kx32 User configurable as 2x512Kx16 or 4x512Kx8 IMPROVEMENT MARK: N = No Connect at pin 21 and 39 in HIP for Upgrades (H1 only) Low Voltage Supply 3.3V ± 10% ACCESS TIME (ns) PACKAGE TYPE: H1 = 1.075" sq. Ceramic Hex In Line Package, HIP (Package 400) G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510) DEVICE GRADE: M = Military I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C LEAD FINISH: Blank = Gold plated leads A = Solder dip leads March 2006 Rev. 12 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WD512K32NV-17H1CA
物料型号: - 型号为WS512K32V-XXX,具体型号有WS512K32V-XG2UX和WS512K32NV-XH1X。

器件简介: - 512Kx32位SRAM存储器,工作电压为3.3V,提供快速访问时间(15ns、17ns、20ns)。 - 采用低功耗CMOS技术,兼容TTL的输入输出。 - 支持全静态操作,无需时钟或刷新。 - 具备三态输出功能。

引脚分配: - WS512K32NV-XH1X型号为66引脚PGA封装,WS512K32V-XG2UX型号为68引脚CQFP封装。 - 引脚包括数据输入/输出(1/O0-31)、地址输入(A0-18)、写使能(WE1-4#)、芯片选择(CS1-#)、输出使能(OE#)、电源(Vcc)和地(GND)。

参数特性: - 工作温度范围从商用、工业用到军用。 - 供电电压为3.3V±10%。 - 支持512Kx32、512Kx16或512Kx8的配置。

功能详解: - 该SRAM支持全静态操作,无需刷新,低功耗。 - 内置去耦电容和多个地线引脚,有助于降低噪声。 - 提供三种访问时间选项,适用于不同速度要求的应用。

应用信息: - 适用于需要高速、低功耗SRAM的场合,如缓存存储、高速数据处理等。

封装信息: - 提供66引脚PGA封装(Package 400)和68引脚CQFP封装(Package 510)。 - PGA封装尺寸为1.075英寸平方,CQFP封装尺寸为22.4mm(0.880英寸)。
WD512K32NV-17H1CA 价格&库存

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