WE32K32N-150G2UMA

White Electronic Designs 32Kx32 EEPROM MODULE, SMD 5962-94614 FEATURES Access Times of 80**, 90, 120, 150ns MIL-STD-883 Compliant Devices Available Packaging: • 68 lead, Hermetic CQFP (G2U), 122.4mm (0.880") square, 3.56mm (0.140") height (Package 510). • 66-pin, PGA Type, 1.075" square, Hermetic Ceramic HIP (Package 400) * This product is subject to change without notice. ** 80ns speed is not fully characterized and is subject to change or cancellation without notice. WE32K32-XXX Data Retention at 25°C, 10 Years Write Endurance, 10,000 Cycles Organized as 32Kx32; User Configurable 64Kx16 or 128Kx8 Commercial, Industrial and Military Temperature Ranges Automatic Page Write Operation Page Write Cycle Time: 10ms Max Data Polling for End of Write Detection Hardware and Software Data Protection TTL Compatible Inputs and Outputs 5 Volt Power Supply Low Power CMOS, 10mA Standby Typical Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation FIGURE 1 – PIN CONFIGURATION FOR WE32K32N-XH1X Top View 1 I/O8 I/O9 I/O10 A13 A14 NC NC NC I/O0 I/O1 I/O2 11 22 12 WE2# CS2# GND I/O11 A10 A11 A12 VCC CS1# NC I/O3 33 23 I/O15 I/O14 I/O13 I/O12 OE# NC WE1# I/O7 I/O6 I/O5 I/O4 I/O24 I/O25 I/O26 A6 A7 NC A8 A9 I/O16 I/O17 I/O18 44 34 VCC CS4# WE4# I/O27 A3 A4 A5 WE3# CS3# GND I/O19 55 45 I/O31 I/O30 I/O29 I/O28 A0 A1 A2 56 Pin Description I/O0-31 A0-14 WE1-4# CS1-4# OE# VCC GND NC Data Input/Output Address Inputs Write Enable Chip Selects Output Enable Power Supply Ground Not Connected Block Diagram W E 1 # CS 1 # W E 2 # CS 2 # W E 3 # CS 3 # W E 4 # CS 4 OE# A0-14 32K x 8 32K x 8 I/O23 I/O22 32K x 8 32K x 8 I/O21 I/O20 8 8 8 8 66 I/O0-7 I/O8-15 I/O16-23 I/O24-31 White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 4 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE32K32-XXX FIGURE 2 – PIN CONFIGURATION FOR WE32K32-XG2UX Top View NC A0 A1 A2 A3 A4 A5 CS3# GND CS4# WE1# A6 A7 A8 A9 A10 VCC Pin Description I/O0-31 A0-14 WE1-4# CS1-4# OE# VCC GND NC Data Input/Output Address Inputs Write Enable Chip Selects Output Enable Power Supply Ground Not Connected 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 CS1# OE# CS2# NC WE2# WE3# WE4# W E 3 # CS 3 # NC NC A12 A13 VCC A14 A11 Block Diagram W E 1 # CS 1 # OE# A0-14 32K x 8 32K x 8 W E 2 # CS 2 # W E 4 # CS 4 # 32K x 8 32K x 8 8 8 8 I/O0-7 I/O8-15 I/O16-23 White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 4 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com NC NC NC 8 I/O24-31 White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Voltage on OE# and A9 Symbol TA TSTG VG -55 to +125 -65 to +150 -0.6 to + 6.25 -0.6 to +13.5 Unit °C °C V V CS# H L L X X X OE# X L H H X L WE# X H L X H X WE32K32-XXX TRUTH TABLE Mode Standby Read Write Out Disable Write Inhibit Data I/O High Z Data Out Data In High Z/Data Out NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAPACITANCE TA = +25°C Parameter Address input capacitance OE# capacitance WE# capacitance CS1-4# capacitance Data I/O capacitance Symbol CAD COE CWE CCS CI/O Conditions VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VI/O = 0 V, f = 1.0 MHz Max Unit 50 50 25 40 pF pF pF pF RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temp. (Mil.) Operating Temp. (Ind.) Symbol VCC VIH VIL TA TA Min 4.5 2.0 -0.3 -55 -40 Max 5.5 VCC + 0.3 +0.8 +125 +85 Unit V V V °C °C This parameter is guaranteed by design but not tested. DC CHARACTERISTICS VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C Parameter Input Leakage Current Output Leakage Current Operating Supply Current (x32) Standby Current Output Low Voltage Output High Voltage Symbol ILI ILOx32 ICCx32 ISB VOL VOH Conditions VCC = 5.5, VIN = GND to VCC CS# = VIH, OE# = VIH, VOUT = GND to VCC CS# = VIL, OE# = VIH, f = 5MHz CS# = VIH, OE# = VIH, f = 5MHz IOL = 2.1mA, VCC = 4.5V IOH = -400µA, VCC = 4.5V -80 Min Max 10 10 320 2.5 0.45 2.4 2.4 Min -90 Max 10 10 250 2.5 0.45 2.4 -120 Min Max 10 10 200 2.5 0.45 2.4 -150 Min Max 10 10 150 2.5 0.45 Unit µA µA mA mA V V FIGURE 3 AC Test Circuit AC TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level Typ VIL = 0, VIH = 3.0 5 1.5 1.5 Unit V ns V V ≈ Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75Ω. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 4 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WRITE A write cycle is initiated when OE# is high and a low pulse is on WE# or CS# with CS# or WE# low. The address is latched on the falling edge of CS# or WE# whichever occurs last. The data is latched by the rising edge of CS# or WE#, whichever occurs first. A byte write operation will automatically continue to completion. WE32K32-XXX The WE# line transition from high to low also initiates an internal 150 µsec delay timer to permit page mode operation. Each subsequent WE# transition from high to low that occurs before the completion of the 150 µsec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. WRITE CYCLE TIMING Figures 4 and 5 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS# line low. Write enable consists of setting the WE# line low. The write cycle begins when the last of either CS# or WE# goes low. AC Write Characteristics VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C WRITE CYCLE Write Cycle Parameter Write Cycle Time, TYP = 6ms Address Set-up Time Write Pulse Width (WE# or CS#) Chip Select Set-up Time Address Hold Time Data Hold Time Chip Select Hold Time Data Set-up Time Write Pulse Width High Output Enable Set-up Time Output Enable Hold Time -80 Symbol Min tWC tAS tWP tCS tAH tDH tCSH tDS tWPH tOES tOEH 0 100 0 50 0 0 50 50 10 10 Max 10 0 100 0 50 0 0 50 50 10 10 Min Max 10 30 150 0 100 10 0 100 50 10 10 Min Max 10 30 150 0 100 10 0 100 50 10 10 Min Max 10 ms ns ns ns ns ns ns ns ns ns ns -90 -120 -150 Unit White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 4 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 4 – WRITE WAVEFORMS WE# CONTROLLED WE32K32-XXX t WC OE# t OES ADDRESS t AS CS1-4# t CS WE1-4# t WP t DS DATA IN t WPH t DH t AH tCSH t OEH FIGURE 5 – WRITE WAVEFORMS CS# CONTROLLED t WC OE# t OES ADDRESS t AS WE1 - 4# t CS CS1 - 4# t WP t DS DATA IN t WPH t DH t AH tCSH t OEH White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 4 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs READ The WE32K32-XXX stores data at the memory location determined by the address pins. When CS# and OE# are low and WE# is high, this data is present on the outputs. When CS# and OE# are high, the outputs are in a high impedance state. This 2 line control prevents bus contention. WE32K32-XXX AC Read Characteristics (See Figure 6) VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C READ CYCLE Parameter Read Cycle Time Address Access Time CS Access Time Output Hold from Add. Change, OE# or CS# Output Enable to Output Valid Chip Select or OE# to Output in High Z tRC tACC tACS tOH tOE tDF 0 40 40 Symbol Min 80 80 80 0 50 50 -80 Max Min 90 90 90 0 85 70 -90 Max Min 120 120 120 0 85 70 -120 Max Min 150 150 150 -150 Max ns ns ns ns ns ns Unit FIGURE 6 – READ WAVEFORMS t RC ADDRESS ADDRESS VALID CS# t ACS OE# t ACC OUTPUT HIGH Z t OE t DF t OH OUTPUT VALID NOTES: 1. OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact on tOE or by tACC - tOE after an address change without impact on tACC. 2. tCHZ, tOHZ are specified from OE# or CS# whichever occurs first (CL = 5pF). 3. All I/O transitions are measured ±200 mV from steady state with loading as specified in "Load Test Circuits." White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 4 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DATA POLLING The WE32K32-XXX offers a data polling feature which allows a faster method of writing to the device. Figure 7 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on D7 (for each chip.) Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle. WE32K32-XXX DATA POLLING CHARACTERISTICS VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C Parameter Data Hold Time OE# Hold Time OE# To Output Valid Write Recovery Time Symbol tDH tOEH tOE tWR 0 Min 10 10 100 Max Unit ns ns ns ns FIGURE 7 – DATA POLLING WAVEFORMS WE1-4# CS1-4# t OEH OE# t DH t OE HIGH Z t WR ADDRESS I/O7 White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 4 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PAGE WRITE OPERATION The WE32K32-XXX has a page write operation that allows one to 64 bytes of data to be written into the device and consecutively loads during the internal programming period. Successive bytes may be loaded in the same manner after the first data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 150µs or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. WE32K32-XXX The usual procedure is to increment the least significant address lines from A0 through A5 at each write cycle. In this manner a page of up to 64 bytes can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle. After the 150µs time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. PAGE WRITE CHARACTERISTICS VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C PAGE MODE WRITE CHARACTERISTICS Parameter Write Cycle Time, TYP = 6ms Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High Symbol tWC tDS tDH tWP tBLC tWPH -80 Min 50 0 100 150 50 50 Max 10 Min 50 0 100 150 50 -90 Max 10 Min 100 10 150 150 50 -120 Max 10 Min 100 10 150 150 -150 Max 10 Unit ms ns ns ns µs ns FIGURE 8 – PAGE WRITE WAVEFORMS OE# CS# t WP WE# t DS t WPH t BLC t DH ADDRESS (1) VALID ADDRESS VALID DATA DATA BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE n BYTE n + 1 t WC NOTE: 1. Decoded Address Lines must be valid for the duration of the write. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 4 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE32K32-XXX FIGURE 9 – SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE WRITES ENABLED(2) NOTES: 1. Data Format: I/O7-0 (Hex); Address Format: A14 -A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data to be loaded. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 4 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 10 – SOFTWARE BLOCK DATA PROTECTION DISABLE ALGORITHM(1) WE32K32-XXX SOFTWARE DATA PROTECTION A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the WE32K32-XXX has the feature disabled. Write access to the device is unrestricted. To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device, however, for the duration of tWC. The write protection feature can be disabled by a six byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. Each 32KByte block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a PROM programmer. LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS EXIT DATA PROTECT STATE(3) HARDWARE DATA PROTECTION These features protect against inadvertent writes to the WE32K32-XXX. These are included to improve reliability during normal operation: a) VCC power on delay As VCC climbs past 3.8V typical the device will wait 5msec typical before allowing write cycles. b) c) VCC sense While below 3.8V typical write cycles are inhibited. Write inhibiting Holding OE# low and either CS# or WE# high inhibits write cycles. d) Noise filter Pulses of