WE512K16-140G4IA

White Electronic Designs 512Kx16 CMOS EEPROM MODULE FEATURES Access Time of 140, 150, 200ns Packaging: • 68 lead, 40mm Hermetic CQFP (Package 501) Organized as 4 banks of 128Kx16 Write Endurance 10,000 Cycles Data Retention Ten Years Minimum Military Temperature Range Low Power CMOS Automatic Page Write Operation WE512K16-XG4X Page Write Cycle Time: 10ms Max Data Polling for End of Write Detection Hardware and Software Data Protection TTL Compatible Inputs and Outputs 5 Volt Power Supply 8 Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight - 20 grams typical FIGURE 1 – PIN CONFIGURATION Top View NC A0 A1 A2 A3 A4 A5 CS1# GND CS3# WE# A6 A7 A8 A9 A10 VCC Pin Description I/O0-15 A0-16 WE# CS1-4# OE# VCC GND NC Data Input/Output Address Inputs Write Enable Chip Selects Output Enable +5.0V Power Ground Not Connected 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 NC NC INC NC NC NC NC NC GND NC NC NC NC NC NC NC NC Block Diagram CS 1 # CS 2 # CS 3 # CS 4 # A0-16 OE# WE# 128K x 8 128K x 8 128K x 8 128K x 8 128K x 8 128K x 8 128K x 8 128K x 8 VCC A11 A12 A13 A14 A15 A16 CS2# OE# CS4# NC NC NC NC NC NC NC I/O0-7 I/O8-15 NOTE: CS1-4# are used as bank selects. During reads, only one CSx# can be active at one time. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 1999 Rev. 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Voltage on OE# and A9 Symbol TA TSTG VG -55 to +125 -65 to +150 -0.6 to + 6.25 -0.6 to +13.5 Unit °C °C V V CS# H L L X X X OE# X L H H X L WE# X H L X H X WE512K16-XG4X TRUTH TABLE Mode Standby Read Write Out Disable Write Inhibit Data I/O High Z Data Out Data In High Z/Data Out NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAPACITANCE TA = +25°C Parameter OE capacitance WE capacitance CS1-4 capacitance Data I/O capacitance Address input capacitance Symbol COE CWE CCS CI/O CAD Conditions VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VI/O = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz Max Unit 50 50 25 40 70 pF pF pF pF pF RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temp. (Mil.) Symbol VCC VIH VIL TA Min 4.5 2.0 -0.3 -55 Max 5.5 VCC + 0.3 +0.8 +125 Unit V V V °C This parameter is guaranteed by design but not tested. DC CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Input Leakage Current Output Leakage Current Operating Supply Current (x16) Chip Erase Current Standby Current Output Low Voltage Output High Voltage Symbol ILI ILO ICCx16 ICC1 ISB VOL VOH Conditions VCC = 5.5, VIN = GND to VCC CS# = VIH, OE# = VIH, Vout = GND to VCC CS1# = VIL, OE# = CS2-4# = VIH, f = 5MHz, VCC = 5.5 CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5 CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5 IOL = 2.1mA, VCC = 4.5V IOH = -400µA, VCC = 4.5V Min Max 10 10 160 250 5 0.45 Unit µA µA mA mA mA V V 2.4 NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V FIGURE 4 AC Test Circuit AC TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level Typ VIL = 0, VIH = 3.0 5 1.5 1.5 Unit V ns V V Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75Ω. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 1999 Rev. 2 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WRITE A write cycle is initiated when OE# is high and a low pulse is on WE# or CS# with CS# or WE# low. The address is latched on the falling edge of CS# or WE# whichever occurs last. The data is latched by the rising edge of CS# or WE#, whichever occurs first. A word write operation will automatically continue to completion. WE512K16-XG4X AC WRITE CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Write Cycle Parameter Write Cycle Time, TYP = 6ms Address Set-up Time Write Pulse Width (WE# or CS#) Chip Select Set-up Time Symbol tWC tAS tWP tCS tAH tDH tCSH tDS tOES tOEH tWPH 10 120 0 100 10 0 100 10 10 50 Min Max 10 Unit ms ns ns ns ns ns ns ns ns ns ns WRITE CYCLE TIMING Figures 3 and 4 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS# line low. Write enable consists of setting the WE# line low. The write cycle begins when the last of either CS# or WE# goes low. The WE# line transition from high to low also initiates an internal 150 µsec delay timer to permit page mode operation. Each subsequent WE# transition from high to low that occurs before the completion of the 150 µsec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. Address Hold Time Data Hold Time Chip Select Hold Time Data Set-up Time Output Enable Set-up Time Output Enable Hold Time Write Pulse Width High White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 1999 Rev. 2 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE512K16-XG4X FIGURE 3 – WRITE WAVEFORM WE# CONTROLLED OE# ADDRESS CS1-4# WE# DATA IN FIGURE 4 – WRITE WAVEFORM CS# CONTROLLED OE# ADDRESS WE# CS1-4# DATA IN White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 1999 Rev. 2 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs READ The module stores data at the memory location determined by the address pins. When CS# and OE# are low and WE# is high, this data is present on the outputs. When CS# and OE# are high, the outputs are in a high impedance state. This two line control prevents bus contention. WE512K16-XG4X AC READ CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change, OE# or CS# Output Enable to Output Valid Chip Select or OE# to High Z Output Symbol trc tacc tacs toh toe tdf -140 Min 140 Max 140 140 0 0 50 50 0 0 Min 150 -150 Max 150 150 55 70 0 0 Min 200 -200 Max 200 200 55 70 Unit ns ns ns ns ns ns FIGURE 5 – READ WAVEFORMS ADDRESS CS# OE# OUTPUT Notes: OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact on tOE or by tACC - toe after an address change without impact on tACC. CS1-4# are used as bank selects. During reads, only one CSx# can be active at one time. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 1999 Rev. 2 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DATA POLLING The module offers a data polling feature which allows a faster method of writing to the device. Figure 6 shows the timing diagram for this function. During a word or page write cycle, an attempted read of the last word written will result in the complement of the written data on I/O7 and I/O15. Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle. DATA POLLING CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Data Hold Time OE# Hold Time OE# To Output Valid Write Recovery Time Symbol tDH tOEH tOE tWR 0 Min 10 10 55 Max Unit ns ns ns ns WE512K16-XG4X FIGURE 6 – DATA POLLING WAVEFORM WE1-4# CS1-4# OE# I/O7 ADDRESS White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 1999 Rev. 2 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PAGE WRITE OPERATION The module has a page write operation that allows one to 128 words of data to be written into the device and consecutively loads during the internal programming period. Successive words may be loaded in the same manner after the first data word has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 150µs or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. The usual procedure is to increment the least significant address lines from A0 through A6 at each write cycle. In this manner a page of up to 128 words can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle. After the 150µs time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of words will be written at the same time. The internal programming cycle is the same regardless of the number of words accessed. WE512K16-XG4X PAGE WRITE CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Page Mode Write Characteristics Parameter Write Cycle Time, TYP = 6ms Address Set-up Time Address Hold Time (1) Data Set-up Time Data Hold Time Write Pulse Width Word Load Cycle Time Write Pulse Width High tWC tAS tAH tDS tDH tWP tBLC tWPH 50 0 50 50 0 100 150 Symbol Min Max 10 ms ns ns ns ns ns µs ns Unit 1. Page address must remain valid for duration of write cycle. FIGURE 7 – PAGE MODE WRITE WAVEFORM OE# CS# WE# tAS ADDRESS (1) VALID ADDRESS tAH DATA WORD 0 WORD 1 WORD 2 WORD 3 WORD 126 WORD 127 White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 1999 Rev. 2 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE512K16-XG4X FIGURE 8 – SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM(1) LOAD DATA AAAA TO ADDRESS 5555 LOAD DATA 5555 TO ADDRESS 2AAA LOAD DATA A0A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XXXX TO ANY ADDRESS(4) LOAD LAST WORD TO LAST ADDRESS ENTER DATA PROTECT STATE NOTES: 1. Data Format: I/O7-0 (Hex); Address Format: A14 -A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 words of data to be loaded. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April 1999 Rev. 2 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 9 – SOFTWARE BLOCK DATA PROTECTION DISABLE ALGORITHM(1) WE512K16-XG4X SOFTWARE DATA PROTECTION A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the module has the feature disabled. Write access to the device is unrestricted. To enable software write protection, the user writes three access code words to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three-word write sequence to permit writing. After setting software data protection, any attempt to write to the device without the three-word command sequence will start the internal write timers. No data will be written to the device, however, for the duration of tWC. The write protection feature can be disabled by a six-word write sequence of specific data to specific locations. Power transitions will not reset the software write protection. Each 128K-word block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a PROM programmer. LOAD DATA AAAA TO ADDRESS 5555 LOAD DATA 5555 TO ADDRESS 2AAA LOAD DATA 8080 TO ADDRESS 5555 LOAD DATA AAAA TO ADDRESS 5555 LOAD DATA 5555 TO ADDRESS 2AAA LOAD DATA 2020 TO ADDRESS 5555 LOAD DATA XXXX TO ANY ADDRESS(4) LOAD LAST WORD TO LAST ADDRESS EXIT DATA PROTECT STATE(3) HARDWARE DATA PROTECTION These features protect against inadvertent writes to the module. These are included to improve reliability during normal operation: a) VCC power on delay As VCC climbs past 3.8V typical the device will wait 5 msec typical before allowing write cycles. b) c) VCC sense While below 3.8V typical write cycles are inhibited. Write inhibiting Holding OE# low and either CS# or WE# high inhibits write cycles. d) Noise filter Pulses of